diff options
| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-08-30 02:07:23 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-08-31 07:56:06 +0300 |
| commit | 392572feb01c03c9db2f73993bdbff2b5ed45c38 (patch) | |
| tree | 3f204f92cca23c2820448a4edbc6bf65c54e53ad | |
| parent | 91200c09d38bbc959671b91f5801d1016b409969 (diff) | |
| download | linux-392572feb01c03c9db2f73993bdbff2b5ed45c38.tar.xz | |
drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix
WA to enable HW L1 Banking fix that allows aniso to operate
at full sample rate.
References: HSD#1937670
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Anuj Phogat <anuj.phogat@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170829230723.20898-1-rodrigo.vivi@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_engine_cs.c | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e2908ae34004..1ad22a824921 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -8072,6 +8072,7 @@ enum { #define HSW_SAMPLE_C_PERFORMANCE (1<<9) #define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8) #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5) +#define CNL_FAST_ANISO_L1_BANKING_FIX (1<<4) #define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) #define GEN9_HALF_SLICE_CHICKEN7 _MMIO(0xe194) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index a6ac9d0a4156..4b9b7828802d 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1090,6 +1090,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine) /* WaPushConstantDereferenceHoldDisable:cnl */ WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE); + /* FtrEnableFastAnisoL1BankingFix: cnl */ + WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX); + /* WaEnablePreemptionGranularityControlByUMD:cnl */ ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1); if (ret) |