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authorSelvamani Rajagopal <Selvamani.Rajagopal@onsemi.com>2026-06-12 00:55:41 +0300
committerJakub Kicinski <kuba@kernel.org>2026-06-16 02:32:10 +0300
commit31e56112e6544afba0a50d60251175585ee62943 (patch)
tree85dc33c4be61a43524c99a6c4177b197e9821c27
parenta5a1d11dd3729146abe7420b874bab15870a42b4 (diff)
downloadlinux-31e56112e6544afba0a50d60251175585ee62943.tar.xz
dt-bindings: net: updated interrupt type to be active low, level triggered
According to OPEN Alliance 10BASE-T1x MACPHY Serial Interface (TC6) specification, interrupt type is active low, level triggered interrupt. Specification calls for when interrupt level will be asserted and what condition it is de-asserted. By using edge triggered interrupt, there is a potential chance to miss it, particularly if it is asserted when interrupt is disabled. Level triggered interrupt can't be missed as it gets de-asserted only on interrupt handler taking actions on interrupting conditions. Fixes: ac49b950bea9 ("dt-bindings: net: add Microchip's LAN865X 10BASE-T1S MACPHY") Signed-off-by: Selvamani Rajagopal <Selvamani.Rajagopal@onsemi.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260611-level-trigger-v5-4-4533a9e85ce2@onsemi.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/net/microchip,lan8650.yaml2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/net/microchip,lan8650.yaml b/Documentation/devicetree/bindings/net/microchip,lan8650.yaml
index 61e11d4a07c4..766ff58147ae 100644
--- a/Documentation/devicetree/bindings/net/microchip,lan8650.yaml
+++ b/Documentation/devicetree/bindings/net/microchip,lan8650.yaml
@@ -67,7 +67,7 @@ examples:
pinctrl-names = "default";
pinctrl-0 = <&eth0_pins>;
interrupt-parent = <&gpio>;
- interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
local-mac-address = [04 05 06 01 02 03];
spi-max-frequency = <15000000>;
};