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| author | Mihai Sain <mihai.sain@microchip.com> | 2025-06-25 09:49:33 +0300 |
|---|---|---|
| committer | Claudiu Beznea <claudiu.beznea@tuxon.dev> | 2025-07-05 10:37:28 +0300 |
| commit | 31a820245903f75e6f5d908561fe5d3eab94f057 (patch) | |
| tree | ff4f919ec6fc91743cfad284b223be056434ca76 | |
| parent | ab435d1265e9667c49b91210ef1162a9fb928580 (diff) | |
| download | linux-31a820245903f75e6f5d908561fe5d3eab94f057.tar.xz | |
ARM: dts: microchip: sama5d3: Update the cache configuration for CPU
Add the memory size properties for L1 according with block
diagram from datasheet:
- L1 cache configuration with 32 KB for both data and instruction cache.
[root@sama5d3 ~]$ lscpu
Architecture: armv7l
Byte Order: Little Endian
CPU(s): 1
On-line CPU(s) list: 0
Vendor ID: ARM
Model name: Cortex-A5
Caches (sum of all):
L1d: 32 KiB (1 instance)
L1i: 32 KiB (1 instance)
Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
Link: https://lore.kernel.org/r/20250625064934.4828-3-mihai.sain@microchip.com
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
| -rw-r--r-- | arch/arm/boot/dts/microchip/sama5d3.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/microchip/sama5d3.dtsi b/arch/arm/boot/dts/microchip/sama5d3.dtsi index e95799c17fdb..00ba59ac1968 100644 --- a/arch/arm/boot/dts/microchip/sama5d3.dtsi +++ b/arch/arm/boot/dts/microchip/sama5d3.dtsi @@ -48,6 +48,8 @@ device_type = "cpu"; compatible = "arm,cortex-a5"; reg = <0x0>; + d-cache-size = <0x8000>; // L1, 32 KB + i-cache-size = <0x8000>; // L1, 32 KB }; }; |