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| author | Vivian Wang <wangruikang@iscas.ac.cn> | 2026-04-05 03:42:40 +0300 |
|---|---|---|
| committer | Paul Walmsley <pjw@kernel.org> | 2026-04-05 03:42:40 +0300 |
| commit | 31454cb5f1a37eefe2465601418a978b7668424e (patch) | |
| tree | ba6848e820e530244656ad324e24d1e10194bc8a | |
| parent | fe0cf82fdeb318e8b2c78a4142385f42f467ff8c (diff) | |
| download | linux-31454cb5f1a37eefe2465601418a978b7668424e.tar.xz | |
riscv: smp: Clarify comment "cache" -> "instruction cache"
local_flush_icache_all() only flushes and synchronizes the *instruction*
cache, not the data cache. Since RISC-V does have a cbo.flush
instruction for data cache flush, clarify the comment to avoid
confusion.
Fixes: 58661a30f1bc ("riscv: Flush the instruction cache during SMP bringup")
Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn>
Link: https://patch.msgid.link/20260204-riscv-smp-comment-update-2026-01-v1-2-8b77aa181530@iscas.ac.cn
Signed-off-by: Paul Walmsley <pjw@kernel.org>
| -rw-r--r-- | arch/riscv/kernel/smpboot.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 0e6fe20c69a2..8b628580fe11 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -251,8 +251,8 @@ asmlinkage __visible void smp_callin(void) set_cpu_online(curr_cpuid, true); /* - * Remote cache and TLB flushes are ignored while the CPU is offline, - * so flush them both right now just in case. + * Remote instruction cache and TLB flushes are ignored while the CPU + * is offline, so flush them both right now just in case. */ local_flush_icache_all(); local_flush_tlb_all(); |