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| author | Thomas Gleixner <tglx@linutronix.de> | 2018-10-07 22:56:29 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-10-07 22:56:29 +0300 |
| commit | 2f6affe35c1d79e3524a6475ea2267535a252258 (patch) | |
| tree | 0173a325eb2a804a228b77acffb4de46a6665700 | |
| parent | 9414229c9c53d3604032aa80f3d2e9ba5770cd4a (diff) | |
| parent | 1f174a1a2cdebc65138e6ed1448b842e73200bb5 (diff) | |
| download | linux-2f6affe35c1d79e3524a6475ea2267535a252258.tar.xz | |
Merge branch 'clockevents/4.20' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core
Pull clockevent updates from Daniel Lezcano:
- Prefix file names with timer-* (Daniel Lezcano)
- Remove old CLOCKSOURCE_OF_DECLARE which was replaced by TIMER_OF_DECLARE
(Daniel Lezcano)
- Add reset control for dw_apb (Dinh Nguyen)
- Add the SPDX identifiers for the renesas and sh timers (Kuninori
Morimoto)
- Use %pOFn instead of device_node.name (Rob Herring)
- Fixup 64bits and clocksource width to 32b for sh_cmt (Sergei Shtylyov)
- Add the R-Car gen3 support (Sergei Shtylyov)
| -rw-r--r-- | drivers/clocksource/dw_apb_timer_of.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c index fabaa29cc3a4..db410acd8964 100644 --- a/drivers/clocksource/dw_apb_timer_of.c +++ b/drivers/clocksource/dw_apb_timer_of.c @@ -22,6 +22,7 @@ #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/clk.h> +#include <linux/reset.h> #include <linux/sched_clock.h> static void __init timer_get_base_and_rate(struct device_node *np, @@ -29,6 +30,7 @@ static void __init timer_get_base_and_rate(struct device_node *np, { struct clk *timer_clk; struct clk *pclk; + struct reset_control *rstc; *base = of_iomap(np, 0); @@ -36,6 +38,16 @@ static void __init timer_get_base_and_rate(struct device_node *np, panic("Unable to map regs for %pOFn", np); /* + * Reset the timer if the reset control is available, wiping + * out the state the firmware may have left it + */ + rstc = of_reset_control_get(np, NULL); + if (!IS_ERR(rstc)) { + reset_control_assert(rstc); + reset_control_deassert(rstc); + } + + /* * Not all implementations use a periphal clock, so don't panic * if it's not present */ |