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| author | Tomer Maimon <tmaimon77@gmail.com> | 2025-07-06 16:42:06 +0300 |
|---|---|---|
| committer | Andrew Jeffery <andrew@codeconstruct.com.au> | 2025-08-11 03:08:08 +0300 |
| commit | 2e6028f8faf07e896ea4c2603adb4b06e8cb92fa (patch) | |
| tree | b1d5c2d0a91f6a5696b42a58587a1f6bf2a39f4e | |
| parent | 91f8329e67b482faa1646609f457ea0f74b93a53 (diff) | |
| download | linux-2e6028f8faf07e896ea4c2603adb4b06e8cb92fa.tar.xz | |
arm64: dts: nuvoton: combine NPCM845 reset and clk nodes
Combine the NPCM845 reset and clock controller nodes into a single node
with compatible "nuvoton,npcm845-reset" in nuvoton-common-npcm8xx.dtsi,
using the auxiliary device framework to provide clock functionality.
Update the register range to 0xC4 to cover the shared reset and clock
registers at 0xf0801000.
Remove the separate nuvoton,npcm845-clk node, as the reset driver now
handles clocks via an auxiliary device.
Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Link: https://patch.msgid.link/20250706134207.2168184-2-tmaimon77@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
| -rw-r--r-- | arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi index 5be132f3fd07..400d5c5b71ac 100644 --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi @@ -42,17 +42,12 @@ interrupt-parent = <&gic>; ranges; - rstc: reset-controller@f0801000 { + clk: rstc: reset-controller@f0801000 { compatible = "nuvoton,npcm845-reset"; - reg = <0x0 0xf0801000 0x0 0x78>; - #reset-cells = <2>; + reg = <0x0 0xf0801000 0x0 0xC4>; nuvoton,sysgcr = <&gcr>; - }; - - clk: clock-controller@f0801000 { - compatible = "nuvoton,npcm845-clk"; + #reset-cells = <2>; #clock-cells = <1>; - reg = <0x0 0xf0801000 0x0 0x1000>; }; apb { |