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| author | Dinh Nguyen <dinguyen@kernel.org> | 2025-11-01 22:08:48 +0300 |
|---|---|---|
| committer | Xu Yilun <yilun.xu@linux.intel.com> | 2025-11-10 10:02:56 +0300 |
| commit | 2cf07ffeba5eb893c9f3637cbdbc5dcf95d7eaac (patch) | |
| tree | 36f87aa3c5ff5a16470ba9b0b19ef8e65fcbca4a | |
| parent | 85faa6495f34129778db61d8cd5a80db8ab19261 (diff) | |
| download | linux-2cf07ffeba5eb893c9f3637cbdbc5dcf95d7eaac.tar.xz | |
dt-bindings: fpga: update link for Altera's and AMD partial recon
The link is giving the 404 error, so use the correct link for the
documents
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20251101190848.24271-1-dinguyen@kernel.org
Reviewed-by: Xu Yilun <yilun.xu@intel.com>
Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
| -rw-r--r-- | Documentation/devicetree/bindings/fpga/fpga-region.yaml | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.yaml b/Documentation/devicetree/bindings/fpga/fpga-region.yaml index 7d2d3b7aa4b7..98e7c311c0c8 100644 --- a/Documentation/devicetree/bindings/fpga/fpga-region.yaml +++ b/Documentation/devicetree/bindings/fpga/fpga-region.yaml @@ -215,9 +215,9 @@ description: | FPGA Bridges that exist on the FPGA fabric prior to the partial reconfiguration. -- - [1] www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_partrecon.pdf + [1] https://www.intel.com/programmable/technical-pdfs/683404.pdf [2] tspace.library.utoronto.ca/bitstream/1807/67932/1/Byma_Stuart_A_201411_MAS_thesis.pdf - [3] https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug702.pdf + [3] https://docs.amd.com/v/u/en-US/ug702 properties: $nodename: |