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authorMd Sadre Alam <quic_mdalam@quicinc.com>2026-03-06 14:39:38 +0300
committerBjorn Andersson <andersson@kernel.org>2026-03-26 17:40:54 +0300
commit2a3cd909b8a4c7c4360413cf78e01ba2970fbba4 (patch)
tree552ec5c54d06d4f1cdfd941db16a938d4d88654d
parent0f4990c86810028fb970872d1624a409b91f097d (diff)
downloadlinux-2a3cd909b8a4c7c4360413cf78e01ba2970fbba4.tar.xz
arm64: dts: qcom: ipq5332: Add QPIC SPI NAND controller support
Add device tree nodes for QPIC SPI NAND flash controller support on IPQ5332 SoC. The IPQ5332 SoC includes a QPIC controller that supports SPI NAND flash devices with hardware ECC capabilities and DMA support through BAM (Bus Access Manager). Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260306113940.1654304-3-quic_mdalam@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-rw-r--r--arch/arm64/boot/dts/qcom/ipq5332.dtsi33
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 45fc512a3bab..e227730d99a6 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -423,6 +423,39 @@
status = "disabled";
};
+ qpic_bam: dma-controller@7984000 {
+ compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
+ reg = <0x07984000 0x1c000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ qpic_nand: spi@79b0000 {
+ compatible = "qcom,ipq5332-snand", "qcom,ipq9574-snand";
+ reg = <0x079b0000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>,
+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
+ clock-names = "core",
+ "aon",
+ "iom";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx",
+ "rx",
+ "cmd";
+
+ status = "disabled";
+ };
+
usb: usb@8af8800 {
compatible = "qcom,ipq5332-dwc3", "qcom,dwc3";
reg = <0x08af8800 0x400>;