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| author | Guoniu Zhou <guoniu.zhou@nxp.com> | 2025-12-05 12:07:43 +0300 |
|---|---|---|
| committer | Hans Verkuil <hverkuil+cisco@kernel.org> | 2026-03-25 00:14:44 +0300 |
| commit | 20b522e812a38e9e9fc445f0f4ef3c842a41e53a (patch) | |
| tree | eee16f1c7178f95235af562b3492f33e3b516064 | |
| parent | 77458ad25ec087f0dbf2be37f6e8903715d0fa85 (diff) | |
| download | linux-20b522e812a38e9e9fc445f0f4ef3c842a41e53a.tar.xz | |
media: dt-bindings: nxp,imx8mq-mipi-csi2: Add i.MX8ULP compatible string
The CSI-2 receiver in the i.MX8ULP is almost identical to the version
present in the i.MX8QXP/QM, but i.MX8ULP CSI-2 controller needs pclk
clock as the input clock for its APB interface of Control and Status
register(CSR). So add compatible string fsl,imx8ulp-mipi-csi2 and
increase maxItems of Clocks (clock-names) to 4 from 3. And keep the
same restriction for existing compatible.
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com>
Link: https://patch.msgid.link/20251205-csi2_imx8ulp-v10-1-190cdadb20a3@nxp.com
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
| -rw-r--r-- | Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml | 49 |
1 files changed, 43 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml index 3389bab266a9..4fcfc4fd3565 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml @@ -20,6 +20,7 @@ properties: - enum: - fsl,imx8mq-mipi-csi2 - fsl,imx8qxp-mipi-csi2 + - fsl,imx8ulp-mipi-csi2 - items: - const: fsl,imx8qm-mipi-csi2 - const: fsl,imx8qxp-mipi-csi2 @@ -39,12 +40,16 @@ properties: clock that the RX DPHY receives. - description: ui is the pixel clock (phy_ref up to 333Mhz). See the reference manual for details. + - description: pclk is clock for csr APB interface. + minItems: 3 clock-names: items: - const: core - const: esc - const: ui + - const: pclk + minItems: 3 power-domains: maxItems: 1 @@ -130,21 +135,53 @@ allOf: compatible: contains: enum: - - fsl,imx8qxp-mipi-csi2 + - fsl,imx8mq-mipi-csi2 + then: + properties: + reg: + maxItems: 1 + resets: + minItems: 3 + clocks: + maxItems: 3 + clock-names: + maxItems: 3 + required: + - fsl,mipi-phy-gpr + + - if: + properties: + compatible: + contains: + const: fsl,imx8qxp-mipi-csi2 then: properties: reg: minItems: 2 resets: maxItems: 1 - else: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8ulp-mipi-csi2 + then: properties: reg: - maxItems: 1 + minItems: 2 resets: - minItems: 3 - required: - - fsl,mipi-phy-gpr + minItems: 2 + maxItems: 2 + clocks: + minItems: 4 + clock-names: + minItems: 4 additionalProperties: false |