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| author | Qingqing Zhou <quic_qqzhou@quicinc.com> | 2026-03-12 02:09:53 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-04-03 00:01:43 +0300 |
| commit | 1d5c82f19b8a079767622191fa7478028a6ce79f (patch) | |
| tree | fc1f85cb62980f63c45af9622da6fd763135b3db | |
| parent | a5a5ad9848980e1019ca841fe057afb83debecfa (diff) | |
| download | linux-1d5c82f19b8a079767622191fa7478028a6ce79f.tar.xz | |
arm64: dts: qcom: talos: add the GPU SMMU node
Add the Adreno GPU SMMU node for Talos chipset.
Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
Signed-off-by: Jie Zhang <jie.zhang@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260312-qcs615-spin-2-v8-1-fca38edcd6e6@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/qcom/talos.dtsi | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi index 9be1e523e9ce..7fe354c4710f 100644 --- a/arch/arm64/boot/dts/qcom/talos.dtsi +++ b/arch/arm64/boot/dts/qcom/talos.dtsi @@ -1846,6 +1846,31 @@ #power-domain-cells = <1>; }; + adreno_smmu: iommu@50a0000 { + compatible = "qcom,qcs615-smmu-500", "qcom,adreno-smmu", + "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x050a0000 0x0 0x40000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; + clock-names = "mem", + "hlos", + "iface"; + power-domains = <&gpucc CX_GDSC>; + dma-coherent; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x0 0x06002000 0x0 0x1000>, |