diff options
| author | Imre Deak <imre.deak@intel.com> | 2025-11-17 13:45:33 +0300 |
|---|---|---|
| committer | Mika Kahola <mika.kahola@intel.com> | 2025-11-19 14:24:16 +0300 |
| commit | 1cefc3ac7d8451cebcfce209c53933fb6309e4e5 (patch) | |
| tree | fce30fb14f4d76066e183190576c1a8d18502639 | |
| parent | dca0eb029f5770e18308db966cdeec4bb4b5a659 (diff) | |
| download | linux-1cefc3ac7d8451cebcfce209c53933fb6309e4e5.tar.xz | |
drm/i915/cx0: Sanitize setting the Cx0 PLL use_c10 flag
Sanitize setting the Cx0 PLL use_c10 flag during state computation and
HW readout, making sure they happen the same way in the
intel_c{10,20}pll_calc_state() and intel_c{10,20}pll_readout_hw_state()
functions.
Follow-up changes will add more state computation/HW readout, this
change prepares for those as well.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://lore.kernel.org/r/20251117104602.2363671-4-mika.kahola@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cx0_phy.c | 23 |
1 files changed, 14 insertions, 9 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index e130c96d0018..93b18dc49ee5 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2125,12 +2125,15 @@ static int intel_c10pll_calc_port_clock(struct intel_encoder *encoder, const struct intel_c10pll_state *pll_state); static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder, - struct intel_c10pll_state *pll_state) + struct intel_cx0pll_state *cx0pll_state) { + struct intel_c10pll_state *pll_state = &cx0pll_state->c10; u8 lane = INTEL_CX0_LANE0; intel_wakeref_t wakeref; int i; + cx0pll_state->use_c10 = true; + wakeref = intel_cx0_phy_transaction_begin(encoder); /* @@ -2356,6 +2359,8 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state, const struct intel_c20pll_state * const *tables; int i; + crtc_state->dpll_hw_state.cx0pll.use_c10 = false; + /* try computed C20 HDMI tables before using consolidated tables */ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { if (intel_c20_compute_hdmi_tmds_pll(crtc_state) == 0) @@ -2372,7 +2377,6 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state, intel_cx0pll_update_ssc(encoder, &crtc_state->dpll_hw_state.cx0pll, intel_crtc_has_dp_encoder(crtc_state)); - crtc_state->dpll_hw_state.cx0pll.use_c10 = false; return 0; } } @@ -2439,13 +2443,16 @@ static int intel_c20pll_calc_port_clock(struct intel_encoder *encoder, } static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, - struct intel_c20pll_state *pll_state) + struct intel_cx0pll_state *cx0pll_state) { + struct intel_c20pll_state *pll_state = &cx0pll_state->c20; struct intel_display *display = to_intel_display(encoder); bool cntx; intel_wakeref_t wakeref; int i; + cx0pll_state->use_c10 = false; + wakeref = intel_cx0_phy_transaction_begin(encoder); /* 1. Read current context selection */ @@ -3444,12 +3451,10 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, if (pll_state->tbt_mode) return; - if (intel_encoder_is_c10phy(encoder)) { - intel_c10pll_readout_hw_state(encoder, &pll_state->c10); - pll_state->use_c10 = true; - } else { - intel_c20pll_readout_hw_state(encoder, &pll_state->c20); - } + if (intel_encoder_is_c10phy(encoder)) + intel_c10pll_readout_hw_state(encoder, pll_state); + else + intel_c20pll_readout_hw_state(encoder, pll_state); } static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a, |