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authorAlexandre Courbot <acourbot@nvidia.com>2026-03-06 07:52:46 +0300
committerAlexandre Courbot <acourbot@nvidia.com>2026-03-09 08:29:21 +0300
commit17d7c97f73c7a0bd90bd22cd7441269a6f8a1d72 (patch)
tree685b92c34b0c1f581489676f67c7b657d915c3d3
parent6ef5141114a95746731a65bc384ff4b1c071a3f2 (diff)
downloadlinux-17d7c97f73c7a0bd90bd22cd7441269a6f8a1d72.tar.xz
gpu: nova-core: firmware: fix and explain v2 header offsets computations
There are no offsets in `FalconUCodeDescV2` to give the non-secure and secure IMEM sections start offsets relative to the beginning of the firmware object. The start offsets for both sections were set to `0`, but that is obviously incorrect since two different sections cannot start at the same offset. Since these offsets were not used by the bootloader, this doesn't prevent proper function but is incorrect nonetheless. Fix this by computing the start of the secure IMEM section relatively to the start of the firmware object and setting it properly. Also add and improve comments to explain how the values are obtained. Fixes: dbfb5aa41f16 ("gpu: nova-core: add FalconUCodeDescV2 support") Reviewed-by: Eliot Courtney <ecourtney@nvidia.com> Link: https://patch.msgid.link/20260306-turing_prep-v11-9-8f0042c5d026@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
-rw-r--r--drivers/gpu/nova-core/firmware.rs16
1 files changed, 12 insertions, 4 deletions
diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firmware.rs
index fff5fa263c26..2bb20081befd 100644
--- a/drivers/gpu/nova-core/firmware.rs
+++ b/drivers/gpu/nova-core/firmware.rs
@@ -63,7 +63,8 @@ pub(crate) struct FalconUCodeDescV2 {
pub(crate) interface_offset: u32,
/// Base address at which to load the code segment into 'IMEM'.
pub(crate) imem_phys_base: u32,
- /// Size in bytes of the code to copy into 'IMEM'.
+ /// Size in bytes of the code to copy into 'IMEM' (includes both secure and non-secure
+ /// segments).
pub(crate) imem_load_size: u32,
/// Virtual 'IMEM' address (i.e. 'tag') at which the code should start.
pub(crate) imem_virt_base: u32,
@@ -205,18 +206,25 @@ impl FalconUCodeDescriptor for FalconUCodeDescV2 {
}
fn imem_sec_load_params(&self) -> FalconDmaLoadTarget {
+ // `imem_sec_base` is the *virtual* start address of the secure IMEM segment, so subtract
+ // `imem_virt_base` to get its physical offset.
+ let imem_sec_start = self.imem_sec_base.saturating_sub(self.imem_virt_base);
+
FalconDmaLoadTarget {
- src_start: 0,
- dst_start: self.imem_sec_base,
+ src_start: imem_sec_start,
+ dst_start: self.imem_phys_base.saturating_add(imem_sec_start),
len: self.imem_sec_size,
}
}
fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
Some(FalconDmaLoadTarget {
+ // Non-secure code always starts at offset 0.
src_start: 0,
dst_start: self.imem_phys_base,
- len: self.imem_load_size.checked_sub(self.imem_sec_size)?,
+ // `imem_load_size` includes the size of the secure segment, so subtract it to
+ // get the correct amount of data to copy.
+ len: self.imem_load_size.saturating_sub(self.imem_sec_size),
})
}