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| author | Jay Cornwall <jay.cornwall@amd.com> | 2025-10-23 23:28:39 +0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-01-06 00:59:56 +0300 |
| commit | 1005ab86cf75aec3462c1c58d6efa87871f2843f (patch) | |
| tree | d69a08663a026b35ebb121e5a70958e0cbe8e355 | |
| parent | 864a8b2c1ff9e5767d6bb19854a671c30b3b268f (diff) | |
| download | linux-1005ab86cf75aec3462c1c58d6efa87871f2843f.tar.xz | |
drm/amdkfd: Fix VGPR bank state save in gfx12.1 trap handler
S_SETREG_IMM32_B32 does not apply a mask to the MODE bank bits.
SRC2 is consequently unconditonally cleared during context save.
Use S_SETREG_B32 instead to preserve SRC2.
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Reviewed-by: Lancelot Six <lancelot.six@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index 5c6d533a5956..d82ce2f1e9b9 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -4731,7 +4731,7 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = { 0xb8eff822, 0xb980f822, 0x00000000, 0xb8fa2b01, 0x847a997a, 0x8c6d7a6d, - 0xb9802b01, 0x00000000, + 0xbefa0080, 0xb97a2b01, 0xbefa007e, 0x8b7bff7f, 0x01ffffff, 0xbefe00c1, 0xbeff00c1, 0xee0a407a, diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm index a807e7557e93..d59400d242d1 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm @@ -414,7 +414,8 @@ L_HAVE_VGPRS: s_getreg_b32 s_save_tmp, hwreg(HW_REG_WAVE_MODE, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SIZE) s_lshl_b32 s_save_tmp, s_save_tmp, S_SAVE_PC_HI_DST_SRC0_SRC1_VGPR_MSB_SHIFT s_or_b32 s_save_pc_hi, s_save_pc_hi, s_save_tmp - s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SIZE), 0 + s_mov_b32 s_save_tmp, 0 + s_setreg_b32 hwreg(HW_REG_WAVE_MODE, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SIZE), s_save_tmp #endif // Trap temporaries must be saved via VGPR but all VGPRs are in use. |