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| author | Arnd Bergmann <arnd@arndb.de> | 2024-09-11 11:54:37 +0300 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2024-09-11 11:54:37 +0300 |
| commit | 0e7af99aef5f58b4bae00e45fd1c2626a987f7bb (patch) | |
| tree | bb0c1ad37187a7efede82e808ffa406d643cf753 | |
| parent | b97acde6f9840edbac5c7ea07cba6f10308d24ee (diff) | |
| parent | 61f2e8a3a94175dbbaad6a54f381b2a505324610 (diff) | |
| download | linux-0e7af99aef5f58b4bae00e45fd1c2626a987f7bb.tar.xz | |
Merge tag 'riscv-soc-fixes-for-v6.11-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes
RISC-V soc fixes for v6.11-final
StarFive:
A fix to return one of the clocks on the JH7110 from 1 GHz to 1.5 GHz
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-soc-fixes-for-v6.11-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: starfive: jh7110-common: Fix lower rate of CPUfreq by setting PLL0 rate to 1.5GHz
Link: https://lore.kernel.org/r/20240909-hybrid-groovy-601a33b5b309@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7110-common.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index ca2d44d59d48..c7771b3b6475 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -365,6 +365,12 @@ }; }; +&syscrg { + assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>, + <&pllclk JH7110_PLLCLK_PLL0_OUT>; + assigned-clock-rates = <500000000>, <1500000000>; +}; + &sysgpio { i2c0_pins: i2c0-0 { i2c-pins { |