diff options
| author | Lukasz Laguna <lukasz.laguna@intel.com> | 2025-11-24 22:02:35 +0300 |
|---|---|---|
| committer | Michal Wajdeczko <michal.wajdeczko@intel.com> | 2025-11-25 19:45:23 +0300 |
| commit | 0e72241a53e9188e88bb7b258266bccd615a4d60 (patch) | |
| tree | 9b2f5b75a94e9c45c3bfbb792bd3efa0d545aec8 | |
| parent | 79cb005c7134340d78e2fa8e526a6104fe492695 (diff) | |
| download | linux-0e72241a53e9188e88bb7b258266bccd615a4d60.tar.xz | |
drm/xe/pf: Configure LMTT in MERT
On platforms with standalone MERT, the PF driver needs to program LMTT
in MERT's LMEM_CFG register.
Signed-off-by: Lukasz Laguna <lukasz.laguna@intel.com>
Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com>
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patch.msgid.link/20251124190237.20503-3-lukasz.laguna@intel.com
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_mert_regs.h | 13 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_lmtt.c | 10 |
2 files changed, 22 insertions, 1 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_mert_regs.h b/drivers/gpu/drm/xe/regs/xe_mert_regs.h new file mode 100644 index 000000000000..5b7c15e08747 --- /dev/null +++ b/drivers/gpu/drm/xe/regs/xe_mert_regs.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2025 Intel Corporation + */ + +#ifndef _XE_MERT_REGS_H_ +#define _XE_MERT_REGS_H_ + +#include "regs/xe_reg_defs.h" + +#define MERT_LMEM_CFG XE_REG(0x1448b0) + +#endif /* _XE_MERT_REGS_H_ */ diff --git a/drivers/gpu/drm/xe/xe_lmtt.c b/drivers/gpu/drm/xe/xe_lmtt.c index 4dc1de482eee..f50c5a4b9edf 100644 --- a/drivers/gpu/drm/xe/xe_lmtt.c +++ b/drivers/gpu/drm/xe/xe_lmtt.c @@ -8,6 +8,7 @@ #include <drm/drm_managed.h> #include "regs/xe_gt_regs.h" +#include "regs/xe_mert_regs.h" #include "xe_assert.h" #include "xe_bo.h" @@ -17,6 +18,7 @@ #include "xe_mmio.h" #include "xe_res_cursor.h" #include "xe_sriov.h" +#include "xe_tile.h" #include "xe_tile_sriov_printk.h" /** @@ -196,16 +198,22 @@ static void lmtt_setup_dir_ptr(struct xe_lmtt *lmtt) struct xe_device *xe = tile_to_xe(tile); dma_addr_t offset = xe_bo_main_addr(lmtt->pd->bo, XE_PAGE_SIZE); struct xe_gt *gt; + u32 config; u8 id; lmtt_debug(lmtt, "DIR offset %pad\n", &offset); lmtt_assert(lmtt, xe_bo_is_vram(lmtt->pd->bo)); lmtt_assert(lmtt, IS_ALIGNED(offset, SZ_64K)); + config = LMEM_EN | REG_FIELD_PREP(LMTT_DIR_PTR, offset / SZ_64K); + for_each_gt_on_tile(gt, tile, id) xe_mmio_write32(>->mmio, GRAPHICS_VER(xe) >= 20 ? XE2_LMEM_CFG : LMEM_CFG, - LMEM_EN | REG_FIELD_PREP(LMTT_DIR_PTR, offset / SZ_64K)); + config); + + if (xe_device_has_mert(xe) && xe_tile_is_root(tile)) + xe_mmio_write32(&tile->mmio, MERT_LMEM_CFG, config); } /** |