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authorBjorn Andersson <andersson@kernel.org>2026-01-03 17:41:23 +0300
committerBjorn Andersson <andersson@kernel.org>2026-01-03 17:41:23 +0300
commit0ba9cc9f6ffefb28e55ba8ffe1caed968d863a38 (patch)
tree0a79ff592bff77a3a87e5ec3448f865570a14bfe
parent0e31dcfefd21ed76ff1b2d05647cd34336ab9772 (diff)
parent5fc25d64c43c1e25a1a0184a894ab0721c6a524b (diff)
downloadlinux-0ba9cc9f6ffefb28e55ba8ffe1caed968d863a38.tar.xz
Merge branch '20260103-ufs_symbol_clk-v2-1-51828cc76236@oss.qualcomm.com' into arm64-for-6.20
Merge the addition of UFS PHY clocks to the Hamoa GCC binding through a topic branch, to avoid DeviceTree validation warnings, and later allow referencing the added clock constants.
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml8
-rw-r--r--include/dt-bindings/clock/qcom,x1e80100-gcc.h3
2 files changed, 10 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
index 1b15b5070954..881a5dd8d06f 100644
--- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
@@ -62,6 +62,9 @@ properties:
- description: USB4_1 PHY max PIPE clock source
- description: USB4_2 PHY PCIE PIPE clock source
- description: USB4_2 PHY max PIPE clock source
+ - description: UFS PHY RX Symbol 0 clock source
+ - description: UFS PHY RX Symbol 1 clock source
+ - description: UFS PHY TX Symbol 0 clock source
power-domains:
description:
@@ -121,7 +124,10 @@ examples:
<&usb4_1_phy_pcie_pipe_clk>,
<&usb4_1_phy_max_pipe_clk>,
<&usb4_2_phy_pcie_pipe_clk>,
- <&usb4_2_phy_max_pipe_clk>;
+ <&usb4_2_phy_max_pipe_clk>,
+ <&ufs_phy_rx_symbol_0>,
+ <&ufs_phy_rx_symbol_1>,
+ <&ufs_phy_tx_symbol_0>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
index 62aa12425592..d905804e6465 100644
--- a/include/dt-bindings/clock/qcom,x1e80100-gcc.h
+++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
@@ -387,6 +387,9 @@
#define GCC_USB4_2_PHY_RX0_CLK_SRC 377
#define GCC_USB4_2_PHY_RX1_CLK_SRC 378
#define GCC_USB4_2_PHY_SYS_CLK_SRC 379
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 380
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 381
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 382
/* GCC power domains */
#define GCC_PCIE_0_TUNNEL_GDSC 0