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authorJagadeesh Kona <quic_jkona@quicinc.com>2025-08-22 12:26:35 +0300
committerBjorn Andersson <andersson@kernel.org>2025-09-01 21:03:31 +0300
commit086079090571910ead0510e756cea14ff3759d4e (patch)
tree784dfe91b2c9d900360cb0108f326751778a4862
parentd49e683574537d416aa0fb022d800430e7c045b6 (diff)
downloadlinux-086079090571910ead0510e756cea14ff3759d4e.tar.xz
arm64: dts: qcom: sm8650: Additionally manage MXC power domain in videocc
Videocc requires both MMCX and MXC rails to be powered ON to configure the video PLLs on SM8650 platform. Hence add MXC power domain to videocc node on SM8650. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-3-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-rw-r--r--arch/arm64/boot/dts/qcom/sm8650.dtsi3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 7ffdd26ff614..e3eabd5d17f8 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -5236,7 +5236,8 @@
reg = <0 0x0aaf0000 0 0x10000>;
clocks = <&bi_tcxo_div2>,
<&gcc GCC_VIDEO_AHB_CLK>;
- power-domains = <&rpmhpd RPMHPD_MMCX>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>,
+ <&rpmhpd RPMHPD_MXC>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;