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authorLeo Wang <leo.jt.wang@gmail.com>2025-10-21 06:15:39 +0300
committerAndrew Jeffery <andrew@codeconstruct.com.au>2025-12-14 11:37:16 +0300
commit033089ff268b825316183aea655b0c8e99b11faf (patch)
treef58503ed467c48cffa247ba94436cfa7bf98937f
parent124b74e42ed3c4f1a72abbf71ff0a1a8f168ad6f (diff)
downloadlinux-033089ff268b825316183aea655b0c8e99b11faf.tar.xz
ARM: dts: aspeed: clemente: Add EEPROMs for boot and data drive FRUs
Add EEPROM devices on the I2C buses used for the boot and data NVMe drives. These EEPROMs store FRU information for each drive, allowing the BMC to identify. Signed-off-by: Leo Wang <leo.jt.wang@gmail.com> Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
-rw-r--r--arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts30
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts
index 450446913e36..885c50a7d665 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts
@@ -311,6 +311,12 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
+
+ // HDD NVMe SSD FRU 0
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
};
i2c0mux0ch1mux0ch1: i2c@1 {
@@ -323,6 +329,12 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
+
+ // HDD NVMe SSD FRU 1
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
};
i2c0mux0ch1mux0ch3: i2c@3 {
@@ -493,6 +505,12 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
+
+ // HDD NVMe SSD FRU 2
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
};
i2c0mux3ch1mux0ch1: i2c@1 {
@@ -505,6 +523,12 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
+
+ // HDD NVMe SSD FRU 3
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
};
i2c0mux3ch1mux0ch3: i2c@3 {
@@ -619,6 +643,12 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
+
+ // BOOT DRIVE FRU
+ eeprom@53 {
+ compatible = "atmel,24c02";
+ reg = <0x53>;
+ };
};
i2c0mux5ch2: i2c@2 {