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| author | Nicholas Piggin <npiggin@gmail.com> | 2019-02-26 11:51:10 +0300 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2019-02-26 15:28:26 +0300 |
| commit | 38555434a910a657ba6d7d06a4fe0376c8b04685 (patch) | |
| tree | cd1b893915eff74c542d57bc3187e59bebdf22cb /.get_maintainer.ignore | |
| parent | e779fc93643c1181b0164745a537986a525850ca (diff) | |
| download | linux-38555434a910a657ba6d7d06a4fe0376c8b04685.tar.xz | |
powerpc/64s: Fix data interrupts vs d-side MCE reentrancy
Handlers for interrupts that set DAR / DSISR, set MSR[RI] before those
SPRs are read. If a d-side machine check hits in this window, DAR /
DSISR will be clobbered silently, leading to random corruption.
Fix this by having handlers save those registers before setting MSR[RI].
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to '.get_maintainer.ignore')
0 files changed, 0 insertions, 0 deletions