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path: root/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
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2024-11-15UefiCpuPkg: Fix unchecked returns and potential integer overflowskenlautner1-1/+1
Resolves several issues in UefiCpuPkg related to: 1. Unchecked returns leading to potential NULL or uninitialized access. 2. Potential unchecked integer overflows. 3. Incorrect comparison between integers of different sizes. Co-authored-by: kenlautner <85201046+kenlautner@users.noreply.github.com> Signed-off-by: Chris Fernald <chfernal@microsoft.com>
2024-04-30UefiCpuPkg/Library: Cleanup debug message in LmceSupportJiaxin Wu1-4/+1
ProcessorNumber 0 is not always BSP. Debug message based on 0 of ProcessorNumber is incorrect. This patch is to clean the debug message in LmceSupport directly. Cc: Ray Ni <ray.ni@intel.com> Cc: Zeng Star <star.zeng@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Zeng Star <star.zeng@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2021-12-07UefiCpuPkg: Apply uncrustify changesMichael Kubacki1-8/+13
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the UefiCpuPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2021-12-07UefiCpuPkg: Change OPTIONAL keyword usage styleMichael D Kinney1-4/+4
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3760 Update all use of ', OPTIONAL' to ' OPTIONAL,' for function params. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2021-06-21UefiCpuPkg/CpuCommonFeaturesLib: Correct the CPU location checkDaoxiang Li1-2/+2
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3424 Processor location information check needs to updated When Core 0 is disabled. In C1e.c, change MSR_FEATURE_CONFIG to MSR_NEHALEM_POWER_CTL in comments to match the correct MSR name. Signed-off-by: Daoxiang Li <daoxiang.li@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
2020-08-03UefiCpuPkg/CpuCommonFeaturesLib: Fix spelling mistakeMichael D Kinney1-1/+1
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2357 Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2019-08-20UefiCpuPkg/CpuCommonFeaturesLib: Use new macros.Dong, Eric1-15/+10
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040 Below code is current implementation: if (MsrRegister[ProcessorNumber].Bits.Lock == 0) { CPU_REGISTER_TABLE_WRITE_FIELD ( ProcessorNumber, Msr, MSR_IA32_FEATURE_CONTROL, MSR_IA32_FEATURE_CONTROL_REGISTER, Bits.Lock, 1 ); } 1. In first normal boot, the Bits.Lock is 0, 1 will be added into the register table and then will set to the MSR. 2. Trig warm reboot, MSR value preserves. After normal boot phase, the Bits.Lock is 1, so it will not be added into the register table during the warm reboot phase. 3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is not added in register table, so it's still 0 after resume. This is not an expect behavior. The expect value is the value should always 1 after booting or resuming from S3. The root cause for this issue is 1. driver bases on current value to insert the "set value action" to the register table. 2. Some MSRs may reserve their value during warm reboot. The solution for this issue is using new added macros for the MSRs which preserve value during warm reboot. Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
2019-06-06UefiCpuPkg CpuCommFeaturesLib: Fix ASSERT if LMCE is supportedStar Zeng1-1/+1
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1829 There will be ASSERT if LMCE is supported as below. DXE_ASSERT!: [CpuFeaturesDxe] XXX\UefiCpuPkg\Library\CpuCommonFeaturesLib\MachineCheck.c (342): ConfigData != ((void *) 0) The code should get Config Data and FeatureControlGetConfigData could be used. This issue is there since the code was added at the commit below. Revision: 3d6275c1137c9633ce24e31522b71105367bd6a0 Date: 2017/8/4 8:46:41 UefiCpuPkg CpuCommonFeaturesLib: Enable LMCE feature. The commits below are also related to move the code. Revision: 023387144299741d727521b425ef443438aecc1f Date: 2017/9/1 10:12:38 UefiCpuPkg/Lmce.c Remove useless file. Revision: 306a5bcc6b0170d28b0db10bd359817bb4b1db9f Date: 2017/8/17 11:40:38 UefiCpuPkg/CpuCommonFeaturesLib: Merge machine check code to same file. So, the code may not be tested at all on a platform that supports LMCE. BTW: A typo in LmceInitialize is also fixed. The typo is introduced by the commit below. Revision: d28daaddb3e732468e930a809d3d3943a5de9558 Date: 2018/10/17 9:24:05 UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2019-04-09UefiCpuPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney1-7/+1
https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
2018-10-26UefiCpuPkg/CpuCommonFeaturesLib: Remove white space at line end.Eric Dong1-1/+1
Remove extra white space at the end of line. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Dandan Bi <dandan.bi@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2018-10-22UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info.Eric Dong1-0/+38
Because MSR has scope attribute, driver has no needs to set MSR for all APs if MSR scope is core or package type. This patch updates code to base on the MSR scope value to add MSR to the register table. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2018-06-28UefiCpuPkg: Clean up source filesLiming Gao1-1/+1
1. Do not use tab characters 2. No trailing white space in one line 3. All files must end with CRLF Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Liming Gao <liming.gao@intel.com>
2018-03-08UefiCpuPkg/CpuCommonFeaturesLib: Fix coding style issueDandan Bi1-1/+1
Boolean values do not need to use explicit comparisons to TRUE or FALSE. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2018-02-09UefiCpuPkg/FeaturesLib: don't init MCi_CTL/STATUS when MCA's disabledRuiyu Ni1-15/+17
Today's McaInitialize() doesn't check State value before initialize MCi_CTL and MCi_STATUS. The patch fixes this issue by only initializing the two kinds of MSRs when State is enabled. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2018-01-15UefiCpuPkg: Enhance feature dependency checkSong, BinX1-0/+3
Enhance MCA feature dependency check base on SDM pseudocode example 15-1. Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Bell Song <binx.song@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2017-08-28UefiCpuPkg/CpuCommonFeaturesLib: Merge machine check code to same file.Eric Dong1-0/+81
Original code about Local Machine Check exception feature saves in a discrete file, because features related to machine check architecture all saved in MachineCheck.c file. This patch moved LMCE logic to same file for easy maintenance. Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2017-04-05UefiCpuPkg/CpuFeatures: Change files format to DOSJeff Fan1-231/+231
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2017-03-22UefiCpuPkg: Add NULL CPU Common Features Library instanceJeff Fan1-0/+231
This NULL CPU common Features Library instance will register some CPU features defined in Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR). Add PCD PcdCpuClockModulationDutyCycle and PcdIsPowerOnReset consumed by NULL CPU Common Features Library instance. v2: 1. Using MSR_IA32_EFER to enable/disable NX feature instead of using MSR_IA32_MISC_ENABLE. 2. Fix bug that SMX and VMX feature is swapped. v3: 1. Add AesniGetConfigData() to get current register state. v5: Move MSR reading from AesniGetConfigData() to AesniSupport(). Cc: Feng Tian <feng.tian@intel.com> Cc: Michael Kinney <michael.d.kinney@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
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