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2026-08-28MdePkg: Update LoongArch64 page table bit mapChao Li1-6/+10
2026-08-28MdePkg: Update LoongArch64 CpuCfg register definitionsChao Li1-34/+85
2026-06-12MdePkg/Svsm: add SVSM_UEFI_MM_PROTOCOLGerd Hoffmann1-0/+6
2026-05-08MdePkg: Fix Spelling Errors in CommentsOliver Smith-Denny4-7/+7
2026-03-18MdePkg: Make X64 Page Table Definitions PublicOliver Smith-Denny1-0/+176
2026-03-11MdePkg: Add AMD CPUID Extended Topology definitionJiaxin Wu1-0/+117
2026-02-24MdePkg: Replace include guards with #pragma onceMichael Kubacki42-167/+42
2026-02-02MdePkg: Replace non-ASCII characters with ASCIIdhiineshm1-3/+3
2025-09-09MdePkg: Add the COHERENCY_SFW_NO CPUID bit fieldTom Lendacky1-2/+7
2025-03-16MdePkg/AmdSev: Add SVSM protocol vTPM call numbersOliver Steffen1-0/+6
2025-03-16MdePkg/AmdSev: Add SVSM protocol call numbersOliver Steffen1-0/+19
2024-11-12MdePkg: Added definition of AMD specific public MSRsKun Qin2-0/+56
2024-10-04MdePkg/BaseLib: RISC-V: Add FPU CSR constantsHeinrich Schuchardt1-0/+4
2024-08-30MdePkg: Remove the old name of LoongArch CSR 0x20Chao Li1-1/+0
2024-08-30MdePkg: Rename the LoongArch CSR 0x20 registerChao Li1-0/+1
2024-07-15MdePkg/Library: Add RISCV64 support to BaseRngLibDhaval1-0/+10
2024-07-12MdePkg/StmApi.h: Add SMM_REV_ID definition for STM headerMichael Kubacki1-0/+2
2024-07-04MdePkg/Register/Amd: Define all bits from MSR_SEV_STATUS_REGISTERAlexey Kardashevskiy1-4/+91
2024-06-26MdePkg/ArchitecturalMsr.h: add #defines for MTRR cache typesGerd Hoffmann1-0/+7
2024-06-18MdePkg/Include: Update AMD specification referencesPaul Grimes2-2/+2
2024-06-18MdePkg/Include: Update Msr.h header guard definePaul Grimes1-2/+2
2024-06-18MdePkg/Include: Remove deprecated AMD SEV-SNP header filePaul Grimes1-153/+0
2024-06-18MdePkg/Include: Update reference to SEV-SNP header filePaul Grimes1-1/+1
2024-06-18MdePkg/Include: Add AMD SEV-SNP header filePaul Grimes1-0/+153
2024-06-05MdePkg: Remove non-ASCII characters from header fileNeo Hsueh2-6/+6
2024-04-17MdePkg/Register/Amd: Define the SVSM related informationTom Lendacky4-2/+156
2024-04-17MdePkg: Avoid hardcoded value for number of Page State Change entriesTom Lendacky1-3/+4
2024-04-17MdePkg: GHCB APIC ID retrieval support definitionsTom Lendacky1-1/+11
2024-02-06MdePkg: Add LoongArch Cpucfg functionChao Li1-0/+565
2024-02-06MdePkg: Add the header file named Csr.h for LoongArch64Chao Li1-0/+263
2024-01-31MdePkg: Adds AMD Extended CPU topology CPUIDAbdul Lateef Attar1-1/+22
2024-01-11MdePkg/BaseLib: RISC-V: Add function to update stimecmp registerSunil V L1-0/+3
2023-07-15MdePkg/Register: RISC-V: Add satp mode bits shift definitionTuan Phan1-3/+4
2023-07-03MdePkg: Adds AMD SMRAM save state mapAbdul Lateef Attar1-0/+194
2023-06-15UefiCpuPkg: RISC-V: TimerLib: Fix delay function to use 64-bitTuan Phan1-1/+0
2023-04-01MdePkg: Add TME-MK related CPUID and MSR definitionsRay Ni2-3/+112
2023-02-16MdePkg/Register: Add register definition header files for RISC-VSunil V L2-0/+144
2022-04-02MdePkg: Update Cpuid.h for TdxMin Xu1-2/+33
2021-12-09MdePkg/GHCB: increase the GHCB protocol max versionBrijesh Singh1-1/+1
2021-12-07MdePkg: Apply uncrustify changesMichael Kubacki32-8630/+6991
2021-10-28MdePkg Cpuid.h: Define CPUID.(EAX=7,ECX=0):EDX[30]Zeng, Star1-2/+2
2021-05-29MdePkg/Register/Amd: define GHCB macros for SNP AP creationTom Lendacky1-0/+84
2021-05-29MdePkg/Register/Amd: define GHCB macro for the Page State ChangeBrijesh Singh2-0/+48
2021-05-29MdePkg/Register/Amd: define GHCB macro for Register GPA structureBrijesh Singh1-0/+7
2021-05-29MdePkg/Register/Amd: define GHCB macros for hypervisor feature detectionBrijesh Singh2-0/+15
2021-05-29MdePkg/Register/Amd: realign macros with more space for future expansionBrijesh Singh2-11/+11
2021-05-29MdePkg/Register/Amd: expand the SEV MSR to include the SNP definitionBrijesh Singh1-1/+6
2021-04-20MdePkg/Cpuid.h: Define new element in CPUID Leaf(07h) data structure.Jason1-3/+11
2021-01-26MdePkg/Cpuid.h: Change and add some macro definitions.Lou, Yun1-5/+14
2021-01-19MdePkg/Cpuid.h: Add CPUID_HYBRID_INFORMATION Leaf(1Ah).Jason Lou1-1/+62
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