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In BuildAdmaDescTable(), Index and Entries were UINT64. Using a 64-bit
Index for array subscripting `Trb->Adma32Desc[Index]`,
`Trb->Adma64V3Desc[Index]`, and `Trb->Adma64V4Desc[Index]` generates
64-bit multiplication on 32-bit architectures (IA32).
Change Index and Entries to UINTN so array indexing and table size
calculations use native integer math.
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
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https://github.com/github/codeql/blob/codeql-cli-2.7.3/csharp/ql/src/API%20Abuse/UncheckedReturnValue.qhelp
When a function has a return status, it should
be checked to verify the function completed successfully.
Failing to check the return status can result in null pointer
dereferences or use of uninitialized variables.
Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
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https://github.com/github/codeql/blob/codeql-cli-2.7.3/cpp/ql/src/Critical/MissingNullTest.qhelp
For items which allocate memory, or get a pointer from another
structure, it is important to validate that the pointers
are not null before they are dereferenced.
Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
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https://codeql.github.com/codeql-query-help/cpp/cpp-comparison-with-wider-type
If the narrow type (smaller range) is compared against a wide type
(larger range), the narrow value may overflow before reaching the wide
value. This can cause unexpected behavior, such as:
Infinite loops (loop condition never becomes false).
Incorrect logic (comparison results are misleading).
Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
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Dispatch Shutdown Notification to every NVMe first, then polling
every NVMe t omaake sure all NVMe's shutdown processing is
completed.This will help to save a lot time when BIOS trigger
reset for Servers whose have many NVMes. Tested on a platform
with AMD EPYC cpu with 26 NVMes, this method reduce reset time
from 3 minutes to 10 seconds.
Signed-off-by: Theo <theo.tao@foxmail.com>
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When UpdatePciInfo() downgrades a PciBarTypePMem64 BAR to a 32-bit type
via EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL, it unconditionally
assigns PciBarTypePMem32 regardless of SpecificFlag, placing the BAR in
the prefetchable bridge window even when the platform intended the
non-prefetchable window.
The ACPI resource descriptor's SpecificFlag field encodes the intended
prefetchability of the constrained resource, using the bit:
EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE.
Fix this by checking the bit in SpecificFlag to select PciBarTypePMem32 or
PciBarTypeMem32, consistent with DumpPpbPaddingResource() in
PciEnumeratorSupport.c that uses the bit as the sole discriminator
between the two 32-bit BAR types.
Signed-off-by: Phil Noh <Phil.Noh@amd.com>
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In arguments of EFI_PCI_IO_PROTOCOL member functions, replace the
EfiPciWidth* enum literals from
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH with the matching
EfiPciIoWidth* values from EFI_PCI_IO_PROTOCOL_WIDTH.
This keeps the call sites aligned with the protocol they actually use.
The old values were copied from EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL code,
so they obscured the intent of the calls and relied on an explicit
cast.
This mimics commit 8ba64a9a9417 ("UefiPayloadPkg: Fix build failure with
CLANGPDB").
Generated by coccinelle script.
``` smpl
@initialize:python@
@@
def to_pci_io_width(name):
return name.replace("EfiPciWidth", "EfiPciIoWidth", 1)
@normalize@
typedef EFI_PCI_IO_PROTOCOL;
typedef EDKII_PCI_DEVICE_PPI;
type T =~ "^EFI_PCI_IO_PROTOCOL_WIDTH$";
EFI_PCI_IO_PROTOCOL *x;
EDKII_PCI_DEVICE_PPI *y;
identifier bad =~ "EfiPciWidth(Uint|FifoUint|FillUint)(8|16|32|64)";
identifier top_op =~ "^(PollMem|PollIo|CopyMem)$";
identifier space =~ "^(Mem|Io|Pci)$";
identifier rw =~ "^(Read|Write)$";
fresh identifier good = script:python(bad) { to_pci_io_width(bad) };
expression first;
expression list rest;
@@
(
x->top_op
|
y->PciIo.top_op
|
x->space.rw
|
y->PciIo.space.rw
) (
first,
- (T)bad
+ good
,
rest
)
```
Verified with:
- `build -p MdeModulePkg/MdeModulePkg.dsc -m MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf -a IA32 -b DEBUG -t GCC`
- `build -p MdeModulePkg/MdeModulePkg.dsc -m MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf -a X64 -b DEBUG -t GCC`
Signed-off-by: Mingjie Shen <shen497@purdue.edu>
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IsPciDeviceRejected() masks BAR value with 0xFFFFFFF0 before testing
the type bits (2:1) that mark a 64-bit memory BAR, essentially clears
them, making the 64-bit BAR code path unreachable and treated as if
it were 32-bit.
The function rejects a device when BAR looks unprogrammed by comparing
if its size mask equals its value. When a 64-bit BAR is mistaken for a
32-bit one, only its lower part is compared, possibly leading a valid
BAR being falsely rejected. For example, a 2G BAR with size mask
0x80000000 at 0x180000000 matches and the device is dropped.
This code runs during light enumeration (PciEnumeratorLight), used when
PCI resources are already assigned by the platform (e.g. Xen HVM, where
hvmloader programs the BARs). The rejected device never receives a
PciIo handle, so no driver can bind to it. For example, a virtio-vga
with a 64-bit BAR vanishes under OVMF on Xen, leaving the guest with
no graphics output.
Fix by testing the type bits on the raw BAR value before masking.
Signed-off-by: Jiaqing Zhao <Zhao.Jiaqing@amd.com>
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Update recent changes in MdeModulePkg to follow the latest EDK II
C Coding Standards Specification (5.3) to use '#pragma once' instead
of traditional macro-based include guards in header files.
https://tianocore-docs.github.io/edk2-CCodingStandardsSpecification/draft/5_source_files/53_include_files.html#53-include-files
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
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CxlDxe is currently compiled as part of the MdeModulePkg
IA32 CI. When running CI with VS2022 version 14.44.35228.0,
the CI build fails with:
CxlDxe.lib(CxlDxe.obj) : unresolved external symbol __allmul
CxlDxe(CxlDxe.obj) : unresolved external symbol __allshl
CxlDxe is not intended to run on IA32 DXE systems, as such
systems are legacy, but until edk2 drops build support for
IA32 DXE (or at least CI for it), the build needs to work.
This fixes the 64 bit multiplication/shifting that occurs
in CxlDxe to use the BaseLib functions that avoid the
compiler intrinsics.
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
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The PCI specification normally requires function 0 to be present
before functions 1 through 7 are used. PciBusDxe therefore stops
scanning a slot when probing function 0 fails.
Some virtualized PCI topologies may expose selected non-zero functions
to a guest while function 0 is hidden. Add an opt-in Feature PCD so a
platform can continue collecting device information for functions 1
through 7 when function 0 is absent.
The default remains FALSE, so existing platform behavior is unchanged
unless the platform explicitly enables the PCD.
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
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In CxlWriteRegblockRegisters() and PciUefiMemReadUInt32Array(),
Status is only assigned inside the for loop but is returned after
the loop exits, causing an uninitialized variable warning. Return
immediately on error to fix this.
Signed-off-by: Tuan Phan <tuan.phan@oss.qualcomm.com>
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No functional change.
Signed-off-by: Qihang Gao <gaoqihang@loongson.cn>
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Replace manual alignment checks with IS_ALIGNED() and
ADDRESS_IS_ALIGNED().
Convert the following bitmask and modulo forms:
- ((E & ((PowOf2Expr) - ONE)) == ZERO)
- ((E & ((PowOf2Expr) - ONE)) != ZERO)
- ((E % (PowOf2Expr)) == ZERO)
- ((E % (PowOf2Expr)) != ZERO)
to the corresponding helper macro forms:
+ IS_ALIGNED (E, PowOf2Expr)
+ !IS_ALIGNED (E, PowOf2Expr)
PowOf2Expr is limited to known power-of-two expressions, including
SIZE_* and BASE_* macros, EFI_PAGE_SIZE, CPU_STACK_ALIGNMENT,
RUNTIME_PAGE_ALLOCATION_GRANULARITY, sizeof() of UEFI integer types
(e.g. BOOLEAN, CHAR16, UINT32, UINTN) and pointer types, and 1 << E1
expressions.
Address checks that cast the checked value to UINTN are written with
ADDRESS_IS_ALIGNED().
The change was generated with the Coccinelle semantic patch below.
```smpl
@power_of_2_expr@
expression PowOf2Expr;
expression E1;
typedef BOOLEAN, CHAR8, CHAR16, INT8, UINT8, INT16, UINT16, INT32, UINT32, INT64, UINT64, INTN, UINTN;
type ScalarType = { BOOLEAN, CHAR8, CHAR16, INT8, UINT8, INT16, UINT16, INT32, UINT32, INT64, UINT64, INTN, UINTN };
type AnyType;
type PointerType = AnyType *;
idexpression ScalarType ScalarValue;
idexpression PointerType PointerValue;
constant SizeBase =~ "^(SIZE|BASE)_(1|2|4|8|16|32|64|128|256|512)[KMGTPE]B$";
constant NamedPowerOf2 =~ "^(EFI_PAGE_SIZE|CPU_STACK_ALIGNMENT|RUNTIME_PAGE_ALLOCATION_GRANULARITY)$";
constant ONE = {1, 1U, 1u};
@@
(
(
SizeBase
|
NamedPowerOf2
|
ONE << E1
|
sizeof (ScalarType)
|
sizeof (PointerType)
|
sizeof (ScalarValue)
|
sizeof (PointerValue)
)
&
PowOf2Expr
)
@aligned depends on power_of_2_expr disable is_zero,isnt_zero@
expression E;
expression power_of_2_expr.PowOf2Expr;
constant ONE = {1, 1U, 1u};
constant ZERO = {0, 0U, 0u};
@@
(
((E & (E - ONE)) == ZERO)
|
- ((E & ((PowOf2Expr) - ONE)) == ZERO)
+ IS_ALIGNED (E, PowOf2Expr)
|
((E & (E - ONE)) != ZERO)
|
- ((E & ((PowOf2Expr) - ONE)) != ZERO)
+ !IS_ALIGNED (E, PowOf2Expr)
|
- ((E % (PowOf2Expr)) == ZERO)
+ IS_ALIGNED (E, PowOf2Expr)
|
- ((E % (PowOf2Expr)) != ZERO)
+ !IS_ALIGNED (E, PowOf2Expr)
)
@address_is_aligned@
typedef UINTN;
expression *Address;
expression Alignment;
@@
- IS_ALIGNED ((UINTN) Address, Alignment)
+ ADDRESS_IS_ALIGNED (Address, Alignment)
@normalize_aligned disable paren expression@
expression E, SZ;
@@
(
- (IS_ALIGNED (E, SZ))
+ IS_ALIGNED (E, SZ)
|
- (!IS_ALIGNED (E, SZ))
+ !IS_ALIGNED (E, SZ)
)
@normalize_macro_args disable paren expression@
expression E, SZ;
@@
(
- IS_ALIGNED ((E), SZ)
+ IS_ALIGNED (E, SZ)
|
- IS_ALIGNED (E, (SZ))
+ IS_ALIGNED (E, SZ)
)
```
Signed-off-by: Mingjie Shen <shen497@purdue.edu>
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Off by one error in the code of NvmExpressMediaClear() causes the last
LBA to be missed when clearing the media.
This patch fixes the issue by adjusting the loop condition to ensure
that all LBAs are cleared properly.
Signed-off-by: Sean Brogan <sebrogan@microsoft.com>
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After allocating Private via AllocateZeroPool and successfully opening
both gEfiDevicePathProtocolGuid and gEfiPciIoProtocolGuid BY_DRIVER,
the function attempts PciIo->Attributes(EfiPciIoAttributeOperationGet)
If this call fails, the code executes return Status instead of goto Exit.
Trigger path:
NvmExpressDriverBindingStart is called.
OpenProtocol for DevicePath succeeds (opens BY_DRIVER).
OpenProtocol for PciIo succeeds (opens BY_DRIVER).
AllocateZeroPool for Private succeeds.
PciIo->Attributes(Get) returns an error.
return Status bypasses the Exit: label.
Consequence:
Memory leak of NVME_CONTROLLER_PRIVATE_DATA. Two protocols remain opened
BY_DRIVER on the controller handle, preventing other drivers from binding.
Signed-off-by: Sean Brogan <sebrogan@microsoft.com>
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NvmExpressMediaClear requires that the overwrite buffer be
the same size as the block size of the media but then
WriteBlocks expects BufferSize in bytes. NvmExpressMediaClear was
hardcoded to call using 1. This causes the WriteBlocks to fail.
Signed-off-by: Sean Brogan <sebrogan@microsoft.com>
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Fix spelling errors in definitions in Pci22.h.
Update consumers in MdeModulePkg, OvmfPkg, ShellPkg,
and SourceLevelDebugPkg.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
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Fix spelling errors in definitions in Atapi.h.
Update consumers in MdeModulePkg.
Continuous-integration-options: PatchCheck.ignore-multi-package
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
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Add CxlDxe driver that provides CxlIo protocol.
Co-authored-by: Abhishek Narvaria <abhi.n@samsung.com>
Co-authored-by: Alok Rathore <alok.rathore@samsung.com>
Co-authored-by: Nick Graves <nicholasgraves@google.com>
Co-authored-by: Ryan Heise <heiserya@google.com>
Co-authored-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
Co-authored-by: Sweta Kumari <s5.kumari@samsung.com>
Signed-off-by: Oleksandr Tymoshenko <ovt@google.com>
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In PciSioSerialDxe driver, gEfiDevicePathProtocolGuid appears twice in
[Procotols] section. In PiSmmCore driver, gEfiSmmSxDispatch2ProtocolGuid
appears twice in [Procotols] section. In PiSmmIpl driver,
gEfiEventReadyToBootGuid appears twice in [Procotols] section. In
DxeCapsuleLib driver, gEfiCapsuleVendorGuid appears twice in [Guids]
section. The duplicate ones should be removed.
Signed-off-by: Qihang Gao <gaoqihang@loongson.cn>
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NVMe Format and Sanitize admin commands correctly populate CDW10
(and CDW11 for Sanitize), but these codewords are not marked as valid
in the passthru command packet. As a result, the passthru layer does
not include the populated codewords in the command payload, causing
the commands to fail.
Set the appropriate CDW validity flags in the passthru command packet:
- Format NVM: CDW10_VALID
- Sanitize: CDW10_VALID | CDW11_VALID
This ensures the populated codewords are included in the passthru
command payload and the commands are issued correctly.
Signed-off-by: Shabab Alam <shabalam@qti.qualcomm.com>
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A purge erase operation on NVMe devices using the MediaSanitize
(MediaPurge) protocol fails with Status Code 02h (Invalid Field
in Command).
According to NVMe specification revision 1.4c, the Sanitize
command (OpCode 84h) does not use the NSID field (Section 5,
Figure 142). For commands that do not use NSID, the field must
be cleared to 0 as defined in Section 4.2, Figure 106.
Clear NSID to 0 before issuing the Sanitize command to ensure
spec compliance and prevent command failure.
Signed-off-by: Shabab Alam <shabalam@qti.qualcomm.com>
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This reverts commit f6489621b8ae1164c5e4930902988ba7c86847ba.
MdeModulePkg/PciBusDxe: Degrade MEM64 to PMEM64 when bridge lacks MEM64
A number of compatibility issues have been reported with this change
to the PciBusDxe behavior. Revert this change at this time to give
time for all the issues to be reviewed and options for supporting
this new behavior to be evaluated and fully validated.
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
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The current PciDevicePresent() implementation skips PCIe devices that
return Configuration Request Retry Status (CRS) during enumeration.
This causes devices that are slow to initialize (e.g., after power-on
or reset) to be missed entirely.
Per PCIe Base Specification Rev 3.1 Section 2.3.1, when CRS Software
Visibility is enabled and a device returns CRS, the Root Complex
reports Vendor ID as 0x0001. The specification recommends software
retry the configuration read until the device becomes ready.
This patch adds optional CRS retry support controlled by PCDs:
- PcdPciCrsRetryIntervalUs: Retry interval in microseconds (default 10000)
- PcdPciCrsTimeoutSeconds: Total timeout in seconds (default 0)
By default (PcdPciCrsTimeoutSeconds=0), CRS retry is disabled and
devices returning CRS are skipped during enumeration. Platforms
requiring CRS retry support should set PcdPciCrsTimeoutSeconds to
a non-zero value.
Additional improvements:
- Add PCI_VENDOR_ID_NONE and PCI_VENDOR_ID_CRS macros for readability
- Handle invalid PCD configurations (e.g., zero retry interval)
- Add DEBUG output for CRS detection, successful retry, and timeout
Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
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MR-IOV was actually not used in MdeModulePkg and it has been
deprecated in PCIe 6.0 specification. Remove code references,
but keep PcdMrIovSupport with just a comment that it is deprecated.
Signed-off-by: Jacek Kolakowski <Jacek.Kolakowski@intel.com>
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Resizable BAR driver selects max available BAR size to configure for use.
It may happen that some PCIe device declare support for size that exceeds
processor address width. Platform needs a way to define the max size it
can accept. This change introduce PCD called PcdPcieResizableBarMaxSize.
It is dynamic PCD where platform can provide its limit for BAR size.
Such PCD can be also controlled with a configuration knob.
Signed-off-by: Jacek Kolakowski <Jacek.Kolakowski@intel.com>
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Replace traditional `#ifndef`/`#define`/`#endif` include guards with
`#pragma` once.
`#pragma once` is a widely supported preprocessor directive that
prevents header files from being included multiple times. It is
supported by all toolchains used to build edk2: GCC, Clang/LLVM, and
MSVC.
Compared to macro-based include guards, `#pragma once`:
- Eliminates the risk of macro name collisions or copy/paste errors
where two headers inadvertently use the same guard macro.
- Eliminate inconsistency in the way include guard macros are named
(e.g., some files use `__FILE_H__`, others use `FILE_H_`, etc.).
- Reduces boilerplate (three lines replaced by one).
- Avoids polluting the macro namespace with guard symbols.
- Can improve build times as the preprocessor can skip re-opening the
file entirely, rather than re-reading it to find the matching
`#endif` ("multiple-include optimization").
- Note that some compilers may already optimize traditional include
guards, by recognzining the idiomatic pattern.
This change is made acknowledging that overall portability of the
code will technically be reduced, as `#pragma once` is not part of the
C/C++ standards.
However, this is considered acceptable given:
1. edk2 already defines a subset of supported compilers in
BaseTools/Conf/tools_def.template, all of which have supported
`#pragma once` for over two decades.
2. There have been concerns raised to the project about inconsistent
include guard naming and potential macro collisions.
Approximate compiler support dates:
- MSVC: Supported since Visual C++ 4.2 (1996)
- GCC: Supported since 3.4 (2004)
(http://gnu.ist.utl.pt/software/gcc/gcc-3.4/changes.html)
- Clang (LLVM based): Since initial release in 2007
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
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P2P bridge Memory Base/Limit registers (0x20-0x22) only support 32-bit
addresses. Previously, MEM64 resources behind such bridges were always
degraded to MEM32, forcing allocation below 4GB. This can lead to
resource constraints when using massive storage (such as MPF drives)
as MEM32 space is limited on most platforms.
Based on PCIe Base Specification 6.3+, assigning 64-bit resources
irrespective of the prefetchable/non-prefetchable BAR bit is allowed.
In DegradeResource(), if an upstream bridge supports PMEM64, MEM64
resources are now degraded to PMEM64 first. This enables 64-bit BAR
allocation for devices like NVMe controllers that declare non-
prefetchable 64-bit BARs.
We still fall back to MEM32 degradation if the bridge lacks PMEM64
support as well.
Ref: PCI-SIG ECN "Removing Prefetchable Terminology" (2024-04-05)
Ref: PCIe Base Specification 6.3+
Signed-off-by: Kun Qin <kuqin12@gmail.com>
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The comment for the Buffer parameter incorrectly said
"then no the size" instead of "then the size".
This patch fixes the typo only; no functional changes.
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
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When StartBusNumber is 0xFF NextNumber would overflow and wrap back to 0.
This will be bypass check NextNumber > MaxNumberInRange as a result
PCI enumeration will continue instead of breaking due to lack of resources.
Signed-off-by: Arkadiusz Filipowski <arkadiusz.filipowski@intel.com>
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The changes introduced by ff3c1ad which made two calls to
ProcessOpRomImage() resulted a platform where single OpRom present, the
same image to be loaded and started.
Prevent loading and starting same image twice.
Signed-off-by: Khalid Ali <khaliidcaliy@gmail.com>
Suggested-by: Ard Biesheuvel <ardb@kernel.org>
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Issue:https://github.com/tianocore/edk2/issues/11800
If there are multiple Option ROM images existed, current code will load
the first image that the emulator supports. Usually, x86 ROM image is
the first one and non-x86 ROM image is behind x86 ROM image. When the
emulator is introduced, x86 ROM image instead of native image is loaded
on non-x86 platforms.
This patch introduces a mechanism to prioritize the loading of native
images. Firstly, search the native image. If the native one is found,
just finish the process since the goal is reached. Otherwise, search
the foriegn images that the platform may support.
Signed-off-by: Qihang Gao <gaoqihang@loongson.cn>
Signed-off-by: Chao Li <lichao@loongson.cn>
Suggested-by: Ard Biesheuvel <ardb@kernel.org>
Tested-by: Chen Zhang <zhangchen@loongson.cn>
Cc: Dongyan Qian <qiandongyan@loongson.cn>
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Signed-off-by: Philipp Schuster <philipp.schuster@cyberus-technology.de>
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Bootup fails when an endpoint requests I/O space BARs and the
Root Bridge does not support I/O space causing a resource conflict
during bus enumeration. While I/O space is traditionally supported
in x86_64, platforms using an Arm architecture may or may not
support I/O space.
This change adds logic allowing the platform to detect I/O space
support for each Root Bridge and prevent submission of the required
I/O resources for allocation when unsupported. Endpoints will not
receive I/O resources, but they will continue to receive Memory
BAR resources.
Signed-off-by: Michael Escue <michael.escue@qti.qualcomm.com>
Reviewed-by: Joseph Oresko <joseph.oresko@qti.qualcomm.com>
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edk2 is dropping support for the ARM32 architecture. This
commit removes ARM32 support from MdeModulePkg. This also
drops irrelevant VALID_ARCHITECTURE comments from infs that
are not arch specific.
Signed-off-by: Oliver Smith-Denny <osde@microsoft.com>
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Clarify wording of the comment before the callback in XhcMonitorAsyncRequests.
Signed-off-by: Sherry Fan <sherryfan@microsoft.com>
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As noted in the comment above the callback invocation,
the URB's callback may free the URB, so any
operations, including updates, must occur before the callback.
Signed-off-by: Sherry Fan <sherryfan@microsoft.com>
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`XhcFreeUrb` attempts to unmap `Urb->DataMap` after
`FreePool(Urb->Data)` has already been called in some cases, causing a
use after free. Change the ordering so `Data` is freed after `Unmap`and
only freed when appropriate.
Signed-off-by: Sherry Fan <sherryfan@microsoft.com>
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Remove the UHCI PEI module, which is unused (in edk2-platforms) and
obsolete. It also implements an older version of the USB host controller
PPI, which can be dropped from EDK2 entirely once this driver is gone.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
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The Universal Graphics Adapter (UGA) is a graphic abstraction.
The UGA I/O and Draw protocols are deprecated since UEFI 2.0 was
introduced. Cf. the UEFI spec v2.9:
"Appendix L - EFI 1.10 Protocol Changes and Deprecation List"
section L.2 "Deprecated Protocols"
Remove the UGA support.
Signed-off-by: GuoMinJ <newexplorerj@gmail.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
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Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
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EFI_SUCESS -> EFI_SUCCESS
EFI_SUCESSS -> EFI_SUCCESS
Signed-off-by: Gao Qihang <gaoqihang@loongson.cn>
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`defintion`->`definition`
Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
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- Updated the PciGetBusRange function signature to use IN OUT for
the Descriptors parameter.
- Introduced a new DescriptorsBuffer variable in PciLib.c to
temporarily hold descriptor data.
- Clean up DescriptorsBuffer and set Descriptors to NULL after use.
Co-authored-by: Michael Kubacki <michael.kubacki@microsoft.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
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If there is a slow device on the PCI Bus, and the HostBridge is
programmed to allow CRS, the slow device may return 0x0001 to inform the
config space reader of the Vendor Id that pci device is not ready. The
current PciBus enumerator will treat 0001 as a valid Vendor Id, but it
is not. It indicates that all other config space is invalid. This code
changes that operation to skip slow devices.
PCI EXPRESS BASE SPECIFICATION, REV. 3.1 section
2.3.1 Request Handling Rules.
Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
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Add missing bit defines from 2.2.26 Capabilities Register (Cat.C Offset 040h)
Signed-off-by: Page Chen <paiching_chen@apple.com>
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When a USB device is enumerated it will report one or more endpoint
descriptors which contains a bInterval field which specifies the
interval a host should periodically poll for that particular endpoint
when scheduling transfers. But the units this value is expressed in
(in whole ms, a power of 2 x 1ms, or a power of 2 x 125us) may differ
depending on the speed of the device and whether the endpoint is
isochronous or interrupt.
Some high/super-speed devices, which are supposed to report isoc/int
bInterval as a power of 2 x 125us, incorrectly report full-speed
bInterval values (that is, in whole units of ms) in their interrupt
endpoint descriptors which results in an assertion error due to being
out of range of the spec-expected values. Rather than asserting, try
to adjust those assuming they were expressed in units of ms with an
upper limit of 128ms.
Signed-off-by: Jack Pham <jackp@qti.qualcomm.com>
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Currently the bInterval value must be calculated differently
based on whether the endpoint type is isochronous or interrupt,
and whether the device is low, full, high or super speed. Plus,
this is duplicated for both XhcInitializeEndpointContext() and
XhcInitializeEndpointContext64().
To reduce code complexity and duplication, and for future ease of
maintenance, factor this logic out to a separate CalculateInterval()
helper function.
Signed-off-by: Jack Pham <jackp@qti.qualcomm.com>
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Protocol/UsbHostController.h described an ancient protocol never part of
a public specification ... and was in fact not needed. So drop the
reference.
Also drop some text from a function documentation header incorrectly
implying use of the UsbHcProtocol.
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
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