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authorDongyan Qian <qiandongyan@loongson.cn>2026-10-20 13:39:34 +0300
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2026-10-24 20:15:38 +0300
commit0a503bc2f5bd37c7a5d39d0ba31008f446f0298d (patch)
tree22067de8bdc99bbe4704c2fe9431b7a7325f1d78 /MdePkg/Library/BasePostCodeLibPort80
parent02c1141a0e5b5c958630e81ac6ebb4b03c1e836f (diff)
downloadedk2-master.tar.xz
MdePkg/BaseLib: Support IMPCTL1, IMPCTL2 and TLBRPRMD on LoongArchHEADmaster
Add CsrRead(), CsrWrite() and CsrXChg() support for IMPCTL1 (0x80), IMPCTL2 (0x81) and TLBRPRMD (0x8F). These selectors currently reach the unsupported-selector trap instead of a CSR instruction. Define the register numbers, add the IMPCTL1/2 dispatch range and extend the existing TLB refill range and instruction tables through TLBRPRMD. Preserve the existing handling of all other selectors. The register definitions follow LoongArch Reference Manual Volume 1, version 1.10, sections 7.4.18, 7.4.19 and 7.5.17. IMPCTL field semantics remain implementation-specific; this change only enables CSR access. Link: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html Signed-off-by: Dongyan Qian <qiandongyan@loongson.cn>
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