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authorRARelph <44270374+RARelph@users.noreply.github.com>2025-10-31 01:02:27 +0300
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2025-11-04 09:51:50 +0300
commitb98ccecdecec0bb768e6e5bd4df1694de87ad42f (patch)
treebf65937fbfd27d509fca19af61996efdf20169f1 /MdePkg/Library/BaseLib/BaseLib.inf
parent8058a94f60a129476a7955ee839cec96467b9bef (diff)
downloadedk2-b98ccecdecec0bb768e6e5bd4df1694de87ad42f.tar.xz
MdePkg: Add code to detect running as an SEV guest
Similar to Intel's Tdx, we need a mechanism to detect running as an AMD SEV guest that will work in all phases everywhere. This will be immediately used to prevent usage of MTRRs with SEV guests. Signed-off-by: Richard Relph <richard.relph@amd.com>
Diffstat (limited to 'MdePkg/Library/BaseLib/BaseLib.inf')
-rw-r--r--MdePkg/Library/BaseLib/BaseLib.inf6
1 files changed, 6 insertions, 0 deletions
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 7925d8cef6..aa067a77a5 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -213,6 +213,7 @@
X86PatchInstruction.c
X86SpeculationBarrier.c
IntelTdxNull.c
+ X64/SevProbe.c
[Sources.X64]
X64/Thunk16.nasm
@@ -299,6 +300,7 @@
X64/TdCall.nasm
X64/TdVmcall.nasm
X64/TdProbe.c
+ X64/SevProbe.c
X64/Non-existing.c
Math64.c
@@ -340,6 +342,7 @@
Unaligned.c
Math64.c
IntelTdxNull.c
+ AmdSevNull.c
[Sources.AARCH64]
AArch64/InternalSwitchStack.c
@@ -368,6 +371,7 @@
AArch64/ArmReadCntPctReg.asm | MSFT
AArch64/ArmReadIdAA64Isar0Reg.asm | MSFT
IntelTdxNull.c
+ AmdSevNull.c
[Sources.RISCV64]
Math64.c
@@ -390,6 +394,7 @@
RiscV64/RiscVMmu.S | GCC
RiscV64/SpeculationBarrier.S | GCC
IntelTdxNull.c
+ AmdSevNull.c
[Sources.LOONGARCH64]
Math64.c
@@ -411,6 +416,7 @@
LoongArch64/Cpucfg.S | GCC
LoongArch64/ReadStableCounter.S | GCC
IntelTdxNull.c
+ AmdSevNull.c
[Packages]
MdePkg/MdePkg.dec