MdePkg: Add PCI/PCIe register offset macros and bitfield definitions

Add register offset macros and bitfield definitions for PCI/PCIe
capability registers to replace hardcoded values and provide type-safe
field access.

1. MdePkg\Include\IndustryStandard\Pci22.h
   (PCI Local Bus Specification / PCI-to-PCI Bridge Architecture)
   - Added Base Address Register (BAR) offset macros for the Type 0
     configuration header:
     * PCI_BASE_ADDRESSREG1_OFFSET (0x14)
     * PCI_BASE_ADDRESSREG2_OFFSET (0x18)
     * PCI_BASE_ADDRESSREG3_OFFSET (0x1C)
     * PCI_BASE_ADDRESSREG4_OFFSET (0x20)
     * PCI_BASE_ADDRESSREG5_OFFSET (0x24)
   - Added bridge register offset macros:
     * PCI_BRIDGE_IO_BASE_REGISTER_OFFSET (0x1C)
     * PCI_BRIDGE_IO_LIMIT_REGISTER_OFFSET (0x1D)
     * PCI_BRIDGE_MEMORY_BASE_REGISTER_OFFSET (0x20)
     * PCI_BRIDGE_MEMORY_LIMIT_REGISTER_OFFSET (0x22)
     * PCI_BRIDGE_64BIT_MEMORY_BASE_REGISTER_OFFSET (0x24)
     * PCI_BRIDGE_64BIT_MEMORY_LIMIT_REGISTER_OFFSET (0x26)
     * PCI_BRIDGE_64BIT_MEMORY_BASE_UPPER_REGISTER_OFFSET (0x28)
     * PCI_BRIDGE_64BIT_MEMORY_LIMIT_UPPER_REGISTER_OFFSET (0x2C)
     * PCI_BRIDGE_IO_BASE_UPPER_REGISTER_OFFSET (0x30)
     * PCI_BRIDGE_IO_LIMIT_UPPER_REGISTER_OFFSET (0x32)
     * PCI_BRIDGE_INTERRUPT_LINE_REGISTER_OFFSET (0x3C)
     * PCI_BRIDGE_CONTROL_REGISTER_OFFSET (0x3E)

     - PCIe spec revision 7.0, Section 7.5.1.3.9/.10 (Figure 7-14),
     which renamed the Type 1 header's "Prefetchable Memory
     Base/Limit" and "Prefetchable Base/Limit Upper 32 Bits" fields
     to "64-bit Memory Base/Limit" and "64-bit Base/Limit Upper 32
     Bits". Offsets and behavior are unchanged, only the naming.

2. MdePkg\Include\IndustryStandard\PciExpress21.h
   (PCIe Extended Capabilities)
   - Added SR-IOV control/status register bitfield unions
   - Added Virtual Channel capability/control register bitfield
     unions and offset macros
   - Added Access Control Services (ACS) capability/control bitfield
     unions
   - Added RCRB capability/control register bitfield unions and offset
     macros
   - Added Alternative Routing-ID Interpretation (ARI) bitfield
     unions

REFERENCES:
- PCI Local Bus Specification, Revision 2.2
- PCI-to-PCI Bridge Architecture Specification, Revision 1.2
- PCI Express Base Specification, Revision 7.0

Cc: Sachin Ganesh <sachinganesh@ami.com>
Cc: Dhanaraj V <vdhanaraj@ami.com>
Cc: Sergiy Yakovlev <sergiyy@ami.com>
Cc: Dhiinesh M <dhiineshm@ami.com>
Signed-off-by: Varun G <varung@ami.com>

0 files changed, 0 insertions, 0 deletions