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| author | Lean Sheng Tan <sheng.tan@9elements.com> | 2022-03-30 21:29:02 +0300 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-04-10 20:46:10 +0300 |
| commit | bfefdc2c49ca9487b7aa0df196b2aca6c0c170a2 (patch) | |
| tree | 0823d2c227d1b042cb8c4637d923ebb8711d3c49 /BaseTools/Source/Python/Workspace | |
| parent | 4f4afcd28802ff8a3e78ad72e47b6acb6e24819c (diff) | |
| download | edk2-bfefdc2c49ca9487b7aa0df196b2aca6c0c170a2.tar.xz | |
UefiPayloadPkg: Fix PciHostBridgeLib
Don't assume a 64bit register always holds an address greater than 4GB.
Check the value in the register and decide which Aperature it should be
assigned to.
Fixes assertion
"ASSERT [PciHostBridgeDxe] Bridge->MemAbove4G.Base >= 0x0000000100000000ULL".
Tested with coreboot as bootloader on platforms that have PCI resource
above 4GiB and on platforms that don't have resource above 4GiB.
Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Cc: Sean Rhodes <sean@starlabs.systems>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Guo Dong <guo.dong@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Workspace')
0 files changed, 0 insertions, 0 deletions