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| author | Alok Kulkarni <akulkarni@microsoft.com> | 2026-01-16 01:37:14 +0300 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2026-01-30 07:53:05 +0300 |
| commit | f6489621b8ae1164c5e4930902988ba7c86847ba (patch) | |
| tree | 43c4b878442477f57d962780136d414f945d7fbe /BaseTools/Source/Python/Workspace/MetaFileParser.py | |
| parent | 300dada916aa9492d5fe52693e9d6fd84adccdf3 (diff) | |
| download | edk2-f6489621b8ae1164c5e4930902988ba7c86847ba.tar.xz | |
MdeModulePkg: PciBusDxe: Degrade MEM64 to PMEM64 when bridge lacks MEM64
P2P bridge Memory Base/Limit registers (0x20-0x22) only support 32-bit
addresses. Previously, MEM64 resources behind such bridges were always
degraded to MEM32, forcing allocation below 4GB. This can lead to
resource constraints when using massive storage (such as MPF drives)
as MEM32 space is limited on most platforms.
Based on PCIe Base Specification 6.3+, assigning 64-bit resources
irrespective of the prefetchable/non-prefetchable BAR bit is allowed.
In DegradeResource(), if an upstream bridge supports PMEM64, MEM64
resources are now degraded to PMEM64 first. This enables 64-bit BAR
allocation for devices like NVMe controllers that declare non-
prefetchable 64-bit BARs.
We still fall back to MEM32 degradation if the bridge lacks PMEM64
support as well.
Ref: PCI-SIG ECN "Removing Prefetchable Terminology" (2024-04-05)
Ref: PCIe Base Specification 6.3+
Signed-off-by: Kun Qin <kuqin12@gmail.com>
Diffstat (limited to 'BaseTools/Source/Python/Workspace/MetaFileParser.py')
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