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| author | Sheng Wei <w.sheng@intel.com> | 2023-11-09 12:14:39 +0300 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2023-12-07 12:43:43 +0300 |
| commit | 553dfb0f57ae8a666938873cf836a33549568c87 (patch) | |
| tree | df38e7205912795b895e2e462bfdd4e2afc22b95 /BaseTools/Source/Python/Workspace/DecBuildData.py | |
| parent | fd1dd8568c78c594540990eaa4fbe37fdd3b1839 (diff) | |
| download | edk2-553dfb0f57ae8a666938873cf836a33549568c87.tar.xz | |
UefiCpuPkg: Backup and Restore MSR IA32_U_CET in SMI handler.
OS may enable CET-IBT feature by set MSR IA32_U_CET.bit2.
If IA32_U_CET.bit2 is set, CPU is in WAIT_FOR_ENDBRANCH state and
the next assemble code is not ENDBR, it will trigger #CP exception
when set CR4.CET bit.
SMI handler needs to backup MSR IA32_U_CET and clear MSR IA32_U_CET
before set CR4.CET bit,
And SMI handler needs to restore MSR IA32_U_CET when exit SMI handler.
Signed-off-by: Sheng Wei <w.sheng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Wu Jiaxin <jiaxin.wu@intel.com>
Cc: Tan Dun <dun.tan@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Workspace/DecBuildData.py')
0 files changed, 0 insertions, 0 deletions