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authorStar Zeng <star.zeng@intel.com>2017-08-24 12:42:49 +0300
committerStar Zeng <star.zeng@intel.com>2017-08-25 12:09:23 +0300
commit0b9c0c65400262ee41eb8f4f4d9079fab4777437 (patch)
treee8dbad561b0652ead2b1ccf3986616341d89e81f /BaseTools/Source/Python/UPT/UnitTest/CommentParsingUnitTest.py
parent9d5dfe9d74fba521011236fb4b0c8c8547e03dda (diff)
downloadedk2-0b9c0c65400262ee41eb8f4f4d9079fab4777437.tar.xz
MdeModulePkg XhciDxe: Fix Map and Unmap inconsistency
We found there are loops of *2* Maps and only *1* Unmap and the DMA buffer address is decreasing. It is caused by the below code flow. XhcAsyncInterruptTransfer -> XhcCreateUrb -> XhcCreateTransferTrb -> Map Urb->DataMap (1) Timer: loops of *2* Maps and only *1* Unmap XhcMonitorAsyncRequests -> XhcFlushAsyncIntMap -> Unmap and Map Urb->DataMap (2) XhcUpdateAsyncRequest -> XhcCreateTransferTrb -> Map Urb->DataMap (3) This patch is to eliminate (3). Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
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