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| author | Star Zeng <star.zeng@intel.com> | 2018-01-16 11:41:42 +0300 |
|---|---|---|
| committer | Star Zeng <star.zeng@intel.com> | 2018-01-17 05:34:22 +0300 |
| commit | e8097a74b763bfc439c273ddfef8e1d542d83ea7 (patch) | |
| tree | 009df592a7f138080dc2bd77885d9736c5b79ccd /BaseTools/Source/Python/Table/TableQuery.py | |
| parent | 6478baf891524348451d75a37f4e4692b835a45b (diff) | |
| download | edk2-e8097a74b763bfc439c273ddfef8e1d542d83ea7.tar.xz | |
IntelSiliconPkg IntelVTdPmrPei: Refine comments about PHMR/PLMR.Limit
According to VTd spec, the real hardware decoded limit should be
PHMR/PLMR.Limit value + alignment value.
"Bits N:0 of the limit register are
decoded by hardware as all 1s."
Cc: Jiewen Yao <jiewen.yao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Table/TableQuery.py')
0 files changed, 0 insertions, 0 deletions