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authorDaniel Schaefer <daniel.schaefer@hpe.com>2020-03-03 20:31:30 +0300
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2020-04-03 20:09:12 +0300
commit9b2b0942f1988e07744fbd6f1a11b57720f7b6ae (patch)
tree3fdb2301aa6328f980fe62610287b5076b235228 /BaseTools/Source/Python/CommonDataClass/DataClass.py
parent0467236267645d4cace02155b25d69f4f395e65a (diff)
downloadedk2-9b2b0942f1988e07744fbd6f1a11b57720f7b6ae.tar.xz
MdePkg/DxeServicesLib: Add RISC-V architecture
BZ:2562: https://bugzilla.tianocore.org/show_bug.cgi?id=2562 Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com> Reviewed-by: Liming Gao <liming.gao@intel.com> Cc: Abner Chang <abner.chang@hpe.com> Cc: Gilbert Chen <gilbert.chen@hpe.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com>
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