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| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2015-11-18 18:59:04 +0300 |
|---|---|---|
| committer | abiesheuvel <abiesheuvel@Edk2> | 2015-11-18 18:59:04 +0300 |
| commit | 07070ecc76cff00175715f9a9534bc9216599a11 (patch) | |
| tree | 2bb576b33b75c70f5db5a7110cff964c3315c7ce /BaseTools/Source/Python/Common/TargetTxtClassObject.py | |
| parent | 2ea66ed9f9ea18cbe2681baaad29ce47ea9918a1 (diff) | |
| download | edk2-07070ecc76cff00175715f9a9534bc9216599a11.tar.xz | |
ArmPkg/ArmV7Mmu: make cached translation table accesses shareable
To align with the way normal cacheable memory is mapped, set the
shareable bit for cached accesses performed by the page table walker.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18896 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'BaseTools/Source/Python/Common/TargetTxtClassObject.py')
0 files changed, 0 insertions, 0 deletions