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| author | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-05-25 12:57:37 +0300 |
|---|---|---|
| committer | Ruiyu Ni <ruiyu.ni@intel.com> | 2018-05-28 11:33:55 +0300 |
| commit | d92336541782f9d51b6a6fb743e14d5ef754deeb (patch) | |
| tree | 87de67320c5c8befb0d5ead182426bfda3cd537c /BaseTools/Source/Python/Common/Database.py | |
| parent | 2b5f0daa6c5f1d205b82c52c9ce55307a1787a3e (diff) | |
| download | edk2-d92336541782f9d51b6a6fb743e14d5ef754deeb.tar.xz | |
MdeModulePkg/PciBus: Do not enable MemWriteAndInvalidate bit for PCIE
Per PCIE spec, Memory Write and Invalidate is hardwired to 0b so
PciBus driver shouldn't write 1b to it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Common/Database.py')
0 files changed, 0 insertions, 0 deletions