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| author | Jiewen Yao <jiewen.yao@intel.com> | 2017-09-15 07:29:10 +0300 |
|---|---|---|
| committer | Jiewen Yao <jiewen.yao@intel.com> | 2017-09-20 09:45:43 +0300 |
| commit | 8e9da4ba3c4a4eeded7651f629330df3a9e5a780 (patch) | |
| tree | 03237bafb8059be7c6cfc613ba9e256290ac2171 /BaseTools/Source/Python/Common/Database.py | |
| parent | f02c531967785780ad14fbc8475d8322dfd0909b (diff) | |
| download | edk2-8e9da4ba3c4a4eeded7651f629330df3a9e5a780.tar.xz | |
IntelSiliconPkg/IntelVTdPmrPei: Parse RMRR table.
In order to support PEI graphic, we let VTdPmrPei driver
parse DMAR table RMRR entry and allow the UMA access.
If a system has no PEI IGD, no RMRR is needed. The behavior
is unchanged.
If a system has PEI IGD, it must report RMRR in PEI phase.
The PeiVTdPrm will program the IGD VTd engine to skip the
RMRR region, and program the rest PCI VTd engine to skip
the another DMA buffer allocated in PEI phase for other
device driver.
Cc: Star Zeng <star.zeng@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Diffstat (limited to 'BaseTools/Source/Python/Common/Database.py')
0 files changed, 0 insertions, 0 deletions