blob: b6408ecc2b584e70d708203aea39c6a25b94af6d (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
|
#;*****************************************************************************
#;
#; Copyright (C) 2021-2025 Advanced Micro Devices, Inc. All rights reserved.
#; SPDX-License-Identifier: BSD-2-Clause-Patent
#;
#;*****************************************************************************
##############################################################################
#
# Genoa reference board - 2 SPI FLash devices accessible by x86 (selected by DIP-switch):
# 1) 32MB Flash with 10-pin header next to the VGA connector.
# 2) 64MB Flash with 10-pin header at 90-degrees from VGA connector, and also accessible by the BMC.
#
################################################################################
################################################################################
#
# BIOS image layout
#
################################################################################
### Flash layout, 16MB and 32MB iamge size with ROM3_FLASH_ENABLE = FALSE
################################################################################
# Start End Size FV Name
################################################################################
# 0x00000000 0x0001ffff 0x00020000 None Unused
# 0x00020000 0x00020fff 0x00001000 DATA EFS
# 0x00021000 0x0005efff 0x0003e000 DATA NVRAM
# 0x0005f000 0x0005ffff 0x00001000 DATA NVRAM FTW
# 0x00060000 0x000a0fff 0x00041000 None NVRAM Reserved
# 0x000a1000 0x002e2fff 0x00242000 None PSPDirectory
# 0x002e3000 0x0033efff 0x0005c000 None BIOSDirectory
# 0x0033f000 0x005adfff 0x0026f000 None PSPDirectory
# 0x005ae000 0x006fffff 0x00152000 None BIOSDirectory
# 0x00700000 0x007cffff 0x000d0000 FV FVADVANCED
# 0x007d0000 0x0084ffff 0x00080000 FV FVADVANCEDSECURITY
# 0x00850000 0x008effff 0x000a0000 FV FVOSBOOT
# 0x008f0000 0x00bc7fff 0x002d8000 FV FVUEFIBOOT
# 0x00bc8000 0x00beffff 0x00028000 FV FVSECURITY
# 0x00bf0000 0x00bf7fff 0x00008000 FV FVPOSTMEMORY
# 0x00bf8000 0x00bfffff 0x00008000 FV FVADVANCEDPREMEMORY
# 0x00c00000 0x00ffffff 0x00400000 FV FVPREMEMORY
################################################################################
# Extra padding for 32MB image size
# 0x01000000 0x01ffffff 0x01000000 None unused
################################################################################
### Flash layout, 32MB with ROM3_FLASH_ENABLE = TRUE
################################################################################
# Start End Size FV Name
################################################################################
# 0x00000000 0x0001ffff 0x00020000 None Unused
# 0x00020000 0x00020fff 0x00001000 DATA EFS
# 0x00021000 0x0005efff 0x0003e000 DATA NVRAM
# 0x0005f000 0x0005ffff 0x00001000 DATA NVRAM FTW
# 0x00060000 0x000a0fff 0x00041000 None NVRAM Reserved
# 0x000a1000 0x002e2fff 0x00242000 None PSPDirectory
# 0x002e3000 0x0033efff 0x0005c000 None BIOSDirectory
# 0x0033f000 0x005adfff 0x0026f000 None PSPDirectory
# 0x005ae000 0x006fffff 0x00152000 None BIOSDirectory
# 0x00bb0000 0x00bd7fff 0x00028000 FV FVSECURITY
# 0x00bd8000 0x00bf7fff 0x00020000 FV FVPOSTMEMORY
# 0x00bf8000 0x00bfffff 0x00008000 FV FVADVANCEDPREMEMORY
# 0x00c00000 0x00ffffff 0x00400000 FV FVPREMEMORY
# 0x01000000 0x010cffff 0x000d0000 FV FVADVANCED
# 0x010d0000 0x0114ffff 0x00080000 FV FVADVANCEDSECURITY
# 0x01150000 0x011effff 0x000a0000 FV FVOSBOOT
# 0x011f0000 0x014c7fff 0x002d8000 FV FVUEFIBOOT
# 0x014bc000 0x01ffefff 0x00b43000 None Unused
# 0x01fff000 0x01ffffff 0x00001000 None Unused
################################################################################
DEFINE ROM2_FLASH_BASE = 0xFF000000
DEFINE ROM2_FLASH_SIZE = 0x01000000
DEFINE ROM3_FLASH_SIZE = 0x02000000
DEFINE SPI_BLOCK_SIZE = 0x1000
!ifndef BUILD_16MB_IMAGE
DEFINE BUILD_16MB_IMAGE = FALSE
!endif
!ifndef ROM3_FLASH_ENABLE
DEFINE ROM3_FLASH_ENABLE = FALSE
!endif
!ifndef ROM3_FLASH_BASE
DEFINE ROM3_FLASH_BASE = 0xFD02000000
!endif
!if $(BUILD_16MB_IMAGE) == TRUE
DEFINE SPI_NUM_BLOCKS = 0x1000
!else
DEFINE SPI_NUM_BLOCKS = 0x2000
!endif
!if ($(ROM3_FLASH_ENABLE) == TRUE) && ($(BUILD_16MB_IMAGE) == TRUE)
!error "ROM3 cannot be enabled on 16MB image"
!endif
!ifndef FV_PRE_MEMORY_SIZE
# Do not reduce the FvPreMemorySize
DEFINE FV_PRE_MEMORY_SIZE = 0x00400000
!endif
!ifndef FV_ADVANCED_PRE_MEMORY_SIZE
DEFINE FV_ADVANCED_PRE_MEMORY_SIZE = 0x00008000
!endif
!ifndef FV_POST_MEMORY_SIZE
!if ($(ROM3_FLASH_ENABLE) == TRUE)
# Need extra space for DxeMain
DEFINE FV_POST_MEMORY_SIZE = 0x00020000
!else
DEFINE FV_POST_MEMORY_SIZE = 0x00008000
!endif
!endif
!ifndef FV_SECURITY_SIZE
DEFINE FV_SECURITY_SIZE = 0x00028000
!endif
!ifndef FV_UEFI_BOOT_SIZE
DEFINE FV_UEFI_BOOT_SIZE = 0x002D8000
!endif
!ifndef FV_OS_BOOT_SIZE
DEFINE FV_OS_BOOT_SIZE = 0x000A0000
!endif
!ifndef FV_ADVANCED_SECURITY_SIZE
DEFINE FV_ADVANCED_SECURITY_SIZE = 0x00080000
!endif
!ifndef FV_ADVANCED_SIZE
DEFINE FV_ADVANCED_SIZE = 0x000D0000
!endif
DEFINE FV_FW_SIG_OFFSET = 0x00020000
DEFINE FV_FW_SIG_SIZE = 0x00001000
DEFINE NVRAM_AREA_VAR_OFFSET = 0x00021000
DEFINE NVRAM_AREA_VAR_SIZE = 0x0003E000
DEFINE NVRAM_AREA_SIZE = 0x00080000
DEFINE FTW_WORKING_OFFSET = $(NVRAM_AREA_VAR_OFFSET) + $(NVRAM_AREA_VAR_SIZE)
DEFINE FTW_WORKING_SIZE = $(SPI_BLOCK_SIZE)
DEFINE FTW_SPARE_OFFSET = $(FTW_WORKING_OFFSET) + $(FTW_WORKING_SIZE)
DEFINE FTW_SPARE_SIZE = $(NVRAM_AREA_SIZE) - $(NVRAM_AREA_VAR_SIZE) - $(FTW_WORKING_SIZE)
# NOTE:
#
# BOOT_FV_BASE value should match with the PspData<SoC>.xml ResetImage address
# e.g.
# <POINT_ENTRY Type="0x62" Address="0xC00000" Destination="0x76C00000" Size="0x400000">
# <TypeAttrib Compressed="0x0" Copy="0x1" ReadOnly="0x0" RegionType="0x0" ResetImage="0x1" />
# </POINT_ENTRY>
#
# Also note that C00000 from 0x76C000000 came from PcdFlashFvPreMemoryOffset
# if PcdFlashFvPreMemoryOffset gets changed then the below value should also
# need to be change.
#
!ifndef BOOT_FV_BASE
DEFINE BOOT_FV_BASE = 0x76C00000
!endif
SET gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashNvStorageBlockSize = $(SPI_BLOCK_SIZE)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF000000
SET gEfiAmdAgesaPkgTokenSpaceGuid.PcdAgesaFlashAreaBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
# SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000
# SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = $(NVRAM_AREA_VAR_OFFSET)
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = $(NVRAM_AREA_VAR_SIZE)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = $(FTW_WORKING_OFFSET)
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = $(FTW_WORKING_SIZE)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = $(FTW_SPARE_OFFSET)
SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = $(FTW_SPARE_SIZE)
#
# FV offset and size assignment
#
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = $(FV_PRE_MEMORY_SIZE)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = ($(ROM2_FLASH_SIZE) - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize = $(FV_ADVANCED_PRE_MEMORY_SIZE)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = $(FV_POST_MEMORY_SIZE)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = $(FV_SECURITY_SIZE)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
!if $(ROM3_FLASH_ENABLE) == FALSE
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = $(FV_UEFI_BOOT_SIZE)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = $(FV_OS_BOOT_SIZE)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize)
SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize = $(FV_ADVANCED_SECURITY_SIZE)
SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset - gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = $(FV_ADVANCED_SIZE)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize)
# NOTE:
# for ROM3_FLASH_ENABLE disabled BIOS image max address (PcdFlashFvAdvancedSize + PcdFlashFvAdvancedOffset)
# should not overlap with BIOS DIR2 offset + size in PspData<SoC>.xml
# e.g
# <BIOS_DIR Level="2" Base="0x5CB000" Size="0x120000" SpiBlockSize=" 0x1000">
#
!endif
!if $(ROM3_FLASH_ENABLE) == TRUE
# if ROM3 is enabled then continue the offset update
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = $(ROM2_FLASH_SIZE)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = $(FV_ADVANCED_SIZE)
SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize)
SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize = $(FV_ADVANCED_SECURITY_SIZE)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityOffset + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = $(FV_OS_BOOT_SIZE)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = (gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize)
SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = $(FV_UEFI_BOOT_SIZE)
# NOTE:
# for ROM3_FLASH_ENABLE enabled BIOS image max address (PcdFlashFvSecuritySize + PcdFlashFvSecurityOffset)
# should not overlap with BIOS DIR2 offset + size in PspData<SoC>.xml
# e.g
# <BIOS_DIR Level="2" Base="0x5CB000" Size="0x120000" SpiBlockSize=" 0x1000">
!endif
SET gAmdMinBoardPkgTokenSpaceGuid.PcdBootFvBase = $(BOOT_FV_BASE)
!if $(ROM3_FLASH_ENABLE) == TRUE
SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase = $(ROM3_FLASH_BASE)
SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize)
SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecurityBase + gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvAdvancedSecuritySize)
SET gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvUefiBootBase = (gAmdMinBoardPkgTokenSpaceGuid.PcdAmdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize)
!endif
|
