diff options
37 files changed, 5131 insertions, 1202 deletions
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec index 6cecd7c289..c422f9fff0 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec @@ -168,6 +168,7 @@ gEfiPlatformTypeWilsonCitySMTProtocolGuid = { 0xEE55562D, 0x4001, 0xFC27, { 0xDF, 0x16, 0x7B, 0x90, 0xEB, 0xE1, 0xAB, 0x04 } } gEfiPlatformTypeCooperCityRPProtocolGuid = { 0x45c302e1, 0x4b86, 0x89be, { 0xab, 0x0f, 0x5e, 0xb5, 0x57, 0xdf, 0xe8, 0xd8 } } gEfiPlatformTypeJunctionCityProtocolGuid = { 0xB1C2B1C9, 0xB606, 0x4B62, { 0x9D, 0x78, 0xCB, 0xD6, 0x0F, 0xF9, 0x0D, 0x0C } } + gEfiPlatformTypeTucanaProtocolGuid = { 0x04a127ed, 0x6862, 0x4d23, { 0x90, 0xab, 0x3a, 0x4c, 0xb1, 0xc8, 0x20, 0xe2 } } gEfiPlatformTypeAowandaProtocolGuid = { 0x65231A3C, 0xC343, 0x4C7E, { 0xA4, 0x5E, 0x0F, 0x99, 0x74, 0xA6, 0x90, 0x83 } } gEfiPlatformTypeBoardPortTemplateProtocolGuid = { 0xecaa1083, 0x9d72, 0x44d1, { 0xb1, 0x42, 0x0e, 0xd8, 0x0a, 0xd1, 0x37, 0xd2 } } # diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Readme.md b/Platform/Intel/WhitleyOpenBoardPkg/Readme.md index 777f434a01..52216f7beb 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Readme.md +++ b/Platform/Intel/WhitleyOpenBoardPkg/Readme.md @@ -63,6 +63,7 @@ gEfiPlatformTypeMyBoardProtocolGuid = { 0xa68228c5, 0xc00f, 0x4d9a, { 0x8d break; ``` 9. Add the gEfiPlatformTypeMyBoardProtocolGuid to the WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf + and WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf 10. Add a build option to edk2-platforms/Platform/Intel/build.cfg. e.g. ``` MyBoard = WhitleyOpenBoardPkg/MyBoard/build_config.cfg diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c new file mode 100644 index 0000000000..2f37289b85 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c @@ -0,0 +1,47 @@ +/** @file + This file implements the IPMI Platform hook functions + + Copyright (c) 2021, American Megatrends International LLC. <BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include <Uefi.h> +#include <Ppi/DynamicSiLibraryPpi.h> +#include <Library/PeiServicesLib.h> +#include <Library/DebugLib.h> +#define KCS_BASE_ADDRESS_MASK 0xFFF0 +#define NUMBER_OF_BYTES_TO_DECODE 0x10 + +/** + This function sets IO Decode Range in LPC registers + + @param[in] IpmiIoBase - IPMI Base IO address + + @retval EFI_SUCCESS - Operation success. + +**/ +EFI_STATUS +EFIAPI +PlatformIpmiIoRangeSet ( + UINT16 IpmiIoBase +) +{ + + EFI_STATUS Status; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi; + + DynamicSiLibraryPpi = NULL; + + DEBUG ((DEBUG_INFO, "PlatformIpmiIoRangeSet IpmiIoBase %x\n", IpmiIoBase)); + + Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, (VOID **) &DynamicSiLibraryPpi); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi for gDynamicSiLibraryPpiGuid failed. Status %r\n", Status)); + ASSERT_EFI_ERROR (Status); + return Status; + } + + DynamicSiLibraryPpi->PchLpcGenIoRangeSet ((IpmiIoBase & KCS_BASE_ADDRESS_MASK), NUMBER_OF_BYTES_TO_DECODE); + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf new file mode 100644 index 0000000000..699d89b24a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf @@ -0,0 +1,32 @@ +## @file +# Component description file for IPMI platform hook Library. +# +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2021, American Megatrends International LLC.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = IpmiPlatformHookLib + FILE_GUID = A770BDB8-331A-4110-8B60-81FC17480B36 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = IpmiPlatformHookLib + +[sources] + IpmiPlatformHookLib.c + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + +[LibraryClasses] + DebugLib + +[Ppis] + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Library/PeiPlatformHookLib/PeiPlatformHooklib.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Library/PeiPlatformHookLib/PeiPlatformHooklib.c new file mode 100644 index 0000000000..5eed3ad207 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Library/PeiPlatformHookLib/PeiPlatformHooklib.c @@ -0,0 +1,95 @@ +/** @file + PEI Library Functions. Initialize GPIOs + + Copyright 1999 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include <Uefi.h> +#include <Guid/PlatformInfo.h> +#include <Library/DebugLib.h> +#include <Library/UbaGpioInitLib.h> +#include <Library/PeiPlatformHooklib.h> +#include <Library/PeiServicesLib.h> +#include <Ppi/DynamicSiLibraryPpi.h> + +/** + Configure GPIO + + @param[in] None + + @retval None +**/ +VOID +GpioInit ( + VOID +) +{ + PlatformInitGpios (); +} + +/** + Disables ME PCI devices like IDE-R , KT + + @param[in] None + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +DisableMEDevices ( + VOID +) +{ + EFI_STATUS Status = EFI_SUCCESS; + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi; + + DynamicSiLibraryPpi = NULL; + + DEBUG ((DEBUG_INFO, "DisableMEDevices\n")); + + Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, (VOID **) &DynamicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + //Disable IDE-R + // + DynamicSiLibraryPpi->PchPcrAndThenOr32 ( + PID_PSF1, + (R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE + R_PCH_PSFX_PCR_T0_SHDW_PCIEN), + (UINT32)~0, + B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS + ); + + // + //Disable KT + // + DynamicSiLibraryPpi->PchPcrAndThenOr32 ( + PID_PSF1, + (R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE + R_PCH_PSFX_PCR_T0_SHDW_PCIEN), + (UINT32)~0, + B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS + ); + return EFI_SUCCESS; + +} + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInit ( + ) +{ + + GpioInit(); + DisableMEDevices (); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf new file mode 100644 index 0000000000..fb3985c4e0 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf @@ -0,0 +1,35 @@ +## @file +# +# @copyright +# Copyright 1999 - 2021 Intel Corporation. <BR> +# Copyright (c) 2021, American Megatrends International LLC. <BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PeiPlatformHookLib + FILE_GUID = 6E9351C3-A17A-4ADF-8602-55B07962718F + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = PeiPlatformHookLib|PEIM PEI_CORE SEC + +[Sources] + PeiPlatformHooklib.c + +[Packages] + MdePkg/MdePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[LibraryClasses] + DebugLib + UbaGpioInitLib + +[Pcd] + +[Ppis] + +[Guids] diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/PlatformPkg.dsc new file mode 100644 index 0000000000..d418cac182 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/PlatformPkg.dsc @@ -0,0 +1,79 @@ +## @file +# X64 Platform with 64-bit DXE. +# +# @copyright +# Copyright 2008 - 2021 Intel Corporation. <BR> +# Copyright (c) 2021 - 2022, American Megatrends International LLC. <BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + PEI_ARCH = IA32 + DXE_ARCH = X64 + + !include WhitleyOpenBoardPkg/PlatformPkg.dsc + +[PcdsFixedAtBuild] + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6 + +[PcdsFeatureFlag] +!if $(gMinPlatformPkgTokenSpaceGuid.PcdBootStage) >= 5 + gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |TRUE + gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable |TRUE +!endif + + !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc + +[Defines] + BOARD_NAME = Tucana + PLATFORM_NAME = $(BOARD_NAME) + PLATFORM_GUID = 4a938dd1-acce-47bc-8614-18fbc8c3dd70 + FLASH_DEFINITION = $(RP_PKG)/$(BOARD_NAME)/PlatformPkg.fdf + +[PcdsFixedAtBuild] + +!if $(TARGET) == "RELEASE" + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03 + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F # Enable asserts, prints, code, clear memory, and deadloops on asserts. + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x80200047 # Built in messages: Error, MTRR, info, load, warn, init + gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 # This is set to INT3 (0x2) for Simics source level debugging +!endif + gPlatformTokenSpaceGuid.PcdBoardId|0x82 + +[PcdsFixedAtBuild.X64] + gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2015 + gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099 + +[PcdsDynamicExHii] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout" + +[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM] + PeiPlatformHookLib|$(RP_PKG)/$(BOARD_NAME)/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf + +!if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable == TRUE + IpmiPlatformHookLib| $(RP_PKG)/$(BOARD_NAME)/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf +!endif + +[Components.IA32] + $(RP_PKG)/Uba/BoardInit/Pei/BoardInitPei.inf { + <LibraryClasses> + NULL|$(RP_PKG)/$(BOARD_NAME)/Uba/TypeTucana/Pei/PeiBoardInitLib.inf + NULL|$(RP_PKG)/Uba/UbaMain/Common/Pei/PeiCommonBoardInitLib.inf + } + +[Components.X64] + $(RP_PKG)/$(BOARD_NAME)/Uba/TypeTucana/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf + $(RP_PKG)/$(BOARD_NAME)/Uba/TypeTucana/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf + $(RP_PKG)/$(BOARD_NAME)/Uba/TypeTucana/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/PlatformPkg.fdf b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/PlatformPkg.fdf new file mode 100644 index 0000000000..9da85524a1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/PlatformPkg.fdf @@ -0,0 +1,827 @@ +## @file +# FDF file of platform with 64-bit DXE +# This package provides platform specific modules and flash layout information. +# +# @copyright +# Copyright 2006 - 2025 Intel Corporation. <BR> +# Copyright (c) 2021, American Megatrends International LLC. <BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] +DEFINE PLATFORM_PKG = MinPlatformPkg + +# 0x00000060 = (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER)) +DEFINE FDF_FIRMWARE_HEADER_SIZE = 0x00000060 + +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x90 # FV Header plus FFS header + +DEFINE VPD_HEADER_SIZE = 0x00000090 + +!if $(FSP_MODE) == 0 + DEFINE FSP_BIN_DIR = Api +!else + DEFINE FSP_BIN_DIR = Dispatch +!endif + +# +# Note: FlashNv PCD naming conventions are as follows: +# Note: This should be 100% true of all PCD's in the gCpPlatFlashTokenSpaceGuid space, and for +# Others should be examined with an effort to work toward this guideline. +# PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec +# PcdFlash*Size is a hex count of the length of the FD or FV +# All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd' +# +# Also all values will have a PCD assigned so that they can be used in the system, and +# the FlashMap edit tool can be used to change the values here, without effecting the code. +# This requires all code to only use the PCD tokens to recover the values. + + +# +# 16MiB Total FLASH Image (visible in memory mapped IO) +# +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF000000 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000 + +################################################################################ +# +# FD SECPEI +# +# Contains all the SEC and PEI modules +# +# Layout: (Low address to high address) +# +# FvBsp for board specific components +# FvPostMemory for compressed post memory MinPlatform spec required components +# FvFspS for compressed post memory silicon initialization components +# FvPostMemorySilicon for silicon components +# FvFspM for pre memory silicon initialization components +# FvPreMemorySilicon for silicon components +# FvFspT for temp RAM silicon initilization components +# FvBspPreMemory for board specific components required to intialize memory +# FvAdvancedPreMemory FV for advanced features components +# FvPreMemory for components required by MinPlatform spec and to initialize memory +# FvPreMemorySecurity FV for stage 6 required components +# Contains reset vector +# +################################################################################ + +[FD.SecPei] + BaseAddress = 0xFFCA0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase #The base address of the FLASH Device + Size = 0x00360000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize #The size in bytes of the FLASH Device + ErasePolarity = 1 + BlockSize = 0x1000 + NumBlocks = 0x360 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manually calculate the offsets. + # At this time, the FSP FV must be aligned at the same address they were built to, 0xFFD00000 + # This will be corrected in the future. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00040000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x00221000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00006000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize = 0x00010000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize + + # + # Calculate Offsets Once (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture specification. + # Each offset is the prior region's offset plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset = 0x00000000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize + + # + # FV Layout (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture specification. + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize + FV = FvBsp + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize + FV = FvPostMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize + FILE = $(FSP_BIN_PKG)/Fsp_Rebased_S.fd + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize + FILE = $(FSP_BIN_PKG)/Fsp_Rebased_M.fd + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize + FILE = $(FSP_BIN_PKG)/Fsp_Rebased_T.fd + + # + # Shared FV layout + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize + FV = FvBspPreMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize + FV = FvPreMemory + + # + # Calculate base addresses (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture specification. + # Each base is the prior region's base plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize + + # + # Set duplicate PCD + # These should not need to be changed + # + + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize + + # + # For API mode, wrappers have some duplicate PCD as well + # + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + +################################################################################ +# +# FD Main +# +# All DXE modules and other regions +# +# Layout: (Low address to high address) +# +# FvAdvanced for advanced feature components +# Assorted advanced feature FV +# FvSecurity for MinPlatform spec required components needed to boot securely +# FvOsBoot for MinPlatform spec required components needed to boot OS +# FvLateSilicon for silicon specific components +# FvUefiBoot for MinPlatform spec required components needed to boot to UEFI shell +# +################################################################################ +[FD.Main] + BaseAddress = 0xFF2E0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase # The base address of the FLASH Device + Size = 0x009C0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize # The size in bytes of the FLASH Device + ErasePolarity = 1 + BlockSize = 0x1000 + NumBlocks = 0x9C0 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manually calculate the offsets. + # These are out of flash layout order because FvAdvanced gets any remaining space + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00070000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00230000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x0004C000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + + # + # Calculate Offsets Once (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture specification. + # Each offset is the prior region's offset plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00000000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize + + # + # FV Layout (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture specification. + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize + FV = FvAdvanced + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + FV = FvSecurity + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize + FV = FvOsBoot + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize + FV = FvUefiBoot + + # + # Calculate base addresses (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture specification. + # Each base is the prior region's base plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize + +################################################################################ +# +# FD BINARY +# +# Contains the OPROM and other binary modules +# +# Layout: (Low address to high address) +# +# FvOpRom containing pre-built components +# FvAcmRegion containing ACM related content +# FV Header + Blank Space (1K) +# Policy block (3K) +# Blank space to align ACM on 64K boundary (60K) +# ACM binary +# FvMicrocode containing microcode update patches +# Unformatted region for PCI Gen 3 Data +# FvVpd containing PCD VPD data +# FvWhea for WHEA data recording +# FvNvStorageVariable for UEFI Variable storage +# FvNvStorageEventLog for NV Store management +# FvNvStorageFtwWorking for Fault Tolerant Write solution +# FvNvStorageFtwSpare for Fault Tolerant Write solution +# +################################################################################ +[FD.Binary] + BaseAddress = 0xFF000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + Size = 0x002E0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize + ErasePolarity = 1 + BlockSize = 0x1000 + NumBlocks = 0x2E0 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manually calculate the offsets. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize = 0x00100000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize = 0x00050000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = 0x000D0000 + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize = 0x00010000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize = 0x00030000 + # + # These four items are tightly coupled. + # The spare area size must be >= the first three areas. + # + # There isn't really a benefit to a larger spare area unless the FLASH device + # block size is larger than the size specified. + # + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0003C000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize = 0x00002000 + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000 + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + + # + # Calculate Offsets Once (You should not need to modify this section) + # Each offset is the prior region's offset plus the prior region's size. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset = 0x00000000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + + # + # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically + # + SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv + SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize - gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv + + # + # FV Layout (You should not need to modify this section) + # + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize + FV = FvOprom + + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + FV = FvAcm + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + FV = FvMicrocode + + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize + FV = FvVPD + + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize + FV = FvWhea + + # + # Do not modify. + # See comments in size discussion above. These four areas are tightly coupled and should be modified with utmost care. + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf + gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written + + # + # Calculate base addresses (You should not need to modify this section) + # Each base is the prior region's base plus the prior region's size. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + $(VPD_HEADER_SIZE) + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase = gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize - $(VPD_HEADER_SIZE) + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + + # + # ACM details + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x1000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize = 0x3000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x10000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize = 0x00040000 + + # + # Other duplicate PCD + # + SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize + SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize +################################################################################ +# +# FD FPGA +# +# Contains the FPGA modules +# +################################################################################ + +[FD.Fpga] + BaseAddress = 0xFD000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase #The base address of the FPGA Device ( 4G - 48M ) + Size = 0x02000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize #The size in bytes of the FPGA Device ( 32M ) + ErasePolarity = 1 + BlockSize = 0x1000 + NumBlocks = 0x2000 + + 0x00000000|0x02000000 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase | gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize + FV = FvFpga + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvSecurityPreMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = 40ab290f-8494-41cf-b302-31b178b4ce0b + + !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf + +[FV.FvPreMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864 + + INF UefiCpuPkg/SecCore/SecCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf + INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf + + INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf + + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf + + INF WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf + + INF WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf + + FILE PEIM = ac4b7f1b-e057-47d3-b2b5-1137493c0f38 { + SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.depex + SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.efi + SECTION UI = "DynamicSiLibraryPei" + } + + INF WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf + + INF WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf + + INF WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf + + # + # UBA common and board specific components + # + !include WhitleyOpenBoardPkg/Uba/UbaPei.fdf + + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf + + INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf + + FILE PEIM = ca8efb69-d7dc-4e94-aad6-9fb373649161 { + SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.depex + SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.efi + SECTION UI = "SiliconPolicyInitPreAndPostMem" + } + + INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf + + !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePreMemory.fdf + + INF WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf + + INF RuleOverride = LzmaCompress UefiCpuPkg/CpuMpPei/CpuMpPei.inf + + !if $(FSP_MODE) == 0 + FILE PEIM = 8F7F3D20-9823-42DD-9FF7-53DAC93EF407 { + SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.depex + SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.efi + SECTION UI = "CsrPseudoOffsetInitPeim" + } + FILE PEIM = 2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352 { + SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.depex + SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.efi + SECTION UI = "RegAccessPeim" + } + FILE PEIM = C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67F { + SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.depex + SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.efi + SECTION UI = "SiliconDataInitPeim" + } + INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf + INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + INF WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchSpi.inf + !endif + + FILE FV_IMAGE = 40ab290f-8494-41cf-b302-31b178b4ce0b { + SECTION FV_IMAGE = FvSecurityPreMemory + } + +[FV.FvAdvancedPreMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = 09f25d44-b2ef-4225-8b2e-e0e094b51775 + + !include AdvancedFeaturePkg/Include/PreMemory.fdf + +[FV.FvBspPreMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = e6c65995-8c2d-4119-a52d-7dbf1acb45a1 + + FILE FV_IMAGE = 09f25d44-b2ef-4225-8b2e-e0e094b51775 { + SECTION FV_IMAGE = FvAdvancedPreMemory + } + +# +# FvPostMemory includes common hardware, common core variable services, load and invoke DXE etc +# +[FV.FvPostMemoryUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA + +[FV.FvPostMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = 3298afc4-c484-47f1-a65a-5917a54b5e8c + + FILE FV_IMAGE = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvPostMemoryUncompressed + } + } + +# +# FvBsp includes board specific components +# +[FV.FvBspUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = e4c65347-fd90-4143-8a41-113e1015fe07 + +[FV.FvBsp] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = 9e151cf3-ca90-444f-b33b-a9941cbc772f + + FILE FV_IMAGE = e4c65347-fd90-4143-8a41-113e1015fe07 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvBspUncompressed + } + } + +[FV.FvUefiBootUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = C4D3B0E2-FB26-44f8-A05B-E95895FCB960 + + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + INF MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf + + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf + #ATA for IDE/AHCI/RAID support + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf + INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + + FILE DRIVER = 85299F8F-F2B9-4487-AF60-231434A5EFF6 { + SECTION PE32 = edk2-non-osi/Drivers/ASpeed/ASpeedGopBinPkg/X64/ASpeedAst2500Gop.efi + } + + +[FV.FvUefiBoot] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = ab9fe87b-1e37-440c-91cc-9aea03ce7bec + + FILE FV_IMAGE = C4D3B0E2-FB26-44f8-A05B-E95895FCB960 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvUefiBootUncompressed + } + } + +[FV.FvOsBootUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 + + # + # DXE Phase modules + # + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + + FILE FV_IMAGE = B7C9F0CB-15D8-26FC-CA3F-C63947B12831 { + SECTION UI = "FvLateSilicon" + SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateSilicon.fv + } + + INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + + !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePostMemory.fdf + + # + # UBA DXE common and board specific components + # + !include WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf + INF $(RP_PKG)/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf + INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeTucana/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf + INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeTucana/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf + INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeTucana/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf + INF WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/PlatformType.inf + INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + + !if ($(FSP_MODE) == 1) + INF WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf + !else + INF MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + !endif + + INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf + INF UefiCpuPkg/CpuDxe/CpuDxe.inf + INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + + FILE FV_IMAGE = a0277d07-a725-4823-90f9-6cba00782111 { + SECTION UI = "FvLateOpenBoard" + SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateOpenBoard.fv + } + + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf + + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf + INF RuleOverride = UI MdeModulePkg/Application/UiApp/UiApp.inf + INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + #TPM when TPM enable, SecurityStubDxe needs to be removed from this FV. + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + + INF FatPkg/EnhancedFatDxe/Fat.inf + + INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf + + INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + INF ShellPkg/Application/Shell/Shell.inf + + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + + INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf + INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf + + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf + + INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf + + INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + + INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf + + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf + + INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf + + INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + + INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf + + # UEFI USB stack + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + + INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf + INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + + INF RuleOverride = ACPITABLE WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/AcpiTables10nm.inf + INF WhitleyOpenBoardPkg/Features/Acpi/AcpiPlatform/AcpiPlatform.inf + INF WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf + INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf + +[FV.FvOsBoot] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = c7488640-5f51-4969-b63b-89fc369e1725 + + FILE FV_IMAGE = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvOsBootUncompressed + } + } + +[FV.FvSecuritySilicon] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = AD262F8D-BDED-4668-A8D4-8BC73516652F + + !include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf + +[FV.FvSecurityUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = 03E25550-89A5-4ee6-AF60-DB0553D91FD2 + + FILE FV_IMAGE = 81F80AEA-91EB-4AD9-A563-7CEBAA167B25 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvSecuritySilicon + } + } + +[FV.FvSecurity] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = 68134833-2ff6-4d22-973b-575d0eae8ffd + + FILE FV_IMAGE = 03E25550-89A5-4ee6-AF60-DB0553D91FD2 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvSecurityUncompressed + } + } + +[FV.FvAdvancedUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = 70aeaf57-4997-49ce-a4f7-122980745670 + + !include AdvancedFeaturePkg/Include/PostMemory.fdf + +[FV.FvAdvanced] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = f21ee7a1-53a9-453d-aee3-b6a5c25bada5 + + FILE FV_IMAGE = 70aeaf57-4997-49ce-a4f7-122980745670 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvAdvancedUncompressed + } + } + +# +# FV for all Microcode Updates. +# +[FV.FvMicrocode] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + LOCK_STATUS = FALSE + FvNameGuid = D2C29BA7-3809-480F-9C3D-DE389C61425A + +!if $(CPUTARGET) == "CPX" + INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf +!else + INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf +!endif + + +[FV.FvVPD] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + LOCK_STATUS = FALSE + FvNameGuid = FFC29BA7-3809-480F-9C3D-DE389C61425A + FILE RAW = FF7DB236-F856-4924-90F8-CDF12FB875F3 { + $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin + } + +# +# Various Vendor UEFI Drivers (OROMs). +# +[FV.FvOpromUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = B6EDE22C-DE30-45fa-BB09-CA202C1654B7 + +[FV.FvOprom] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = 983BCAB5-BF10-42ce-B85D-CB805DCB1EFD + + FILE FV_IMAGE = B6EDE22C-DE30-45fa-BB09-CA202C1654B7 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FvOpromUncompressed + } + } + +[FV.FvWhea] + BlockSize = 0x1000 + NumBlocks = 0x30 + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = d6a1cd70-4b33-4994-a6ea-375f2ccc5437 + +# +# FV For ACM Binary. +# +[FV.FvAcm] + BlockSize = 0x1000 + NumBlocks = 0x50 + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = 11668261-8A8D-47ca-9893-052D24435E59 + +[FV.FvFpga] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid = 974650E7-6DFE-4998-A124-CEDEC5C9B47D + +################################################################################ +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are the default +# rules for the different module type. User can add the customized rules to define the +# content of the FFS file. +# +################################################################################ + +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM = $(NAMED_GUID) { + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.DXE_RUNTIME_DRIVER.DRIVER_ACPITABLE] + FILE DRIVER = $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + UI STRING="$(MODULE_NAME)" Optional + VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER) + } diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c new file mode 100644 index 0000000000..51e2f7b2ef --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c @@ -0,0 +1,100 @@ +/** @file + IIO Config Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "IioCfgUpdateDxe.h" + +EFI_STATUS +UpdateTucanaIioConfig ( + IN IIO_GLOBALS *IioGlobalData + ) +{ + return EFI_SUCCESS; +} + +PLATFORM_IIO_CONFIG_UPDATE_TABLE TypeTucanaIioConfigTable = +{ + PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE, + PLATFORM_IIO_CONFIG_UPDATE_VERSION, + + IioBifurcationTable, + sizeof(IioBifurcationTable), + UpdateTucanaIioConfig, + IioSlotTable, + sizeof(IioSlotTable) + +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this driver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +IioCfgUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL; + + DEBUG((DEBUG_INFO, "UBA:IioCfgUpdate-TypeTucana\n")); + Status = gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + (VOID **) &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid, + &TypeTucanaIioConfigTable, + sizeof(TypeTucanaIioConfigTable) + ); + + Status = UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_1, + &TypeTucanaIioConfigTable, + sizeof(TypeTucanaIioConfigTable) + ); + + Status = UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_2, + &TypeTucanaIioConfigTable, + sizeof(TypeTucanaIioConfigTable) + ); + + Status = UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_3, + &TypeTucanaIioConfigTable, + sizeof(TypeTucanaIioConfigTable) + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h new file mode 100644 index 0000000000..53d3a49f9a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h @@ -0,0 +1,119 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IIOCFG_UPDATE_DXE_H_ +#define _IIOCFG_UPDATE_DXE_H_ + +#include <Base.h> +#include <Uefi.h> +#include <Protocol/UbaCfgDb.h> +#include <Library/UefiDriverEntryPoint.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PciLib.h> +#include <Library/UbaIioConfigLib.h> +#include <IioPlatformData.h> + +typedef enum { + Iio_Socket0 = 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + VPP_PORT_0 = 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORT; + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_0 0 +#define VPP_PORT_1 1 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF + +static IIO_BIFURCATION_DATA_ENTRY IioBifurcationTable[] = +{ + // Neon City IIO bifurcation table (Based on Neon City Block Diagram rev 0.6) + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxx8x4x4 }, + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, + { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, +}; + +static IIO_SLOT_CONFIG_DATA_ENTRY IioSlotTable[] = { + // Port | Slot | Inter | Power Limit | Power Limit | Hot | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD | Hidden + // Index | | lock | Scale | Value | Plug | Port | Addr | Cap | VppPort | VppAddr | + { PORT_1A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x4C , HIDE },//Oculink + { PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x4C , HIDE },//Oculink + { PORT_1C_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE }, + { PORT_2A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE }, + // Slot 2 supports HP: PCA9555 (CPU0) Addres 0x40, SCH (Rev 0.604) P 118 (MRL in J65) + { PORT_3A_INDEX, 2 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 , NOT_HIDE }, + { PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 , HIDE }, + { PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 , HIDE }, + { PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 , HIDE }, + { SOCKET_1_INDEX + + PORT_0_INDEX , 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE }, + // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 121 (MRL in J287) + { SOCKET_1_INDEX + + PORT_1A_INDEX, 4 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 , NOT_HIDE }, + { SOCKET_1_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 , HIDE }, + { SOCKET_1_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 , HIDE }, + { SOCKET_1_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 , HIDE }, + { SOCKET_1_INDEX + + PORT_2A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_1 , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x44 , NOT_HIDE }, + { SOCKET_1_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x44 , HIDE }, + { SOCKET_1_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x46 , HIDE }, + { SOCKET_1_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x46 , HIDE }, + { SOCKET_1_INDEX + + PORT_3A_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE }, + { SOCKET_1_INDEX + + PORT_3C_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE }, + // Note: On Neon City, Slot 3 is assigned to PCH's PCIE port +}; + +#endif //_IIOCFG_UPDATE_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf new file mode 100644 index 0000000000..f6e7563804 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf @@ -0,0 +1,52 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation. <BR> +# Copyright (c) 2021, American Megatrends International LLC. <BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION = 0x00010005 + BASE_NAME = IioCfgUpdateDxeTucana + FILE_GUID = 9ecb1682-8b3a-475e-92df-cc63d25d93fa + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = IioCfgUpdateEntry + +[sources] + IioCfgUpdateDxe.c + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + gPlatformIioConfigDataDxeGuid + gPlatformIioConfigDataDxeGuid_1 + gPlatformIioConfigDataDxeGuid_2 + gPlatformIioConfigDataDxeGuid_3 + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeTucanaProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c new file mode 100644 index 0000000000..e4df349043 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c @@ -0,0 +1,116 @@ +/** @file + Slot Data Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SlotDataUpdateDxe.h" + +UINT8 +GetTypeTucanaIOU0Setting ( + UINT8 IOU0Data +) +{ + // + // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled. + // + IOU0Data = IIO_BIFURCATE_xxx8xxx8; + return IOU0Data; +} + +UINT8 +GetTypeTucanaIOU2Setting ( + UINT8 SkuPersonalityType, + UINT8 IOU2Data +) +{ + return IOU2Data; +} + +static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeTucanaBroadwayTable[] = { + {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 }, + {Iio_Socket1, Iio_Iou1, Bw5_Addr_2}, + {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 }, +}; + + +PLATFORM_SLOT_UPDATE_TABLE TypeTucanaSlotTable = +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeTucanaBroadwayTable, + GetTypeTucanaIOU0Setting, + 0 +}; + +PLATFORM_SLOT_UPDATE_TABLE2 TypeTucanaSlotTable2 = +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeTucanaBroadwayTable, + GetTypeTucanaIOU0Setting, + 0, + GetTypeTucanaIOU2Setting +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this driver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +SlotDataUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL; + + DEBUG((DEBUG_INFO, "UBA:SlotDataUpdate-TypeTucana\n")); + Status = gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + (VOID **) &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformSlotDataDxeGuid, + &TypeTucanaSlotTable, + sizeof(TypeTucanaSlotTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformSlotDataDxeGuid, + &TypeTucanaSlotTable2, + sizeof(TypeTucanaSlotTable2) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h new file mode 100644 index 0000000000..e59e70c9ee --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h @@ -0,0 +1,58 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SLOT_DATA_UPDATE_DXE_H_ +#define _SLOT_DATA_UPDATE_DXE_H_ + + +#include <Base.h> +#include <Uefi.h> + +#include <Protocol/UbaCfgDb.h> + +#include <Library/UefiDriverEntryPoint.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PciLib.h> + +#include <Library/UbaSlotUpdateLib.h> +#include <IioPlatformData.h> + +typedef enum { + Iio_Socket0 = 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Bw5_Addr_0 = 0, + Bw5_Addr_1, + Bw5_Addr_2, + Bw5_Addr_3, + Bw5_Addr_Max +} BW5_ADDRESS; + +#endif //_SLOT_DATA_UPDATE_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf new file mode 100644 index 0000000000..aa2741a26d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf @@ -0,0 +1,49 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation. <BR> +# Copyright (c) 2021, American Megatrends International LLC. <BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION = 0x00010005 + BASE_NAME = SlotDataUpdateDxeTucana + FILE_GUID = 3b3de60f-211c-44b6-bea5-c40f39d2a51e + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = SlotDataUpdateEntry + +[sources] + SlotDataUpdateDxe.c + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + gPlatformSlotDataDxeGuid + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeTucanaProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c new file mode 100644 index 0000000000..f6196332d9 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c @@ -0,0 +1,128 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "UsbOcUpdateDxe.h" + +#include <Library/UbaUsbOcUpdateLib.h> +#include <PchLimits.h> +#include <ConfigBlock/UsbConfig.h> +#include <ConfigBlock/Usb2PhyConfig.h> + +USB_OVERCURRENT_PIN TypeTucanaUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = { + UsbOverCurrentPinSkip, //Port00: BMC + UsbOverCurrentPinSkip, //Port01: BMC + UsbOverCurrentPin0, //Port02: Rear Panel + UsbOverCurrentPin1, //Port03: Rear Panel + UsbOverCurrentPin1, //Port04: Rear Panel + UsbOverCurrentPinSkip, //Port05: NC + UsbOverCurrentPinSkip, //Port06: NC + UsbOverCurrentPin4, //Port07: Type A internal + UsbOverCurrentPinSkip, //Port08: NC + UsbOverCurrentPinSkip, //Port09: NC + UsbOverCurrentPin6, //Port10: Front Panel + UsbOverCurrentPinSkip, //Port11: NC + UsbOverCurrentPin6, //Port12: Front Panel + UsbOverCurrentPinSkip, //Port13: NC + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB_OVERCURRENT_PIN TypeTucanaUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = { + UsbOverCurrentPin6, //Port01: Front Panel + UsbOverCurrentPin6, //Port02: Front Panel + UsbOverCurrentPin0, //Port03: Rear Panel + UsbOverCurrentPin1, //Port04: Rear Panel + UsbOverCurrentPin1, //Port05: Rear Panel + UsbOverCurrentPinSkip, //Port06: NC + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB2_PHY_PARAMETERS TypeTucanaUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS] = { + {3, 0, 3, 1}, // PP0 + {5, 0, 3, 1}, // PP1 + {3, 0, 3, 1}, // PP2 + {0, 5, 1, 1}, // PP3 + {3, 0, 3, 1}, // PP4 + {3, 0, 3, 1}, // PP5 + {3, 0, 3, 1}, // PP6 + {3, 0, 3, 1}, // PP7 + {2, 2, 1, 0}, // PP8 + {6, 0, 2, 1}, // PP9 + {2, 2, 1, 0}, // PP10 + {6, 0, 2, 1}, // PP11 + {0, 5, 1, 1}, // PP12 + {7, 0, 2, 1}, // PP13 + }; + +EFI_STATUS +TypeTucanaPlatformUsbOcUpdateCallback ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +) +{ + *Usb20OverCurrentMappings = &TypeTucanaUsb20OverCurrentMappings[0]; + *Usb30OverCurrentMappings = &TypeTucanaUsb30OverCurrentMappings[0]; + + *Usb20AfeParams = TypeTucanaUsb20AfeParams; + return EFI_SUCCESS; +} + +PLATFORM_USBOC_UPDATE_TABLE TypeTucanaUsbOcUpdate = +{ + PLATFORM_USBOC_UPDATE_SIGNATURE, + PLATFORM_USBOC_UPDATE_VERSION, + TypeTucanaPlatformUsbOcUpdateCallback +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this driver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +UsbOcUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL; + + DEBUG((DEBUG_INFO, "UBA:UsbOcUpdate-TypeTucana\n")); + Status = gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + (VOID **) &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gDxePlatformUbaOcConfigDataGuid, + &TypeTucanaUsbOcUpdate, + sizeof(TypeTucanaUsbOcUpdate) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h new file mode 100644 index 0000000000..2ba90c7598 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h @@ -0,0 +1,27 @@ +/** @file + + @copyright + Copyright 2015 - 2021 Intel Corporation. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _USBOC_UPDATE_DXE_H_ +#define _USBOC_UPDATE_DXE_H_ + +#include <Base.h> +#include <Uefi.h> + +#include <Protocol/UbaCfgDb.h> + +#include <Library/UefiDriverEntryPoint.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> + + + +#endif //_USBOC_UPDATE_DXE_H_ + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf new file mode 100644 index 0000000000..0bc24342a5 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf @@ -0,0 +1,46 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation. <BR> +# Copyright (c) 2021, American Megatrends International LLC. <BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION = 0x00010005 + BASE_NAME = UsbOcUpdateDxeTucana + FILE_GUID = 6ab0f797-626a-4093-a60e-4a04b03cd893 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = UsbOcUpdateEntry + +[sources] + UsbOcUpdateDxe.c + UsbOcUpdateDxe.h + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + gDxePlatformUbaOcConfigDataGuid + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeTucanaProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/AcpiTablePcds.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/AcpiTablePcds.c new file mode 100644 index 0000000000..d42f647f5b --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/AcpiTablePcds.c @@ -0,0 +1,52 @@ +/** @file + ACPI table pcds update. + + @copyright + Copyright 2015 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include <Library/PcdLib.h> +#include <Library/HobLib.h> +#include <Guid/PlatformInfo.h> +#include <UncoreCommonIncludes.h> +#include <Cpu/CpuIds.h> + +EFI_STATUS +TypeTucanaPlatformUpdateAcpiTablePcds ( + VOID + ) +{ + CHAR8 AcpiName10nm[] = "EPRP10NM"; // USED for identify ACPI table for 10nm in systmeboard dxe driver + CHAR8 OemTableIdXhci[] = "xh_nccrb"; + + UINTN Size; + EFI_STATUS Status; + + EFI_HOB_GUID_TYPE *GuidHob; + + DEBUG ((DEBUG_INFO, "Uba Callback: PlatformUpdateAcpiTablePcds entered\n")); + + GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob != NULL); + if (GuidHob == NULL) { + return EFI_NOT_FOUND; + } + + //# + //#ACPI items + //# + Size = AsciiStrSize (AcpiName10nm); + Status = PcdSetPtrS (PcdOemSkuAcpiName , &Size, AcpiName10nm); + DEBUG ((DEBUG_INFO, "%a TypeTucana ICX\n", __func__)); + ASSERT_EFI_ERROR (Status); + + Size = AsciiStrSize (OemTableIdXhci); + Status = PcdSetPtrS (PcdOemTableIdXhci , &Size, OemTableIdXhci); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/GpioTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/GpioTable.c new file mode 100644 index 0000000000..49abaec2d2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/GpioTable.c @@ -0,0 +1,296 @@ +/** @file + + @copyright + Copyright 2020 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include <Library/UbaGpioUpdateLib.h> + +#include <Library/GpioLib.h> +#include <Library/UbaGpioInitLib.h> +#include <GpioPinsSklH.h> +#include <Library/PcdLib.h> + +// +// Board : Wilson City RP +// +static GPIO_INIT_CONFIG mGpioTableTucana [] = + { + {GPIO_SKL_H_GPP_A0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N //IRQ_ESPI_FPGA_PCH_ALERT1_N PU not used + {GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_1_LPC_LAD0_ESPI_IO0 + {GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_2_LPC_LAD1_ESPI_IO1 + {GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_3_LPC_LAD2_ESPI_IO2 + {GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_4_LPC_LAD3_ESPI_IO3 + {GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N + {GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N + {GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N + {GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_8_FM_LPC_CLKRUN_N //PU_LPC_CLKRUN_N PU not used + {GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_9_CLK_24M_66M_LPC0_ESPI + {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_10_TP_PCH_GPP_A_10 + {GPIO_SKL_H_GPP_A11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_11_FM_LPC_PME_N //PU_LPC_PME_N PU not used + {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_12_IRQ_PCH_SCI_WHEA_N //PU_IRQ_PCH_SCI_WHEA_N PU not used + {GPIO_SKL_H_GPP_A13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_13_FM_EUP_LOT6_N //TP_PCH_GPP_A_13 + {GPIO_SKL_H_GPP_A14, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_14_RST_ESPI_RESET_N + {GPIO_SKL_H_GPP_A15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_15_FM_SUSACK_N //TP_PCH_GPP_A_15 + {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_16_TP_PCH_GPP_A_16 //FM_PCHIE_BMC_N + {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_17_TP_PCH_GPP_A_16 //FM_BMC_PCHIE_N + {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_18_FM_BIOS_ADV_FUNCTIONS //IRQ_BMC_PCH_SMI_LPC_N +// GPIO_SKL_H_GPP_A19 - Not Owned by BIOS //ME Recovery Jumper FM_ME_RCVR_N + {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_20_TP_PCH_GPP_A_20 //FM_BMC_READY_N + {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_21_TP_PCH_GPP_A_21 + {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_22_TP_PCH_GPP_A_22 + {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_23_TP_PCH_GPP_A_23 + {GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_0_FM_PCH_CORE_VID_0 + {GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_1_FM_PCH_CORE_VID_1 + {GPIO_SKL_H_GPP_B2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_2_PU_PCH_VRALERT_N + {GPIO_SKL_H_GPP_B3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}}, //PU_SATA_EN +// GPIO_SKL_H_GPP_B4 - Not Owned by BIOS //ME SMB Alert MGPIO IRQ_SML1_PMBUS_ALERT + {GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_5_FM_PCH_INTERPOSER_SEL1 //TP_PCH_GPP_B_5 + {GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_6_FM_PCH_INTERPOSER_SEL2 //TP_PCH_GPP_B_6 + {GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_7_TP_PCH_GPP_B_7 + {GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_8_TP_PCH_GPP_B_8 + {GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_9_FM_BOARD_REV_ID2 //TP_PCH_GPP_B_9 + {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_10_FM_TPM_MOD_PRES_N +// GPIO_SKL_H_GPP_B11 - Not Owned by BIOS //ME SMB Alert_EN MGPIO FM_PMBUS_ALERT_BUF_EN_N + {GPIO_SKL_H_GPP_B12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_12_TP_SLP_S0_N //FM_GLOBAL_RST_WARN_N + {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_13_RST_PLTRST_N + {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_14_FM_PCH_BIOS_RCVR_SPKR + {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_15_FM_CPU_ERR0_PCH_N + {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_16_FM_CPU_ERR1_PCH_N + {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_17_FM_CPU_ERR2_PCH_N + {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_18_FM_NO_REBOOT //PU_NO_REBOOT Spare + {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_19_FM_BOARD_SKU_ID5 //TP_PCH_GPP_B19 + {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigLock}},//GPP_B_20_FM_BIOS_POST_CMPLT_N + {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_21_TP_PCH_GPP_B_21 + {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_22_FM_PCH_BOOT_BIOS_DEVICE //FM_USB_PWR_EN + {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_23_FM_PCH_BMC_THERMTRIP_EXI_STRAP_N +// GPIO_SKL_H_GPP_C0 - Not Owned by BIOS //ME SMBCLK +// GPIO_SKL_H_GPP_C1 - Not Owned by BIOS //ME SMBDATA + {GPIO_SKL_H_GPP_C2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_2_PU_PCH_TLS_ENABLE_STRAP //IRQ_SMB_ALERT_N_TLS_EN_STRP +// GPIO_SKL_H_GPP_C3 - Not Owned by BIOS //ME SML0CLK +// GPIO_SKL_H_GPP_C4 - Not Owned by BIOS //ME SML0DATA + {GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_5_IRQ_SML0_ALERT_N +// GPIO_SKL_H_GPP_C6 - Not Owned by BIOS //ME SML1CLK +// GPIO_SKL_H_GPP_C7 - Not Owned by BIOS //ME SML1DATA + {GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_8_FM_PASSWORD_CLEAR_N + {GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_9_FM_MFG_MODE + {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//GPP_C_10_FM_PCH_SATA_RAID_KEY + {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_11_TP_FP_AUD_DETECT_N //FM_BOARD_REV_ID0 + {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_12_FM_BOARD_REV_ID0 //FM_BOARD_REV_ID1 + {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_13_FM_BOARD_REV_ID1 //FM_BOARD_REV_ID2 + {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_14_FM_BMC_PCH_SCI_LPC_N //TP_PCH_GPP_C_14 + {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_15_FM_RISER1_ID_0 //TP_PCH_GPP_C_15 + {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_16_FM_RISER1_ID_1 //TP_PCH_GPP_C_16 + {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_17_FM_RISER2_ID_0 //TP_PCH_GPP_C_17 + {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_18_FM_RISER2_ID_1 //TP_PCH_GPP_C_18 +// GPIO_SKL_H_GPP_C19 - Not Owned by BIOS //SMBus Smbus Mux GPIO reset GPP_C_19_RST_SMB_HOST_PCH_MUX_N +// GPIO_SKL_H_GPP_C20 - Not Owned by BIOS //ME PROCHOT MGPIO GPP_C_20_FM_THROTTLE_N + {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_21_RST_PCH_MIC_MUX_N //TP_PCH_GPP_C_21 + {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N //FM_BMC_PCH_SCI_LPC_N + {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_N + {GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntNmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI + {GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset,GpioTermNone, GpioPadConfigLock}},//GPP_D_1_FP_PWR_LED_N + {GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_2_FM_TBT_FORCE_PWR //TP_PCH_GPP_D_2 + {GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_3_FM_TBT_SCI_EVENT //TP_PCH_GPP_D_3 + {GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_4_FM_PLD_PCH_DATA + {GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_5_TP_PCH_GPP_D_5 //FM_OCP_MOD1_PRSNT_N + {GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_6_TP_PCH_GPP_D_6 + {GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_7_TP_PCH_GPP_D_7 + {GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_8_FM_UPLINK_SEL //TP_PCH_GPP_D_8 + {GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_9_TP_PCH_GPP_D_9 + {GPIO_SKL_H_GPP_D10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_10_FM_M2_2_SSD_DEVSLP //TP_PCH_GPP_D_10 + {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_11_TP_PCH_GPP_D_11 + {GPIO_SKL_H_GPP_D12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_12_SGPIO_SSATA_DATA1 //TP_PCH_GPP_D_12 + {GPIO_SKL_H_GPP_D13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_13_SMB_SMLINK5_STBY_LVC3_R_SCL //TP_PCH_GPP_D_13 + {GPIO_SKL_H_GPP_D14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_14_SMB_SMLINK5_STBY_LVC3_R_SDA //TP_PCH_GPP_D_14 + {GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_15_SGPIO_SSATA_DATA0 + {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_16_FM_ME_PFR_1 //FM_SLOT1_PRSNT + {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_17_FM_ME_PFR_2 //FM_SLOT2_PRSNT + {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_18_MCP_RESET_CTRL_N //TP_PCH_GPP_D_18 + {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_19_FM_PS_PWROK_DLY_SEL_R + {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_20_TP_PCH_GPP_D_20 + {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_21_TP_PCH_GPP_D_21 + {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_22_TP_PCH_GPP_D_22 + {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_23_TP_PCH_GPP_D_23 + {GPIO_SKL_H_GPP_E0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_0_FM_QAT_ENABLE_N //TP_PCH_GPP_E_0 + {GPIO_SKL_H_GPP_E1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_1_FM_QAT_ENABLE_N //TP_PCH_GPP_E_1 + {GPIO_SKL_H_GPP_E2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_2_FM_QAT_ENABLE_N //TP_PCH_GPP_E_2 + {GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_3_FM_ADR_TRIGGER_N + {GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_4_TP_PCH_GPP_E_4 //FM_CPU0_SSD0_PRSNT_N + {GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_5_TP_PCH_GPP_E_5 //FM_CPU0_SSD1_PRSNT_N + {GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_6_TP_PCH_GPP_E_6 //FM_CPU0_SSD2_PRSNT_N + {GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_7_FM_ADR_SMI_GPIO_R_N + {GPIO_SKL_H_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_8_LED_PCH_SATA_HDD_N //FM_CPU0_SSD3_PRSNT_N + {GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_9_FM_OC0_USB_N + {GPIO_SKL_H_GPP_E10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_10_FM_OC1_USB_N + {GPIO_SKL_H_GPP_E11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_11_PU_OC2_USB_N + {GPIO_SKL_H_GPP_E12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_12_PU_OC3_USB_N + {GPIO_SKL_H_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_0_FM_QAT_ENABLE_N //FM_OCP_MOD2_PRSNT_N + {GPIO_SKL_H_GPP_F1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_1_FM_QAT_ENABLE_N //TP_PCH_GPP_F_1 + {GPIO_SKL_H_GPP_F2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_2_FM_QAT_ENABLE_N //FM_EDSFF0_PRSNT0_N + {GPIO_SKL_H_GPP_F3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_3_FM_QAT_ENABLE_N //FM_EDSFF0_PRSNT1_N + {GPIO_SKL_H_GPP_F4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_4_FM_QAT_ENABLE_N //FM_BIOS_USB_RECOVERY + {GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_5_IRQ_TPM_SPI_N + {GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_6_JTAG_PCH_PLD_TCK //FM_EDSFF1_PRSNT0_N + {GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_7_JTAG_PCH_PLD_TDI //FM_EDSFF1_PRSNT1_N + {GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_8_JTAG_PCH_PLD_TMS //FM_EDSFF2_PRSNT0_N + {GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_9_JTAG_PCH_PLD_TDO //FM_EDSFF2_PRSNT1_N + {GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_10_SGPIO_SATA_CLOCK + {GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_11_SGPIO_SATA_LOAD + {GPIO_SKL_H_GPP_F12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_12_SGPIO_SATA_DATA1 + {GPIO_SKL_H_GPP_F13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_13_SGPIO_SATA_DATA0 + {GPIO_SKL_H_GPP_F14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_14_LED_PCH_SSATA_HDD_N //TP_PCH_GPP_F14 + {GPIO_SKL_H_GPP_F15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_15_FM_OC4_USB_N //FM_EDSFF3_PRSNT0_N + {GPIO_SKL_H_GPP_F16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_16_PU_OC5_USB_N //FM_EDSFF3_PRSNT1_N + {GPIO_SKL_H_GPP_F17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_17_FM_OC6_USB_N //FM_EDSFF4_PRSNT0_N + {GPIO_SKL_H_GPP_F18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_18_PU_OC7_USB_N //FM_EDSFF4_PRSNT1_N + {GPIO_SKL_H_GPP_F19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_19_SMB_GBE_STBY_LVC3_SCL //FM_EDSFF5_PRSNT0_N + {GPIO_SKL_H_GPP_F20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_20_SMB_GBE_STBY_LVC3_SDA //FM_EDSFF5_PRSNT1_N + {GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_21_TP_PCH_GPP_F_21 + {GPIO_SKL_H_GPP_F22, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_22_SGPIO_SSATA_CLOCK + {GPIO_SKL_H_GPP_F23, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_23_SGPIO_SSATA_LOAD + {GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_0_TP_FAN_PCH_TACH0 //FM_BOARD_SKU_ID0 + {GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_1_TP_FAN_PCH_TACH1 //FM_BOARD_SKU_ID1 + {GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_2_TP_FAN_PCH_TACH2 //FM_BOARD_SKU_ID2 + {GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_3_TP_FAN_PCH_TACH3 //FM_BOARD_SKU_ID3 + {GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_4_TP_FAN_PCH_TACH4 //FM_BOARD_SKU_ID4 + {GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_5_TP_FAN_PCH_TACH5 //FM_BOARD_SKU_ID5 + {GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_6_TP_FAN_PCH_TACH6 //FM_MIDPLANE_PCH_ID0 + {GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_7_TP_FAN_PCH_TACH7 //FM_MIDPLANE_PCH_ID1 + {GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_8_TP_FAN_PCH_PWM0 //FM_PCH_GPP_G8 + {GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_9_TP_FAN_PCH_PWM1 //FM_PCH_GPP_G9 + {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_10_TP_FAN_PCH_PWM2 //FM_PCH_GPP_G10 + {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_11_TP_FAN_PCH_PWM3 //FM_PCH_GPP_G11 + {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_12_GSXDOUT //IRQ_FORCE_NM_THROTTLE_N + {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_13_FM_BOARD_SKU_ID1 //TP_PCH_GPP_G_13 + {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_14_FM_BOARD_SKU_ID2 //TP_PCH_GPP_G_14 + {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_15_FM_BOARD_SKU_ID3 //TP_PCH_GPP_G_15 + {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_16_FM_BOARD_SKU_ID4 //TP_PCH_GPP_G_16 + {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_17_FM_ADR_COMPLETE + {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_18_IRQ_NMI_EVENT_N + {GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_19_IRQ_SMI_ACTIVE_N + {GPIO_SKL_H_GPP_G20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}}, //TP_PCH_GPP_G_20 + {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_21_FM_BIOS_IMAGE_SWAP_N //TP_PCH_GPP_G_21 + {GPIO_SKL_H_GPP_G22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_22_FM_M2_2_SSD_DEVSLP //TP_PCH_GPP_G_22 + {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_23_TP_PCH_GPP_G_23 + {GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_0_FM_PCH_MGPIO_TEST2 //FM_CLKREQ_M2_SSD_A_N + {GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_1_FM_SWAP_OVERRIDE_N //FM_CLKREQ_M2_SSD_B_N + {GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_2_FM_PCH_MGPIO_TEST0 //FM_ROWOL_ENABLE + {GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_3_FM_PCH_MGPIO_TEST1 //FM_ROWOL_LATCH + {GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_4_FM_PCH_MGPIO_TEST4 //TP_PCH_GPP_H_4 + {GPIO_SKL_H_GPP_H5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_5_FM_CLKREQ_M2_1_N //TP_PCH_GPP_H_5 + {GPIO_SKL_H_GPP_H6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_6_FM_CLKREQ_M2_2_N //TP_PCH_GPP_H_6 + {GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_7_FM_PCH_MGPIO_TEST3 //TP_PCH_GPP_H_7 + {GPIO_SKL_H_GPP_H8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_8_FM_CLKREQ_NIC1_N //TP_PCH_GPP_H_8 + {GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_9_FM_PCH_MGPIO_TEST5 //TP_PCH_GPP_H_9 +// GPIO_SKL_H_GPP_H10 - Not Owned by BIOS //ME SML2CLK +// GPIO_SKL_H_GPP_H11 - Not Owned by BIOS //ME SML2DATA + {GPIO_SKL_H_GPP_H12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_12_FM_ESPI_FLASH_MODE //IRQ_SML2_ALERT_N + {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_15_PU_ADR_TIMER_HOLD_OFF_N + {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_18_FM_LT_KEY_DOWNGRADE_N + {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_19_FM_PCH_10GBE_PCI_DISABLE_N //TP_PCH_GPP_H_19 + {GPIO_SKL_H_GPP_H20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_20_FM_SSATA_PCIE_M2_1_SEL //TP_PCH_GPP_H_20 + {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_21_FM_PCH_10GBE_LAN_DISABLE_N //TP_PCH_GPP_H_21 + {GPIO_SKL_H_GPP_H22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_22_FM_SSATA_PCIE_M2_2_SEL //TP_PCH_GPP_H_22 + {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_23_TP_PCH_GPP_H_23 + {GPIO_SKL_H_GPP_I0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_0_TP_PCH_GPP_I_0 + {GPIO_SKL_H_GPP_I1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_1_TP_PCH_GPP_I_1 + {GPIO_SKL_H_GPP_I2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_2_TP_PCH_GPP_I_2 + {GPIO_SKL_H_GPP_I3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_3_TP_PCH_GPP_I_3 + {GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_4_TP_PCH_GPP_I_4 + {GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_5_TP_PCH_GPP_I_5 + {GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_6_TP_PCH_GPP_I_6 + {GPIO_SKL_H_GPP_I7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_7_TP_PCH_GPP_I_7 + {GPIO_SKL_H_GPP_I8, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_8_FM_PCH_10GBE_PCI_DISABLE_N + {GPIO_SKL_H_GPP_I9, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_9_FM_PCH_10GBE_LAN_DISABLE_N + {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_10_TP_PCH_GPP_I_10 //FM_BIOS_MRC_DEBUG_MSG_DIS_N +// GPIO_SKL_H_GPP_I11 - Not Owned by BIOS +// GPIO_SKL_H_GPD0 - Not Owned by BIOS //ME FIVRBREAK + {GPIO_SKL_H_GPD1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_1_PU_ACPRESENT + {GPIO_SKL_H_GPD2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_2_FM_LAN_WAKE_N //RST_BMC_SRST_N + {GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_3_FM_PCH_PWRBTN_N + {GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_4_FM_SLPS3_N + {GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_5_FM_SLPS4_N + {GPIO_SKL_H_GPD6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_6_FM_SLPA_N + {GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_7_TP_GPD_7 + {GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_8_TP_GPD_8_SUSCLK + {GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_9_TP_GPD_9_SLP + {GPIO_SKL_H_GPD10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_10_FM_SLPS5_N + {GPIO_SKL_H_GPD11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_11_FM_PHY_DISABLE_N + {GPIO_SKL_H_GPP_J0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_0_TP_PCH_GPP_J_0 + {GPIO_SKL_H_GPP_J1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_1_TP_PCH_GPP_J_1 + {GPIO_SKL_H_GPP_J2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_2_TP_PCH_GPP_J_2 + {GPIO_SKL_H_GPP_J3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_3_TP_PCH_GPP_J_3 + {GPIO_SKL_H_GPP_J4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_4_TP_PCH_GPP_J_4 + {GPIO_SKL_H_GPP_J5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_5_TP_PCH_GPP_J_5 + {GPIO_SKL_H_GPP_J6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_6_TP_PCH_GPP_J_6 + {GPIO_SKL_H_GPP_J7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_7_TP_PCH_GPP_J_7 + {GPIO_SKL_H_GPP_J8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_8_TP_PCH_GPP_J_8 + {GPIO_SKL_H_GPP_J9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_9_TP_PCH_GPP_J_9 + {GPIO_SKL_H_GPP_J10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_10_TP_PCH_GPP_J_10 + {GPIO_SKL_H_GPP_J11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_11_TP_PCH_GPP_J_11 + {GPIO_SKL_H_GPP_J12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_12_TP_PCH_GPP_J_12 + {GPIO_SKL_H_GPP_J13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_13_TP_PCH_GPP_J_13 + {GPIO_SKL_H_GPP_J14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_14_TP_PCH_GPP_J_14 + {GPIO_SKL_H_GPP_J15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_15_TP_PCH_GPP_J_15 + {GPIO_SKL_H_GPP_J16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_16_TP_PCH_GPP_J_16 + {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_17_TP_PCH_GPP_J_17 + {GPIO_SKL_H_GPP_J18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_18_TP_PCH_GPP_J_18 + {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_19_TP_PCH_GPP_J_19 + {GPIO_SKL_H_GPP_J20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_20_TP_PCH_GPP_J_20 + {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_21_TP_PCH_GPP_J_21 + {GPIO_SKL_H_GPP_J22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_22_TP_PCH_GPP_J_22 + {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_23_TP_PCH_GPP_J_23 + {GPIO_SKL_H_GPP_K0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_0_CLK_50M_CKMNG_PCH + {GPIO_SKL_H_GPP_K1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_1_RMII_BMC_PCH_TXD0 + {GPIO_SKL_H_GPP_K2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_2_RMII_BMC_PCH_TXD1 + {GPIO_SKL_H_GPP_K3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_3_RMII_BMC_PCH_TX_EN + {GPIO_SKL_H_GPP_K4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_4_RMII_PCH_BMC_CRS_DV + {GPIO_SKL_H_GPP_K5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_5_RMII_PCH_BMC_RXD0 + {GPIO_SKL_H_GPP_K6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_6_RMII_PCH_BMC_RXD1 + {GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_7_RMII_PCH_BMC_RX_ER + {GPIO_SKL_H_GPP_K8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_8_RMII_PCH_CONN_ARB_IN + {GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_9_RMII_PCH_CONN_ARB_OUT + {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_10_RST_PCIE_PCH_PERST_N +// GPIO_SKL_H_GPP_K11 - Not Owned by BIOS + {GPIO_SKL_H_GPP_L2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_2_TRC_2CH0_D0 + {GPIO_SKL_H_GPP_L3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_3_TRC_2CH0_D1 + {GPIO_SKL_H_GPP_L4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_4_TRC_2CH0_D2 + {GPIO_SKL_H_GPP_L5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_5_TRC_2CH0_D3 + {GPIO_SKL_H_GPP_L6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_6_TRC_2CH0_D4 + {GPIO_SKL_H_GPP_L7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_7_TRC_2CH0_D5 + {GPIO_SKL_H_GPP_L8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_8_TRC_2CH0_D6 + {GPIO_SKL_H_GPP_L9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_9_TRC_2CH0_D7 + {GPIO_SKL_H_GPP_L10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_10_TRC_2CH0_CLK + {GPIO_SKL_H_GPP_L11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_11_TRC_2CH1_D0 + {GPIO_SKL_H_GPP_L12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_12_TRC_2CH1_D1 + {GPIO_SKL_H_GPP_L13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_13_TRC_2CH1_D2 + {GPIO_SKL_H_GPP_L14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_14_TRC_2CH1_D3 + {GPIO_SKL_H_GPP_L15, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_15_TRC_2CH1_D4 + {GPIO_SKL_H_GPP_L16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_16_TRC_2CH1_D5 + {GPIO_SKL_H_GPP_L17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_17_TRC_2CH1_D6 + {GPIO_SKL_H_GPP_L18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_18_TRC_2CH1_D7 + {GPIO_SKL_H_GPP_L19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_19_TRC_2CH1_CLK +}; + +EFI_STATUS +TypeTucanaInstallGpioData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status = UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformGpioInitDataGuid, + &mGpioTableTucana, + sizeof(mGpioTableTucana) + ); + Status = PcdSet32S (PcdOemSku_GPIO_TABLE_SIZE, sizeof (mGpioTableTucana)); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/IioBifurInit.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/IioBifurInit.c new file mode 100644 index 0000000000..16e266fb94 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/IioBifurInit.c @@ -0,0 +1,239 @@ +/** @file + IIO Config Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include <Library/UbaIioConfigLib.h> +#include <IioPlatformData.h> + +typedef enum { + Iio_Socket0 = 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 = 0, + Iio_Iou1, + Iio_Iou2, + Iio_Iou3, + Iio_Iou4, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + VPP_PORT_0 = 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORT; + +#define ENABLE 1 +#define DISABLE 0 + +static IIO_BIFURCATION_DATA_ENTRY_EX IioBifurcationTable[] = +{ + + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_x4x4xxx8, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxx8xxx8, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxx8xxx8, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou3, IIO_BIFURCATE_xxx8x4x4, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX } +}; +//[-start-210223-Enhance_Dynamic_Type9-modify]// +static IIO_SLOT_CONFIG_DATA_ENTRY_EX IioSlotTable[] = { + // Port Index | Slot |Interlock |power |Power |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer |Retimer |Mux |Mux |ExtnCard |ExtnCard |ExtnCard |ExtnCard |ExtnCard Retimer|ExtnCard Retimer|ExtnCard |ExtnCard Hotplug|ExtnCard Hotplug|Max Retimer| + // | | |Limit Scale |Limit Value |Cap | | |Cap |Port |Address | |Clock | |Port | |Address |Channel |Width |Address |Channel |Support |SMBus Port |SMBus Addr |Retimer |SMBus Address |Width |Hotplug |Vpp Port |Vpp Address | | + {SOCKET_0_INDEX + + PORT_1A_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1C_INDEX, 2 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1D_INDEX, 3 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2A_INDEX, 4 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2C_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_4A_INDEX, 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_5A_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_5B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_5C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_5D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + + {SOCKET_1_INDEX + + PORT_1A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_2A_INDEX, 9 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_2C_INDEX, 10 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4A_INDEX, 11 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4B_INDEX, 12 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4C_INDEX, 13 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_5A_INDEX, 14 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_5B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_5C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_5D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 } +}; + +EFI_STATUS +UpdateTucanaIioConfig ( + IN IIO_GLOBALS *IioGlobalData + ) +{ + return EFI_SUCCESS; +} + +PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX TypeTucanaIioConfigTable = +{ + PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE, + PLATFORM_IIO_CONFIG_UPDATE_VERSION_2, + + IioBifurcationTable, + sizeof(IioBifurcationTable), + UpdateTucanaIioConfig, + IioSlotTable, + sizeof(IioSlotTable) +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +TypeTucanaIioPortBifurcationInit ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX *PlatformIioInfoPtr; + UINTN PlatformIioInfoSize; + + GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob != NULL); + if (GuidHob == NULL) { + return EFI_NOT_FOUND; + } + + // + // This is config for ICX + // + PlatformIioInfoPtr = &TypeTucanaIioConfigTable; + PlatformIioInfoSize = sizeof(TypeTucanaIioConfigTable); + + Status = UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_1, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_2, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_3, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/KtiEparam.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/KtiEparam.c new file mode 100644 index 0000000000..6940277c90 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/KtiEparam.c @@ -0,0 +1,66 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include <KtiSetupDefinitions.h> +#include <UbaKti.h> + +extern EFI_GUID gPlatformKtiEparamUpdateDataGuid; + +ALL_LANES_EPARAM_LINK_INFO KtiTucanaIcxAllLanesEparamTable[] = { + // + // SocketID, Freq, Link, TXEQL, CTLEPEAK + // Please propagate changes to WilsonCitySMT and WilsonCityModular UBA KtiEparam tables + // + // + // Socket 0 + // + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2B33373F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK1), 0x2A33363F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK2), 0x2B34363F, ADAPTIVE_CTLE}, + // + // Socket 1 + // + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2A31383F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK1), 0x2A30393F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK2), 0x2C34373F, ADAPTIVE_CTLE} +}; + +PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeTucanaIcxKtiEparamUpdate = { + PLATFORM_KTIEP_UPDATE_SIGNATURE, + PLATFORM_KTIEP_UPDATE_VERSION, + KtiTucanaIcxAllLanesEparamTable, + sizeof (KtiTucanaIcxAllLanesEparamTable), + NULL, + 0 +}; + + +EFI_STATUS +TypeTucanaInstallKtiEparamData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + + GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob != NULL); + if (GuidHob == NULL) { + return EFI_NOT_FOUND; + } + Status = UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformKtiEparamUpdateDataGuid, + &TypeTucanaIcxKtiEparamUpdate, + sizeof(TypeTucanaIcxKtiEparamUpdate) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PcdData.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PcdData.c new file mode 100644 index 0000000000..cb307e6232 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PcdData.c @@ -0,0 +1,275 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include <ImonVrSvid.h> +#include <Library/MemVrSvidMapLib.h> +#include <Guid/PlatformInfo.h> +#include <Library/UbaPcdUpdateLib.h> +#include <Library/PcdLib.h> +#include <UncoreCommonIncludes.h> +#include <Ppi/DynamicSiLibraryPpi.h> +#include <CpuAndRevisionDefines.h> + +#define GPIO_SKL_H_GPP_B20 0x01010014 + +VOID TypeTucanaPlatformUpdateVrIdAddress (VOID); + +/** + Update Tucana IMON SVID Information + + retval N/A +**/ +VOID +TypeTucanaPlatformUpdateImonAddress ( + VOID + ) +{ + VCC_IMON *VccImon = NULL; + UINTN Size = 0; + + Size = sizeof (VCC_IMON); + VccImon = (VCC_IMON *) PcdGetPtr (PcdImonAddr); + if (VccImon == NULL) { + DEBUG ((DEBUG_ERROR, "UpdateImonAddress() - PcdImonAddr == NULL\n")); + return; + } + + VccImon->VrSvid[0] = PcdGet8 (PcdWilsonCitySvidVrP1V8); + VccImon->VrSvid[1] = PcdGet8 (PcdWilsonCitySvidVrVccAna); + VccImon->VrSvid[2] = IMON_ADDR_LIST_END; // End array with 0xFF + + PcdSetPtrS (PcdImonAddr, &Size, (VOID *) VccImon); +} + +/** + Update WilsonCity VR ID SVID Information + + retval N/A +**/ +VOID +TypeTucanaPlatformUpdateVrIdAddress ( + VOID + ) +{ + MEM_SVID_MAP *MemSvidMap = NULL; + UINTN Size = 0; + + Size = sizeof (MEM_SVID_MAP); + MemSvidMap = (MEM_SVID_MAP *) PcdGetPtr (PcdMemSrvidMap); + if (MemSvidMap == NULL) { + DEBUG ((DEBUG_ERROR, "UpdateVrIdAddress() - PcdMemSrvidMap == NULL\n")); + return; + } + /* + Map VR ID Address to Memory controller + The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14, and 0x16. + Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs (VR ID's 0x10 and 0x12). + Those are typically shared such that MC0/MC2 share the same DDR VR (as they are on the same side of the CPU) + and MC1/MC3 share the other. Depending on motherboard layout and other design constraints, this could change + BIT 4 => 0 or 1, SVID BUS\Interface 0 or 1 respectively + BIT 0:3 => SVID ADDRESS + */ + + MemSvidMap->Socket[0].Mc[0] = 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[0].Mc[1] = 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[1].Mc[0] = 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[1].Mc[1] = 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[2].Mc[0] = 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[2].Mc[1] = 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[3].Mc[0] = 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[3].Mc[1] = 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[4].Mc[0] = 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[4].Mc[1] = 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[5].Mc[0] = 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[5].Mc[1] = 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[6].Mc[0] = 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[6].Mc[1] = 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[7].Mc[0] = 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[7].Mc[1] = 0x12; //SVID BUS 1, ADDR 2 + + PcdSetPtrS (PcdMemSrvidMap, &Size, (VOID *) MemSvidMap); +} + +EFI_STATUS +TypeTucanaPlatformPcdUpdateCallback ( + VOID +) +{ + CHAR8 FamilyName[] = "Whitley"; + + CHAR8 BoardName[] = "EPRP"; + UINT32 Data32; + UINTN Size; + UINTN PlatformFeatureFlag = 0; + + CHAR16 PlatformName[] = L"TypeTucana"; + UINTN PlatformNameSize = 0; + EFI_STATUS Status; + + //#Integer for BoardID, must match the SKU number and be unique. + Status = PcdSet16S (PcdOemSkuBoardID , TypeTucana); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status = PcdSet16S (PcdOemSkuBoardFamily , 0x30); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + // Number of Sockets on Board. + Status = PcdSet32S (PcdOemSkuBoardSocketCount, 2); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + // Max channel and max DIMM + Status = PcdSet32S (PcdOemSkuMaxChannel , 8); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status = PcdSet32S (PcdOemSkuMaxDimmPerChannel , 2); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status = PcdSetBoolS (PcdOemSkuDimmLayout, TRUE); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //Update Onboard Video Controller PCI Ven_id, Dev_id + Status = PcdSet16S (PcdOnboardVideoPciVendorId, 0x1A03); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = PcdSet16S (PcdOnboardVideoPciDeviceId, 0x2000); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# + //# Misc. + //# + //# V_PCIE_PORT_PXPSLOTCTRL_ATNLED_OFF + Status = PcdSet16S (PcdOemSkuMrlAttnLed , 0xc0); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //SDP Active Flag + Status = PcdSet8S (PcdOemSkuSdpActiveFlag , 0x0); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Zero terminated string to ID family + Size = AsciiStrSize (FamilyName); + Status = PcdSetPtrS (PcdOemSkuFamilyName , &Size, FamilyName); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Zero terminated string to Board Name + Size = AsciiStrSize (BoardName); + Status = PcdSetPtrS (PcdOemSkuBoardName , &Size, BoardName); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + PlatformNameSize = sizeof (PlatformName); + Status = PcdSet32S (PcdOemSkuPlatformNameSize , (UINT32)PlatformNameSize); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status = PcdSetPtrS (PcdOemSkuPlatformName , &PlatformNameSize, PlatformName); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# FeaturesBasedOnPlatform + Status = PcdSet32S (PcdOemSkuPlatformFeatureFlag , (UINT32)PlatformFeatureFlag); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Assert GPIO + Data32 = 0; + Status = PcdSet32S (PcdOemSkuAssertPostGPIOValue, Data32); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status = PcdSet32S (PcdOemSkuAssertPostGPIO, GPIO_SKL_H_GPP_B20); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# UplinkPortIndex + Status = PcdSet8S (PcdOemSkuUplinkPortIndex, 5); + if (EFI_ERROR(Status)) { + return Status; + } + + DEBUG ((DEBUG_INFO, "Uba Callback: PlatformPcdUpdateCallback is called!\n")); + Status = TypeTucanaPlatformUpdateAcpiTablePcds (); + //# BMC Pcie Port Number + PcdSet8S (PcdOemSkuBmcPciePortNumber, 5); + ASSERT_EFI_ERROR(Status); + + //# Board Type Bit Mask + PcdSet32S (PcdBoardTypeBitmask, CPU_TYPE_F_MASK | (CPU_TYPE_F_MASK << 4)); + ASSERT_EFI_ERROR(Status); + + //Update IMON Address + TypeTucanaPlatformUpdateImonAddress (); + + return Status; +} + +PLATFORM_PCD_UPDATE_TABLE TypeTucanaPcdUpdateTable = +{ + PLATFORM_PCD_UPDATE_SIGNATURE, + PLATFORM_PCD_UPDATE_VERSION, + TypeTucanaPlatformPcdUpdateCallback +}; + +EFI_STATUS +TypeTucanaInstallPcdData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status = UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPcdConfigDataGuid, + &TypeTucanaPcdUpdateTable, + sizeof(TypeTucanaPcdUpdateTable) + ); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PchEarlyUpdate.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PchEarlyUpdate.c new file mode 100644 index 0000000000..43b83d3996 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PchEarlyUpdate.c @@ -0,0 +1,93 @@ +/** @file + Pch Early update. + + @copyright + Copyright 2019 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" + +#include <Library/UbaPchEarlyUpdateLib.h> + +#include <PchAccess.h> +#include <GpioPinsSklH.h> +#include <Library/GpioLib.h> +#include <Ppi/DynamicSiLibraryPpi.h> + +EFI_STATUS +TypeTucanaPchLanConfig ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL; + EFI_STATUS Status; + + Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, (VOID **) &DynamicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DynamicSiLibraryPpi->GpioSetOutputValue (GPIO_SKL_H_GPP_I9, (UINT32)SystemConfig->LomDisableByGpio); + DynamicSiLibraryPpi->PchDisableGbe (); + + return EFI_SUCCESS; +} + +EFI_STATUS +TypeTucanaOemInitLateHook ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + return EFI_SUCCESS; +} + + +PLATFORM_PCH_EARLY_UPDATE_TABLE TypeTucanaPchEarlyUpdateTable = +{ + PLATFORM_PCH_EARLY_UPDATE_SIGNATURE, + PLATFORM_PCH_EARLY_UPDATE_VERSION, + TypeTucanaPchLanConfig, + TypeTucanaOemInitLateHook +}; + + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +EFIAPI +TypeTucanaPchEarlyUpdate( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + EFI_STATUS Status; + + Status = PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + (VOID **) &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPchEarlyConfigDataGuid, + &TypeTucanaPchEarlyUpdateTable, + sizeof(TypeTucanaPchEarlyUpdateTable) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PeiBoardInit.h b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PeiBoardInit.h new file mode 100644 index 0000000000..009bed5a13 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PeiBoardInit.h @@ -0,0 +1,78 @@ +/** @file + PeiBoardInit. + + @copyright + Copyright 2018 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_BOARD_INIT_PEIM_H_ +#define _PEI_BOARD_INIT_PEIM_H_ + +#include <Library/BaseLib.h> +#include <Library/DebugLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Ppi/UbaCfgDb.h> +#include <Guid/PlatformInfo.h> +#include <Library/PeiServicesLib.h> +#include <Library/HobLib.h> +#include <Library/PeiServicesTablePointerLib.h> +#include <Library/GpioLib.h> +#include <GpioPinsSklH.h> +#include <Ppi/DynamicSiLibraryPpi.h> + +// TypeTucana +EFI_STATUS +TypeTucanaPlatformUpdateUsbOcMappings ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeTucanaPlatformUpdateAcpiTablePcds ( + VOID +); + +EFI_STATUS +TypeTucanaInstallClockgenData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeTucanaInstallPcdData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeTucanaPchEarlyUpdate ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeTucanaIioPortBifurcationInit ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeTucanaInstallSlotTableData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeTucanaInstallKtiEparamData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +// TypeTucana +EFI_STATUS +TypeTucanaInstallGpioData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) ; + +EFI_STATUS +TypeTucanaInstallSoftStrapData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); +#endif // _PEI_BOARD_INIT_PEIM_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PeiBoardInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PeiBoardInitLib.c new file mode 100644 index 0000000000..9e7c62ee77 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PeiBoardInitLib.c @@ -0,0 +1,157 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation. + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + +/** + The constructor function for Board Init Libray. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS Table initialization successfully. + @retval EFI_OUT_OF_RESOURCES No enough memory to initialize table. +**/ + +#include "PeiBoardInit.h" +#include <UncoreCommonIncludes.h> +#include <Library/PchMultiPchBase.h> +#include <Ppi/DynamicSiLibraryPpi.h> + +EFI_STATUS +EFIAPI +TypeTucanaPeiBoardInitLibConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + UINT8 SocketIndex; + UINT8 ChannelIndex; + + GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob != NULL); + if (GuidHob == NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo = GET_GUID_HOB_DATA(GuidHob); + + if (PlatformInfo->BoardId == TypeTucana) { + + DEBUG ((DEBUG_INFO, "PEI UBA init BoardId 0x%X: Tucana\n", PlatformInfo->BoardId)); + + // Socket 0 has SMT DIMM connector, Socket 1 has PTH DIMM connector + for (SocketIndex = 0; SocketIndex < MAX_SOCKET; SocketIndex++) { + for (ChannelIndex = 0; ChannelIndex < MAX_CH; ChannelIndex++) { + switch (SocketIndex) { + case 0: + PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = DimmConnectorSmt; + break; + case 1: + // Fall through since socket 1 is PTH type + default: + // Use the more restrictive type as the default case + PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = DimmConnectorPth; + break; + } + } + } + + BuildGuidDataHob ( + &gEfiPlatformInfoGuid, + &(PlatformInfo), + sizeof (EFI_PLATFORM_INFO) + ); + + Status = PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + (VOID **) &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = UbaConfigPpi->InitSku ( + UbaConfigPpi, + PlatformInfo->BoardId, + NULL, + NULL + ); + ASSERT_EFI_ERROR (Status); + + Status = TypeTucanaInstallGpioData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = TypeTucanaInstallPcdData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = TypeTucanaInstallSoftStrapData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = TypeTucanaPchEarlyUpdate (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = TypeTucanaPlatformUpdateUsbOcMappings (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = TypeTucanaInstallSlotTableData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = TypeTucanaInstallKtiEparamData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + for (SocketIndex = 0; SocketIndex < MAX_SOCKET; SocketIndex++) { + + // + // Set default memory type connector. + // Socket 0: DimmConnectorSmt + // Socket 1: DimmConnectorPth + // + if (SocketIndex % 2 == 0) { + (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketIndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnectorSmt); + } else { + (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketIndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnectorPth); + } + } + + // + // Initialize InterposerType to InterposerUnknown + // + for (SocketIndex = 0; SocketIndex < MAX_SOCKET; ++SocketIndex) { + PlatformInfo->InterposerType[SocketIndex] = InterposerUnknown; + } + + // + // TypeTucanaIioPortBifurcationInit will use PlatformInfo->InterposerType for PPO. + // + Status = TypeTucanaIioPortBifurcationInit (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + } + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PeiBoardInitLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PeiBoardInitLib.inf new file mode 100644 index 0000000000..aba186a70a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/PeiBoardInitLib.inf @@ -0,0 +1,178 @@ +## @file +# Component information file for BoardInitLib in PEI post memory phase. +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation. +# Copyright (c) 2021, American Megatrends International LLC. <BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Specification Reference: +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = TypeTucanaPeiBoardInitLib + FILE_GUID = b7dc947f-aa57-481c-b6c8-492a27a10a23 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + LIBRARY_CLASS = NULL|PEIM + CONSTRUCTOR = TypeTucanaPeiBoardInitLibConstructor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PeiServicesLib + HobLib + PeiServicesTablePointerLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[Sources] + PeiBoardInitLib.c + GpioTable.c + PcdData.c + UsbOC.c + AcpiTablePcds.c + IioBifurInit.c + SlotTable.c + KtiEparam.c + PchEarlyUpdate.c + SoftStrapFixup.c + PeiBoardInit.h + +[FixedPcd] + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + gOemSkuTokenSpaceGuid.PcdOemSkuBoardID + gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID + gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily + + gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName + gOemSkuTokenSpaceGuid.PcdOemSkuBoardName + + gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount + + gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel + gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel + gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13 + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13 + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05 + + gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName + + gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed + gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag + + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE + + gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32 + + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11 + + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue + gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber + gOemSkuTokenSpaceGuid.PcdOemTableIdXhci + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex + gPlatformTokenSpaceGuid.PcdBoardTypeBitmask + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8 + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna + gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr + gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap + + gPlatformTokenSpaceGuid.PcdMemInterposerMap + gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId + gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId + +[Ppis] + gUbaConfigDatabasePpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Guids] + gPlatformGpioInitDataGuid + gPlatformIioConfigDataGuid + gPlatformIioConfigDataGuid_1 + gPlatformIioConfigDataGuid_2 + gPlatformIioConfigDataGuid_3 + gPlatformPcdConfigDataGuid + gPlatformPchEarlyConfigDataGuid + gPlatformSlotDataGuid + gPlatformSlotDataGuid2 + gPlatformPciSlotImplementedGuid + gPlatformPchSoftStrapConfigDataGuid + gPeiPlatformUbaOcConfigDataGuid + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/SlotTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/SlotTable.c new file mode 100644 index 0000000000..0144d40cc8 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/SlotTable.c @@ -0,0 +1,172 @@ +/** @file + Slot Table Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include <Library/UbaSlotUpdateLib.h> +#include <IioPlatformData.h> + +#define PCI_DEVICE_ON_BOARD_TRUE 0 +#define PCI_DEVICE_ON_BOARD_FALSE 1 + +typedef enum { + Iio_Socket0 = 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =0, + Iio_Iou1, + Iio_Iou2, + Iio_Iou3, + Iio_Iou4, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Bw5_Addr_0 = 0, + Bw5_Addr_1, + Bw5_Addr_2, + Bw5_Addr_3, + Bw5_Addr_Max +} BW5_ADDRESS; + +static UINT8 TypeTucanaPchPciSlotImpementedTableData[] = { + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 0 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 1 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 2 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 3 + PCI_DEVICE_ON_BOARD_TRUE, // Root Port 4 + PCI_DEVICE_ON_BOARD_TRUE, // Root Port 5 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 6 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 7 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 8 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 9 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 10 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 11 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 12 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 13 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 14 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 15 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 16 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 17 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 18 + PCI_DEVICE_ON_BOARD_FALSE // Root Port 19 +}; + +UINT8 +GetTypeTucanaIOU0Setting ( + UINT8 IOU0Data +) +{ + // + // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled. + // + IOU0Data = IIO_BIFURCATE_xxx8xxx8; + return IOU0Data; +} + +UINT8 +GetTypeTucanaIOU2Setting ( + UINT8 SkuPersonalityType, + UINT8 IOU2Data +) +{ + return IOU2Data; +} + +static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeTucanaBroadwayTable[] = { + {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 }, + {Iio_Socket1, Iio_Iou1, Bw5_Addr_2}, + {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 }, +}; + + +PLATFORM_SLOT_UPDATE_TABLE TypeTucanaSlotTable = +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeTucanaBroadwayTable, + GetTypeTucanaIOU0Setting, + 0 +}; + +PLATFORM_SLOT_UPDATE_TABLE2 TypeTucanaSlotTable2 = +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeTucanaBroadwayTable, + GetTypeTucanaIOU0Setting, + 0, + GetTypeTucanaIOU2Setting +}; + +PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE TypeTucanaPchPciSlotImplementedTable = { + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + TypeTucanaPchPciSlotImpementedTableData +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +TypeTucanaInstallSlotTableData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status = UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformSlotDataGuid, + &TypeTucanaSlotTable, + sizeof(TypeTucanaSlotTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformSlotDataGuid2, + &TypeTucanaSlotTable2, + sizeof(TypeTucanaSlotTable2) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status = UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPciSlotImplementedGuid, + &TypeTucanaPchPciSlotImplementedTable, + sizeof(TypeTucanaPchPciSlotImplementedTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/SoftStrapFixup.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/SoftStrapFixup.c new file mode 100644 index 0000000000..3d0bab5e72 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/SoftStrapFixup.c @@ -0,0 +1,121 @@ +/** @file + Soft Strap update. + + @copyright + Copyright 2018 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include <Library/UbaSoftStrapUpdateLib.h> + +PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY TypeTucanaSoftStrapTable[] = +{ +// SoftStrapNumber, LowBit, BitLength, Value + {3, 1, 1, 0x1 }, // Intel QuickAssist Endpoint 2 (EP[2]) Primary Mux Select + {4, 24, 1, 0x0 }, // 10 GbE MAC Power Gate Control + {15, 4, 2, 0x3 }, // sSATA / PCIe Select for Port 2 (SATA_PCIE_SP2) + {15, 6, 2, 0x1 }, // sSATA / PCIe Select for Port 3 (SATA_PCIE_SP3) + {15, 18, 1, 0x1 }, // Polarity of GPP_H20 (GPIO polarity of Select between sSATA Port 2 and PCIe Port 8) + {16, 4, 2, 0x3 }, // sSATA / PCIe GP Select for Port 2 (SATA_PCIE_GP2) + {16, 6, 2, 0x1 }, // sSATA / PCIe GP Select for Port 3 (SATA_PCIE_GP3) + {17, 6, 1, 0x0 }, // Intel (R) GbE Legacy PHY over PCIe Enabled + {17, 12, 2, 0x3 }, // sSATA / PCIe Combo Port 2 + {18, 0, 2, 0x1 }, // sSATA / PCIe Combo Port 3 + {18, 6, 2, 0x3 }, // SATA / PCIe Combo Port 0 + {18, 8, 2, 0x3 }, // SATA / PCIe Combo Port 1 + {18, 10, 2, 0x3 }, // SATA / PCIe Combo Port 2 + {18, 12, 2, 0x3 }, // SATA / PCIe Combo Port 3 + {18, 14, 2, 0x3 }, // SATA / PCIe Combo Port 4 + {19, 2, 1, 0x1 }, // Polarity Select sSATA / PCIe Combo Port 2 + {19, 16, 2, 0x3 }, // SATA / PCIe Combo Port 5 + {19, 18, 2, 0x3 }, // SATA / PCIe Combo Port 6 + {19, 20, 2, 0x3 }, // SATA / PCIe Combo Port 7 + {19, 26, 1, 0x1 }, // Statically assign PCH PCIe NP8 Uplink to act as Downlink or Uplink(PCIEUDS) + {33, 24, 7, 0x17}, // IE SMLink1 I2C Target Address + {64, 24, 7, 0x17}, // ME SMLink1 I2C Target Address + {84, 24, 1, 0x0 }, // SMS1 Gbe Legacy MAC SMBus Address Enable + {85, 8, 3, 0x0 }, // SMS1 PMC SMBus Connect + {88, 8, 2, 0x3 }, // Root Port Configuration 0 + {93, 0, 2, 0x3 }, // Flex IO Port 18 AUXILLARY Mux Select between SATA Port 0 and PCIe Port 12 + {93, 2, 2, 0x3 }, // Flex IO Port 19 AUXILLARY Mux Select between SATA Port 1 and PCIe Port 13 + {93, 4, 2, 0x3 }, // Flex IO Port 20 AUXILLARY Mux Select between SATA Port 2 and PCIe Port 14 + {94, 0, 2, 0x3 }, // Flex IO Port 21 AUXILLARY Mux Select between SATA Port 3 and PCIe Port 15 + {94, 2, 2, 0x3 }, // Flex IO Port 22 AUXILLARY Mux Select between SATA Port 4 and PCIe Port 16 + {94, 4, 2, 0x3 }, // Flex IO Port 23 AUXILLARY Mux Select between SATA Port 5 and PCIe Port 17 + {94, 6, 2, 0x3 }, // Flex IO Port 24 AUXILLARY Mux Select between SATA Port 6 and PCIe Port 18 + {94, 8, 2, 0x3 }, // Flex IO Port 25 AUXILLARY Mux Select between SATA Port 7 and PCIe Port 19 + {102, 0, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 0 and PCIe Port 12 + {102, 2, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 1 and PCIe Port 13 + {102, 4, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 2 and PCIe Port 14 + {102, 6, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 3 and PCIe Port 15 + {102, 8, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 4 and PCIe Port 16 + {102, 10, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 5 and PCIe Port 17 + {102, 12, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 6 and PCIe Port 18 + {102, 14, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 7 and PCIe Port 19 + {103, 16, 3, 0x0 }, // GbE Legacy PHY Smbus Connection + {103, 26, 1, 0x0 }, // GbE Legacy LCD SMBus PHY Address Enabled + {103, 27, 1, 0x0 }, // GbE Legacy LC SMBus Address Enabled +// {133, 1, 1, 0x1 }, // Dual I/O Read Enabled +// {133, 2, 1, 0x1 }, // Quad Output Read Enabled +// {133, 3, 1, 0x1 }, // Quad I/O Read Enabled +// {136, 10, 2, 0x3 }, // eSPI / EC Maximum I/O Mode +// {136, 12, 1, 0x1 }, // Slave 1 (2nd eSPI device) Enable +// {136, 16, 3, 0x4 }, // eSPI / EC Slave 1 Device Bus Frequency +// {136, 19, 2, 0x3 }, // eSPI / EC Slave Device Maximum I/O Mode + +// +// END OF LIST +// + {0, 0, 0, 0} +}; + +UINT32 +TypeTucanaSystemBoardRevIdValue (VOID) +{ + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT(GuidHob != NULL); + if (GuidHob == NULL) { + return 0xFF; + } + PlatformInfo = GET_GUID_HOB_DATA(GuidHob); + return PlatformInfo->TypeRevisionId; +} + +VOID +TypeTucanaPlatformSpecificUpdate ( + IN OUT UINT8 *FlashDescriptorCopy + ) +{ +} + +PLATFORM_PCH_SOFTSTRAP_UPDATE TypeTucanaSoftStrapUpdate = +{ + PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE, + PLATFORM_SOFT_STRAP_UPDATE_VERSION, + TypeTucanaSoftStrapTable, + TypeTucanaPlatformSpecificUpdate +}; + +EFI_STATUS +TypeTucanaInstallSoftStrapData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + EFI_STATUS Status; + + Status = UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPchSoftStrapConfigDataGuid, + &TypeTucanaSoftStrapUpdate, + sizeof(TypeTucanaSoftStrapUpdate) + ); + + return Status; +} + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/UsbOC.c b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/UsbOC.c new file mode 100644 index 0000000000..82d44adde1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/Uba/TypeTucana/Pei/UsbOC.c @@ -0,0 +1,127 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation. <BR> + Copyright (c) 2021, American Megatrends International LLC. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" + + +#include <Library/PcdLib.h> +#include <Library/UbaUsbOcUpdateLib.h> +#include <PchLimits.h> +#include <ConfigBlock/UsbConfig.h> +#include <ConfigBlock/Usb2PhyConfig.h> + +USB_OVERCURRENT_PIN TypeTucanaUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = { + UsbOverCurrentPin0, + UsbOverCurrentPin1, + UsbOverCurrentPin1, + UsbOverCurrentPin2, + UsbOverCurrentPin3, + UsbOverCurrentPin3, + UsbOverCurrentPin7, + UsbOverCurrentPin7, + UsbOverCurrentPin6, + UsbOverCurrentPin4, + UsbOverCurrentPin6, + UsbOverCurrentPin4, + UsbOverCurrentPin5, + UsbOverCurrentPin4, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB_OVERCURRENT_PIN TypeTucanaUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = { + UsbOverCurrentPin0, + UsbOverCurrentPin1, + UsbOverCurrentPin1, + UsbOverCurrentPin2, + UsbOverCurrentPin3, + UsbOverCurrentPin3, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB2_PHY_PARAMETERS TypeTucanaUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS] = { + {3, 0, 3, 1}, // PP0 + {5, 0, 3, 1}, // PP1 + {3, 0, 3, 1}, // PP2 + {0, 5, 1, 1}, // PP3 + {3, 0, 3, 1}, // PP4 + {3, 0, 3, 1}, // PP5 + {3, 0, 3, 1}, // PP6 + {3, 0, 3, 1}, // PP7 + {2, 2, 1, 0}, // PP8 + {6, 0, 2, 1}, // PP9 + {2, 2, 1, 0}, // PP10 + {6, 0, 2, 1}, // PP11 + {0, 5, 1, 1}, // PP12 + {7, 0, 2, 1}, // PP13 + }; + +EFI_STATUS +TypeTucanaPlatformUsbOcUpdateCallback ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +) +{ + *Usb20OverCurrentMappings = &TypeTucanaUsb20OverCurrentMappings[0]; + *Usb30OverCurrentMappings = &TypeTucanaUsb30OverCurrentMappings[0]; + + *Usb20AfeParams = TypeTucanaUsb20AfeParams; + return EFI_SUCCESS; +} + +PLATFORM_USBOC_UPDATE_TABLE TypeTucanaUsbOcUpdate = +{ + PLATFORM_USBOC_UPDATE_SIGNATURE, + PLATFORM_USBOC_UPDATE_VERSION, + TypeTucanaPlatformUsbOcUpdateCallback +}; + +EFI_STATUS +TypeTucanaPlatformUpdateUsbOcMappings ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + //# + //# USB, see PG 104 in GZP SCH + //# + +// USB2 USB3 Port OC +// +//Port00: PORT5 Back Panel ,OC0# +//Port01: PORT2 Back Panel ,OC0# +//Port02: PORT3 Back Panel ,OC1# +//Port03: PORT0 NOT USED ,NA +//Port04: BMC1.0 ,NA +//Port05: INTERNAL_2X5_A ,OC2# +//Port06: INTERNAL_2X5_A ,OC2# +//Port07: NOT USED ,NA +//Port08: EUSB (AKA SSD) ,NA +//Port09: INTERNAL_TYPEA ,OC6# +//Port10: PORT1 Front Panel ,OC5# +//Port11: NOT USED ,NA +//Port12: BMC2.0 ,NA +//Port13: PORT4 Front Panel ,OC5# + + EFI_STATUS Status; + + Status = UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPeiPlatformUbaOcConfigDataGuid, + &TypeTucanaUsbOcUpdate, + sizeof(TypeTucanaUsbOcUpdate) + ); + + return Status; +} + + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/build_board.py b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/build_board.py new file mode 100644 index 0000000000..a54b12a4fd --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/build_board.py @@ -0,0 +1,197 @@ +# @ build_board.py +# Extensions for building Tucana using build_bios.py +# +# +# Copyright (c) 2021 - 2023, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2021, American Megatrends International LLC. <BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +""" +This module serves as a sample implementation of the build extension +scripts +""" + +import os +import sys + +def pre_build_ex(config, functions): + """Additional Pre BIOS build function + + :param config: The environment variables to be used in the build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: nothing + """ + print("pre_build_ex") + + config["BUILD_DIR_PATH"] = os.path.join(config["WORKSPACE"], + 'Build', + config["PLATFORM_BOARD_PACKAGE"], + "{}_{}".format( + config["TARGET"], + config["TOOL_CHAIN_TAG"])) + # set BUILD_DIR path + config["BUILD_DIR"] = os.path.join('Build', + config["PLATFORM_BOARD_PACKAGE"], + "{}_{}".format( + config["TARGET"], + config["TOOL_CHAIN_TAG"])) + config["BUILD_X64"] = os.path.join(config["BUILD_DIR_PATH"], 'X64') + config["BUILD_IA32"] = os.path.join(config["BUILD_DIR_PATH"], 'IA32') + + if not os.path.isdir(config["BUILD_DIR_PATH"]): + try: + os.makedirs(config["BUILD_DIR_PATH"]) + except OSError: + print("Error while creating Build folder") + sys.exit(1) + + #@todo: Replace this with PcdFspModeSelection + if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE": + config["EXT_BUILD_FLAGS"] += " -D FSP_MODE=0" + else: + config["EXT_BUILD_FLAGS"] += " -D FSP_MODE=1" + + if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE": + raise ValueError("FSP API Mode is currently unsupported on Ice Lake Xeon Scalable") + + # Build the ACPI AML offset table *.offset.h + print("Info: re-generating PlatformOffset header files") + + execute_script = functions.get("execute_script") + + # AML offset arch is X64, not sure if it matters. + command = ["build", "-a", "X64", "-t", config["TOOL_CHAIN_TAG"], "-D", "MAX_SOCKET=" + config["MAX_SOCKET"]] + + if config["EXT_BUILD_FLAGS"] and config["EXT_BUILD_FLAGS"] != "": + ext_build_flags = config["EXT_BUILD_FLAGS"].split(" ") + ext_build_flags = [x.strip() for x in ext_build_flags] + ext_build_flags = [x for x in ext_build_flags if x != ""] + command.extend(ext_build_flags) + + aml_offsets_split = os.path.split(os.path.normpath(config["AML_OFFSETS_PATH"])) + command.append("-p") + command.append(os.path.normpath(config["AML_OFFSETS_PATH"]) + '.dsc') + command.append("-m") + command.append(os.path.join(aml_offsets_split[0], aml_offsets_split[1], aml_offsets_split[1] + '.inf')) + command.append("-y") + command.append(os.path.join(config["WORKSPACE"], "PreBuildReport.txt")) + command.append("--log=" + os.path.join(config["WORKSPACE"], "PreBuild.log")) + + shell = True + if os.name == "posix": # linux + shell = False + + _, _, _, code = execute_script(command, config, shell=shell) + if code != 0: + print(" ".join(command)) + print("Error re-generating PlatformOffset header files") + sys.exit(1) + + # Build AmlGenOffset command to consume the *.offset.h and produce AmlOffsetTable.c for StaticSkuDataDxe use. + + # Get destination path and filename from config + relative_file_path = os.path.normpath(config["STRIPPED_AML_OFFSETS_FILE_PATH"]) # get path relative to Platform/Intel + out_file_path = os.path.join(config["WORKSPACE_PLATFORM"], relative_file_path) # full path to output file + out_file_dir = os.path.dirname(out_file_path) # remove filename + + out_file_root_ext = os.path.splitext(os.path.basename(out_file_path)) # root and extension of output file + + # Get relative path for the generated offset.h file + relative_dsdt_file_path = os.path.normpath(config["DSDT_TABLE_FILE_PATH"]) # path relative to Platform/Intel + dsdt_file_root_ext = os.path.splitext(os.path.basename(relative_dsdt_file_path)) # root and extension of generated offset.h file + + # Generate output directory if it doesn't exist + if not os.path.exists(out_file_dir): + os.mkdir(out_file_dir) + + command = [sys.executable, + os.path.join(config["MIN_PACKAGE_TOOLS"], "AmlGenOffset", "AmlGenOffset.py"), + "-d", "--aml_filter", config["AML_FILTER"], + "-o", out_file_path, + os.path.join(config["BUILD_X64"], aml_offsets_split[0], aml_offsets_split[1], aml_offsets_split[1], "OUTPUT", os.path.dirname(relative_dsdt_file_path), dsdt_file_root_ext[0] + ".offset.h")] + + # execute the command + _, _, _, code = execute_script(command, config, shell=shell) + if code != 0: + print(" ".join(command)) + print("Error re-generating PlatformOffset header files") + sys.exit(1) + + print("GenOffset done") + + + return None + +def _merge_files(files, ofile): + with open(ofile, 'wb') as of: + for x in files: + if not os.path.exists(x): + return + + with open(x, 'rb') as f: + of.write(f.read()) + +def build_ex(config, functions): + """Additional BIOS build function + + :param config: The environment variables to be used in the build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("build_ex") + fv_path = os.path.join(config["BUILD_DIR_PATH"], "FV") + binary_fd = os.path.join(fv_path, "BINARY.fd") + main_fd = os.path.join(fv_path, "MAIN.fd") + secpei_fd = os.path.join(fv_path, "SECPEI.fd") + board_fd = config["BOARD"].upper() + final_fd = os.path.join(fv_path, "{}.fd".format(board_fd)) + _merge_files((binary_fd, main_fd, secpei_fd), final_fd) + return None + + +def post_build_ex(config, functions): + """Additional Post BIOS build function + + :param config: The environment variables to be used in the post + build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("post_build_ex") + fv_path = os.path.join(config["BUILD_DIR_PATH"], "FV") + board_fd = config["BOARD"].upper() + final_fd = os.path.join(fv_path, "{}.fd".format(board_fd)) + final_ifwi = os.path.join(fv_path, "{}.bin".format(board_fd)) + + ifwi_ingredients_path = os.path.join(config["WORKSPACE_PLATFORM_BIN"], "Ifwi", config["BOARD"]) + flash_descriptor = os.path.join(ifwi_ingredients_path, "descriptor.bin") + intel_me = os.path.join(ifwi_ingredients_path, "me.bin") + ptt = os.path.join(ifwi_ingredients_path, "ptt.bin") + devexp1 = os.path.join(ifwi_ingredients_path, "devexp1.bin") + _merge_files((flash_descriptor, intel_me, ptt, devexp1, final_fd), final_ifwi) + if os.path.isfile(final_fd): + print("IFWI image can be found at {}".format(final_ifwi)) + return None + + +def clean_ex(config, functions): + """Additional clean function + + :param config: The environment variables to be used in the build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("clean_ex") + return None diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Tucana/build_config.cfg b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/build_config.cfg new file mode 100644 index 0000000000..21f5833663 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Tucana/build_config.cfg @@ -0,0 +1,52 @@ +# @ build_config.cfg +# This is the Tucana board specific build settings +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2021, American Megatrends International LLC. <BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + + +[CONFIG] +WORKSPACE_PLATFORM_BIN = edk2-non-osi/Platform/Intel/WhitleyOpenBoardBinPkg +EDK_SETUP_OPTION = +openssl_path = +PLATFORM_BOARD_PACKAGE = WhitleyOpenBoardPkg +PROJECT = WhitleyOpenBoardPkg/Tucana +BOARD = Tucana +FLASH_MAP_FDF = WhitleyOpenBoardPkg/FspFlashOffsets.fdf +PROJECT_DSC = WhitleyOpenBoardPkg/Tucana/PlatformPkg.dsc +BOARD_PKG_PCD_DSC = WhitleyOpenBoardPkg/PlatformPkgConfig.dsc +ADDITIONAL_SCRIPTS = WhitleyOpenBoardPkg/Tucana/build_board.py +PrepRELEASE = DEBUG +SILENT_MODE = FALSE +EXT_CONFIG_CLEAR = +CapsuleBuild = FALSE +EXT_BUILD_FLAGS = -D CPUTARGET=ICX -D RP_PKG=WhitleyOpenBoardPkg -D SILICON_PKG=WhitleySiliconPkg -D PCD_DYNAMIC_AS_DYNAMICEX -D MAX_CORE=64 -D MAX_THREAD=2 -D PLATFORM_PKG=MinPlatformPkg +MAX_SOCKET = 4 +CAPSULE_BUILD = 0 +TARGET = DEBUG +TARGET_SHORT = D +PERFORMANCE_BUILD = FALSE +FSP_WRAPPER_BUILD = TRUE +FSP_BIN_PKG = WhitleyFspBinPkg +FSP_PKG_NAME = WhitleyFspPkg +FSP_BINARY_BUILD = FALSE +FSP_TEST_RELEASE = FALSE +SECURE_BOOT_ENABLE = FALSE +BIOS_INFO_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807 + +# +# AML offset table generation configuration options +# All paths should use / and be relative to edk2-platforms/Platform/Intel +# +# AML_FILTER - AML filter is used to strip out unused AML offset data +# AML_OFFSETS_PATH - Path to INF file that builds AML offsets C source file +# The directory name, DSC file name, INF file name, and BASE_NAME must match identically +# DSDT_TABLE_FILE_PATH - Path to DSDT ASL file for the board +# STRIPPED_AML_OFFSETS_FILE_PATH - Target AML offset data file consumed by UBA driver +# +AML_FILTER = \"PSYS\" .\.DRVT\" .\.FIX[0-9,A-Z] BBI[0] BBU[0] CRCM BAR0 .\.CCT[0-9A-Z]\" .\.CFH[0-9A-Z]\" .\.FXCD\" .\.FXST\" .\.FXIN\" .\.FXOU\" .\.FXBS\" .\.FXFH\" .\.CENA\" .\.DRVT\" .\.CFIS\" {NULL }; +AML_OFFSETS_PATH = WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets +DSDT_TABLE_FILE_PATH = WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl +STRIPPED_AML_OFFSETS_FILE_PATH = WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AmlOffsetTable.c diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c index 18c05e2d01..37d9ad93ef 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c @@ -99,6 +99,16 @@ BoardInitDxeDriverEntry ( ASSERT_EFI_ERROR (Status); break; + case TypeTucana: + Status = gBS->InstallProtocolInterface ( + &Handle, + &gEfiPlatformTypeTucanaProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + break; + case TypeAowanda: Status = gBS->InstallProtocolInterface ( &Handle, diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf index ef47d1b1b8..8bff030ac0 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf @@ -64,6 +64,7 @@ gEfiPlatformTypeWilsonCitySMTProtocolGuid #PRODUCER gEfiPlatformTypeCooperCityRPProtocolGuid #PRODUCER gEfiPlatformTypeJunctionCityProtocolGuid #PRODUCER + gEfiPlatformTypeTucanaProtocolGuid #PRODUCER gEfiPlatformTypeAowandaProtocolGuid #PRODUCER [FixedPcd] diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf index ac663d9b43..a74ba7133a 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf +++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/StaticSkuDataDxe.inf @@ -59,4 +59,5 @@ gEfiPlatformTypeWilsonCitySMTProtocolGuid OR gEfiPlatformTypeWilsonCityRPProtocolGuid OR gEfiPlatformTypeJunctionCityProtocolGuid OR + gEfiPlatformTypeTucanaProtocolGuid OR gEfiPlatformTypeAowandaProtocolGuid diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg index a5c3262240..f8ae3fc6d5 100644 --- a/Platform/Intel/build.cfg +++ b/Platform/Intel/build.cfg @@ -70,5 +70,6 @@ CooperCityRvp = WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg WilsonCityRvp = WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg BoardTiogaPass = PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg JunctionCity = WhitleyOpenBoardPkg/JunctionCity/build_config.cfg +Tucana = WhitleyOpenBoardPkg/Tucana/build_config.cfg Aowanda = WhitleyOpenBoardPkg/Aowanda/build_config.cfg AlderlakePRvp = AlderlakeOpenBoardPkg/AlderlakePRvp/build_config.cfg diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py index ec0788956d..6c2d7448ab 100755 --- a/Platform/Intel/build_bios.py +++ b/Platform/Intel/build_bios.py @@ -1,1203 +1,1203 @@ #!/usr/bin/env python3 -#
-# @ build_bios.py
-# Builds BIOS using configuration files and dynamically
-# imported functions from board directory
-#
-# Copyright (c) 2019 - 2025, Intel Corporation. All rights reserved.<BR>
-# Copyright (c) 2021, American Megatrends International LLC.<BR>
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-
-"""
-This module builds BIOS using configuration files and dynamically
-imported functions from board directory
-"""
-
-
-import os
-import re
-import sys
-import glob
-import signal
-import shutil
-import argparse
-import traceback
-import subprocess
-from importlib import import_module
-
-try:
- # python 2.7
- import ConfigParser as configparser
-except ImportError:
- # python 3
- import configparser
-
-
-def pre_build(build_config, build_type="DEBUG", silent=False, toolchain=None, skip_tools=False):
- """Sets the environment variables that shall be used for the build
-
- :param build_config: The build configuration as defined in the JSON
- configuration files
- :type build_config: Dictionary
- :param build_type: The build target, DEBUG, RELEASE, RELEASE_PDB,
- TEST_RELEASE
- :type build_type: String
- :param silent: Enables build in silent mode
- :type silent: Boolean
- :param toolchain: Specifies the tool chain tag to use for the build
- :type toolchain: String
- :returns: The updated environment variables
- :rtype: Dictionary
- """
-
- # get current environment variables
- config = os.environ.copy()
-
- # patch the build config
- build_config = patch_config(build_config)
-
- # update the current config with the build config
- config.update(build_config)
-
- # make the config and build python 2.7 compatible
- config = py_27_fix(config)
-
- # Set WORKSPACE environment.
- config["WORKSPACE"] = os.path.abspath(os.path.join("..", "..", "..", ""))
- print("Set WORKSPACE as: {}".format(config["WORKSPACE"]))
-
- # Check whether Git has been installed and been added to system path.
- try:
- subprocess.Popen(["git", "--help"], stdout=subprocess.PIPE)
- except OSError:
- print("The 'git' command is not recognized.")
- print("Please make sure that Git is installed\
- and has been added to system path.")
- sys.exit(1)
-
- # Create the Conf directory under WORKSPACE
- if not os.path.isdir(os.path.join(config["WORKSPACE"], "Conf")):
- try:
- # create directory
- os.makedirs(os.path.join(config["WORKSPACE"], "Conf"))
- # copy files to it
- config_template_path = os.path.join(config["WORKSPACE"],
- config["BASE_TOOLS_PATH"],
- "Conf")
- config_path = os.path.join(config["WORKSPACE"], "Conf")
- shutil.copyfile(config_template_path +
- os.sep + "target.template",
- config_path + os.sep + "target.txt")
- shutil.copyfile(config_template_path +
- os.sep + "tools_def.template",
- config_path + os.sep + "tools_def.txt")
- shutil.copyfile(config_template_path +
- os.sep + "build_rule.template",
- config_path + os.sep + "build_rule.txt")
- except OSError:
- print("Error while creating Conf")
- sys.exit(1)
-
- # Set other environments.
- # Basic Rule:
- # Platform override Silicon override Core
- # Source override Binary
- config["WORKSPACE_PLATFORM"] = os.path.join(config["WORKSPACE"],
- config["WORKSPACE_PLATFORM"])
- config["WORKSPACE_SILICON"] = os.path.join(config["WORKSPACE"],
- config["WORKSPACE_SILICON"])
- config["WORKSPACE_FEATURES"] = os.path.join(config["WORKSPACE"],
- config["WORKSPACE_FEATURES"])
- config["WORKSPACE_FEATURES_INTEL"] = os.path.join(config["WORKSPACE"],
- config["WORKSPACE_FEATURES_INTEL"])
- config["WORKSPACE_DRIVERS"] = os.path.join(config["WORKSPACE"],
- config["WORKSPACE_DRIVERS"])
- config["WORKSPACE_PLATFORM_BIN"] = \
- os.path.join(config["WORKSPACE"], config["WORKSPACE_PLATFORM_BIN"])
- config["WORKSPACE_SILICON_BIN"] = \
- os.path.join(config["WORKSPACE"], config["WORKSPACE_SILICON_BIN"])
- config["WORKSPACE_FSP_BIN"] = os.path.join(config["WORKSPACE"],
- config["WORKSPACE_FSP_BIN"])
-
- # add to package path
- config["PACKAGES_PATH"] = config["WORKSPACE_PLATFORM"]
- config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_SILICON"]
- config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_SILICON_BIN"]
- config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_FEATURES"]
- config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_FEATURES_INTEL"]
- # add all feature domains in WORKSPACE_FEATURES_INTEL to package path
- for filename in os.listdir(config["WORKSPACE_FEATURES_INTEL"]):
- filepath = os.path.join(config["WORKSPACE_FEATURES_INTEL"], filename)
- # feature domains folder does not contain dec file
- if os.path.isdir(filepath) and \
- not glob.glob(os.path.join(filepath, "*.dec")):
- config["PACKAGES_PATH"] += os.pathsep + filepath
- config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_DRIVERS"]
- config["PACKAGES_PATH"] += os.pathsep + \
- os.path.join(config["WORKSPACE"], config["WORKSPACE_FSP_BIN"])
- config["PACKAGES_PATH"] += os.pathsep + \
- os.path.join(config["WORKSPACE"], config["WORKSPACE_CORE"])
- config["PACKAGES_PATH"] += os.pathsep + os.path.join(config["WORKSPACE"])
- config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_PLATFORM_BIN"]
- config["EDK_TOOLS_PATH"] = os.path.join(config["WORKSPACE"],
- config["EDK_TOOLS_PATH"])
- config["BASE_TOOLS_PATH"] = config["EDK_TOOLS_PATH"]
- config["EDK_TOOLS_BIN"] = os.path.join(config["WORKSPACE"],
- config["EDK_TOOLS_BIN"])
-
- #
- # Board may have different FSP binary between API and Dispatch modes.
- # In API mode if FSP_BIN_PKG_FOR_API_MODE is assigned, it should
- # override FSP_BIN_PKG.
- #
- if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
- if config.get("FSP_BIN_PKG_FOR_API_MODE") is not None:
- config['FSP_BIN_PKG'] = config['FSP_BIN_PKG_FOR_API_MODE']
-
- config["PLATFORM_FSP_BIN_PACKAGE"] = \
- os.path.join(config['WORKSPACE_FSP_BIN'], config['FSP_BIN_PKG'])
- config['PROJECT_DSC'] = os.path.join(config["WORKSPACE_PLATFORM"],
- config['PROJECT_DSC'])
- config['BOARD_PKG_PCD_DSC'] = os.path.join(config["WORKSPACE_PLATFORM"],
- config['BOARD_PKG_PCD_DSC'])
- config["CONF_PATH"] = os.path.join(config["WORKSPACE"], "Conf")
-
- # get the python path
- if os.environ.get("PYTHON_HOME") is None:
- if os.environ.get("PYTHONPATH") is not None:
- config["PYTHON_HOME"] = os.environ.get("PYTHONPATH")
- else:
- config["PYTHON_HOME"] = os.path.dirname(sys.executable)
- config["PYTHONPATH"] = config["PYTHON_HOME"]
-
- if config.get("PYTHON_HOME") is None or \
- not os.path.exists(config.get("PYTHON_HOME")):
- print("PYTHON_HOME environment variable is not found")
- sys.exit(1)
-
- # if python is installed, disable the binary base tools.
- # python is installed if this code is running :)
- if config.get("PYTHON_HOME") is not None:
- if config.get("EDK_TOOLS_BIN") is not None:
- del config["EDK_TOOLS_BIN"]
-
- if os.name == 'nt' and toolchain is not None and \
- toolchain.startswith ('CLANG') and 'BASETOOLS_MINGW_PATH' in config:
- config['BASETOOLS_MINGW_BUILD'] = 'TRUE'
- if config.get("EDK_SETUP_OPTION"):
- config["EDK_SETUP_OPTION"] = config["EDK_SETUP_OPTION"].strip() + " " + "Mingw-w64"
- else:
- config["EDK_SETUP_OPTION"] = "Mingw-w64"
- config["PATH"] = os.path.join(config["BASETOOLS_MINGW_PATH"],
- "bin") + os.pathsep + config["PATH"]
- del config["CLANG_BIN"]
- del config["CLANG_HOST_BIN"]
-
- # Run edk setup and update config
- if os.name == 'nt':
- edk2_setup_cmd = [os.path.join(config["EFI_SOURCE"], "edksetup"),
- "Rebuild"]
-
- if config.get("EDK_SETUP_OPTION") and \
- config["EDK_SETUP_OPTION"] != " ":
- edk2_setup_cmd.append(config["EDK_SETUP_OPTION"])
-
- _, _, result, return_code = execute_script(edk2_setup_cmd,
- config,
- collect_env=True,
- shell=True)
- if return_code == 0 and result is not None and isinstance(result,
- dict):
- config.update(result)
- else:
- # UNIX environment variable setup
- if os.environ.get("PYTHON_COMMAND") is not None:
- config["PYTHON_COMMAND"] = os.environ.get("PYTHON_COMMAND")
- else:
- config["PYTHON_COMMAND"] = sys.executable
-
- # Add BaseTools shell wrappers to the PATH
- config["PATH"] = os.path.join(config["BASE_TOOLS_PATH"],
- "BinPipWrappers", "PosixLike") + \
- os.pathsep + config["PATH"]
-
- # Make BaseTools source
- # and enable BaseTools source build
- shell = True
- command = ["nmake", "-f", os.path.join(config["BASE_TOOLS_PATH"],
- "Makefile")]
- if os.name == 'nt' and toolchain is not None and \
- toolchain.startswith ('CLANG') and 'BASETOOLS_MINGW_PATH' in config:
- command = ["mingw32-make", "-C", os.path.join(config["BASE_TOOLS_PATH"])]
- if os.name == "posix": # linux
- shell = False
- command = ["make", "-C", os.path.join(config["BASE_TOOLS_PATH"])]
-
- if not skip_tools:
- _, _, result, return_code = execute_script(command, config, shell=shell)
- if return_code != 0:
- #
- # If the BaseTools build fails, then run a clean build and retry
- #
- clean_command = ["nmake", "-f",
- os.path.join(config["BASE_TOOLS_PATH"], "Makefile"),
- "clean"]
- if os.name == 'nt' and toolchain is not None and \
- toolchain.startswith ('CLANG') and 'BASETOOLS_MINGW_PATH' in config:
- clean_command = ["mingw32-make", "-C",
- os.path.join(config["BASE_TOOLS_PATH"], "clean")]
- if os.name == "posix":
- clean_command = ["make", "-C",
- os.path.join(config["BASE_TOOLS_PATH"]), "clean"]
- _, _, result, return_code = execute_script(clean_command, config,
- shell=shell)
- if return_code != 0:
- build_failed(config)
- _, _, result, return_code = execute_script(command, config, shell=shell)
- if return_code != 0:
- build_failed(config)
-
- #
- # build platform silicon tools
- #
- # save the current workspace
- saved_work_directory = config["WORKSPACE"]
- # change the workspace to silicon tools directory
- config["WORKSPACE"] = os.path.join(config["WORKSPACE_SILICON"], "Tools")
-
- command = ["nmake"]
- if os.name == 'nt' and toolchain is not None and \
- toolchain.startswith ('CLANG') and 'BASETOOLS_MINGW_PATH' in config:
- command = ["mingw32-make"]
- if os.name == "posix": # linux
- command = ["make"]
- # add path to generated FitGen binary to
- # environment path variable
- config["PATH"] += os.pathsep + \
- os.path.join(config["BASE_TOOLS_PATH"],
- "Source", "C", "bin")
-
- # build the silicon tools
- _, _, result, return_code = execute_script(command, config, shell=shell)
- if return_code != 0:
- #
- # If the BaseTools build fails, then run a clean build and retry
- #
- clean_command = ["nmake", "clean"]
- if os.name == 'nt' and toolchain is not None and \
- toolchain.startswith ('CLANG') and 'BASETOOLS_MINGW_PATH' in config:
- clean_command = ["mingw32-make", "clean"]
- if os.name == "posix":
- clean_command = ["make", "clean"]
- _, _, result, return_code = execute_script(clean_command, config,
- shell=shell)
- if return_code != 0:
- build_failed(config)
- _, _, result, return_code = execute_script(command, config, shell=shell)
- if return_code != 0:
- build_failed(config)
-
- # restore WORKSPACE environment variable
- config["WORKSPACE"] = saved_work_directory
-
- config["SILENT_MODE"] = 'TRUE' if silent else 'FALSE'
-
- print("==============================================")
-
- if os.path.isfile(os.path.join(config['WORKSPACE'], "Prep.log")):
- os.remove(os.path.join(config['WORKSPACE'], "Prep.log"))
-
- config["PROJECT"] = os.path.join(config["PLATFORM_BOARD_PACKAGE"],
- config["BOARD"])
-
- # Setup Build
- # @todo: Need better TOOL_CHAIN_TAG detection
- if toolchain is not None:
- config["TOOL_CHAIN_TAG"] = toolchain
- elif config.get("TOOL_CHAIN_TAG") is None:
- if os.name == 'nt':
- config["TOOL_CHAIN_TAG"] = "VS2015"
- else:
- config["TOOL_CHAIN_TAG"] = "GCC5"
-
- # echo Show CL revision
- config["PrepRELEASE"] = build_type
-
- if build_type == "DEBUG":
- config["TARGET"] = 'DEBUG'
- config["TARGET_SHORT"] = 'D'
- else:
- config["TARGET"] = 'RELEASE'
- config["TARGET_SHORT"] = 'R'
-
- # set BUILD_DIR_PATH path
- config["BUILD_DIR_PATH"] = os.path.join(config["WORKSPACE"],
- 'Build',
- config["PROJECT"],
- "{}_{}".format(
- config["TARGET"],
- config["TOOL_CHAIN_TAG"]))
- # set BUILD_DIR path
- config["BUILD_DIR"] = os.path.join('Build',
- config["PROJECT"],
- "{}_{}".format(
- config["TARGET"],
- config["TOOL_CHAIN_TAG"]))
-
- config["BUILD_X64"] = os.path.join(config["BUILD_DIR_PATH"], 'X64')
- config["BUILD_IA32"] = os.path.join(config["BUILD_DIR_PATH"], 'IA32')
-
- if not os.path.isdir(config["BUILD_DIR_PATH"]):
- try:
- os.makedirs(config["BUILD_DIR_PATH"])
- except OSError:
- print("Error while creating Build folder")
- sys.exit(1)
-
- # Set FSP_WRAPPER_BUILD
- if config['FSP_WRAPPER_BUILD'] == "TRUE":
- # Create dummy Fsp_Rebased_S_padded.fd to build the BiosInfo.inf
- # if it is wrapper build, due to the SECTION inclusion
- open(os.path.join(config["WORKSPACE_FSP_BIN"],
- config["FSP_BIN_PKG"],
- "Fsp_Rebased_S_padded.fd"), 'w').close()
-
- if not os.path.isdir(config["BUILD_X64"]):
- try:
- os.mkdir(config["BUILD_X64"])
- except OSError:
- print("Error while creating {}".format(config["BUILD_X64"]))
- sys.exit(1)
-
- # update config file with changes
- update_target_file(config)
-
- # Additional pre build scripts for this platform
- result = pre_build_ex(config)
- if result is not None and isinstance(result, dict):
- config.update(result)
-
- # print user settings
- print("BIOS_SIZE_OPTION = {}".format(config["BIOS_SIZE_OPTION"]))
- print("EFI_SOURCE = {}".format(config["EFI_SOURCE"]))
- print("TARGET = {}".format(config["TARGET"]))
- print("TARGET_ARCH = {}".format("IA32 X64"))
- print("TOOL_CHAIN_TAG = {}".format(config["TOOL_CHAIN_TAG"]))
- print("WORKSPACE = {}".format(config["WORKSPACE"]))
- print("WORKSPACE_CORE = {}".format(config["WORKSPACE_CORE"]))
- print("EXT_BUILD_FLAGS = {}".format(config["EXT_BUILD_FLAGS"]))
-
- return config
-
-
-def build(config):
- """Builds the BIOS image
-
- :param config: The environment variables to be used
- in the build process
- :type config: Dictionary
- :returns: nothing
- """
-
- if config["FSP_WRAPPER_BUILD"] == "TRUE":
- pattern = "Fsp_Rebased.*\\.fd$"
- file_dir = os.path.join(config['WORKSPACE_FSP_BIN'],
- config['FSP_BIN_PKG'])
- for item in os.listdir(file_dir):
- if re.search(pattern, item):
- os.remove(os.path.join(file_dir, item))
-
- command = [sys.executable, os.path.join(config['WORKSPACE_PLATFORM'],
- config['PLATFORM_PACKAGE'],
- 'Tools', 'Fsp',
- 'RebaseFspBinBaseAddress.py'),
- os.path.join(config['WORKSPACE_PLATFORM'],
- config['FLASH_MAP_FDF']),
- os.path.join(config['WORKSPACE_FSP_BIN'],
- config['FSP_BIN_PKG']),
- "Fsp.fd",
- "0x0"]
-
- _, _, _, return_code = execute_script(command, config, shell=False)
-
- if return_code != 0:
- print("ERROR:RebaseFspBinBaseAddress failed")
- sys.exit(return_code)
-
- # create Fsp_Rebased.fd which is Fsp_Rebased_S.fd +
- # Fsp_Rebased_M + Fsp_Rebased_T
- with open(os.path.join(file_dir, "Fsp_Rebased_S.fd"), 'rb') as fsp_s, \
- open(os.path.join(file_dir,
- "Fsp_Rebased_M.fd"), 'rb') as fsp_m, \
- open(os.path.join(file_dir,
- "Fsp_Rebased_T.fd"), 'rb') as fsp_t:
-
- fsp_rebased = fsp_s.read() + fsp_m.read() + fsp_t.read()
- with open(os.path.join(file_dir,
- "Fsp_Rebased.fd"), 'wb') as new_fsp:
- new_fsp.write(fsp_rebased)
-
- if not os.path.isfile(os.path.join(file_dir, "Fsp_Rebased.fd")):
- print("!!! ERROR:failed to create fsp!!!")
- sys.exit(1)
-
- # Output the build variables the user has selected.
- print("==========================================")
- print(" User Selected build options:")
- print(" SILENT_MODE = ", config.get("SILENT_MODE"))
- print(" REBUILD_MODE = ", config.get("REBUILD_MODE"))
- print(" BUILD_ROM_ONLY = ", config.get("BUILD_ROM_ONLY"))
- print(" BINARY_CACHE_CMD_LINE = ", config.get("HASH"), config.get("BINARY_CACHE_CMD_LINE"))
- print("==========================================")
-
- command = ["build", "-n", config["NUMBER_OF_PROCESSORS"]]
-
- if config["REBUILD_MODE"] and config["REBUILD_MODE"] != "":
- command.append(config["REBUILD_MODE"])
-
- if config["EXT_BUILD_FLAGS"] and config["EXT_BUILD_FLAGS"] != "":
- ext_build_flags = config["EXT_BUILD_FLAGS"].split(" ")
- ext_build_flags = [x.strip() for x in ext_build_flags]
- ext_build_flags = [x for x in ext_build_flags if x != ""]
- command.extend(ext_build_flags)
-
- if config.get('BINARY_CACHE_CMD_LINE'):
- command.append(config['HASH'])
- command.append(config['BINARY_CACHE_CMD_LINE'])
-
- if config.get("SILENT_MODE", "FALSE") == "TRUE":
- command.append("--silent")
- command.append("--quiet")
-
- else:
- command.append("--log=" + config.get("BUILD_LOG", "Build.log"))
- command.append("--report-file=" +
- config.get("BUILD_REPORT", "BuildReport.log"))
-
- if config.get("VERBOSE", "FALSE") == "TRUE":
- command.append("--verbose")
-
- if config.get("VERY_VERBOSE", "FALSE") == "TRUE":
- command.append("--debug=1")
-
- if config.get("MAX_SOCKET") is not None:
- command.append("-D")
- command.append("MAX_SOCKET=" + config["MAX_SOCKET"])
-
- if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
- #Override PCD to enable API mode FSP wrapper.
- command.append("--pcd")
- command.append("gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection=1")
-
- if config.get("PERFORMANCE_BUILD", "FALSE") == "TRUE":
- command.append("--pcd")
- command.append("gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable=True")
-
- shell = True
- if os.name == "posix":
- shell = False
-
- _, _, _, exit_code = execute_script(command, config, shell=shell)
- if exit_code != 0:
- build_failed(config)
-
- # Additional build scripts for this platform
- result = build_ex(config)
- if result is not None and isinstance(result, dict):
- config.update(result)
-
- return config
-
-
-def post_build(config):
- """Post build process of BIOS image
-
- :param config: The environment variables to be used in the build process
- :type config: Dictionary
- :returns: nothing
- """
- print("Running post_build to complete the build process.")
- board_fd = config["BOARD"].upper()
- final_fd = os.path.join(config["BUILD_DIR_PATH"], "FV",
- "{}.fd".format(board_fd))
-
- if config["BIOS_INFO_GUID"]:
- # Generate the fit table
- print("Generating FIT ...")
- if os.path.isfile(final_fd):
- temp_fd = os.path.join(config["BUILD_DIR_PATH"], "FV",
- "{}_.fd".format(board_fd))
- shell = True
- command = ["FitGen", "-D",
- final_fd, temp_fd, "-NA",
- "-I", config["BIOS_INFO_GUID"]] #@todo: Need mechanism to add additional options to the FitGen command line
-
- if os.name == "posix": # linux
- shell = False
-
- _, _, result, return_code = execute_script(command, config, shell=shell)
- if return_code != 0:
- print("Error while generating fit")
- else:
- # copy output to final binary
- shutil.copyfile(temp_fd, final_fd)
- # remove temp file
- os.remove(temp_fd)
- else:
- print("{} does not exist".format(final_fd))
- # remove temp file
-
- # Additional build scripts for this platform
- result = post_build_ex(config)
- if result is not None and isinstance(result, dict):
- config.update(result)
-
- # cleanup
- pattern = "Fsp_Rebased.*\\.fd$"
- file_dir = os.path.join(config['WORKSPACE_FSP_BIN'],
- config['FSP_BIN_PKG'])
- for item in os.listdir(file_dir):
- if re.search(pattern, item):
- os.remove(os.path.join(file_dir, item))
-
- if config.get("DYNAMIC_BUILD_INIT_FILES") is not None:
- for item in config["DYNAMIC_BUILD_INIT_FILES"].split(","):
- try:
- os.remove(item) # remove __init__.py
- os.remove(item + "c") # remove __init__.pyc as well
- except OSError:
- pass
-
- print("Done")
- if os.path.isfile(final_fd):
- print("Fd file can be found at {}".format(final_fd))
-
-def build_failed(config):
- """Displays results when build fails
-
- :param config: The environment variables used in the build process
- :type config: Dictionary
- :returns: nothing
- """
- print(" The EDKII BIOS Build has failed!")
- # clean up
- if config.get("DYNAMIC_BUILD_INIT_FILES") is not None:
- for item in config["DYNAMIC_BUILD_INIT_FILES"].split(","):
- if os.path.isfile(item):
- try:
- os.remove(item) # remove __init__.py
- os.remove(item + "c") # remove __init__.pyc as well
- except OSError:
- pass
- sys.exit(1)
-
-
-def import_platform_lib(path, function):
- """Imports custom functions for the platforms being built
-
- :param path: the location of the custom build script to be executed
- :type path: String
- :param path: the function to be executed
- :type path: String
- :returns: nothing
- """
- if path.endswith(".py"):
- path = path[:-3]
- path = path.replace(os.sep, ".")
- module = import_module(path)
- lib = getattr(module, function)
- return lib
-
-
-def pre_build_ex(config):
- """ An extension of the pre_build process as defined platform
- specific pre_build setup script
-
- :param config: The environment variables used in the pre build process
- :type config: Dictionary
- :returns: config dictionary
- :rtype: Dictionary
- """
- if config.get("ADDITIONAL_SCRIPTS"):
- try:
- platform_function =\
- import_platform_lib(config["ADDITIONAL_SCRIPTS"],
- "pre_build_ex")
- functions = {"execute_script": execute_script}
- return platform_function(config, functions)
- except ImportError as error:
- print(config["ADDITIONAL_SCRIPTS"], str(error))
- build_failed(config)
- return None
-
-
-def build_ex(config):
- """ An extension of the build process as defined platform
- specific build setup script
-
- :param config: The environment variables used in the build process
- :type config: Dictionary
- :returns: config dictionary
- :rtype: Dictionary
- """
- if config.get("ADDITIONAL_SCRIPTS"):
- try:
- platform_function =\
- import_platform_lib(config["ADDITIONAL_SCRIPTS"],
- "build_ex")
- functions = {"execute_script": execute_script}
- return platform_function(config, functions)
- except ImportError as error:
- print("error", config["ADDITIONAL_SCRIPTS"], str(error))
- build_failed(config)
- return None
-
-
-def post_build_ex(config):
- """ An extension of the post build process as defined platform
- specific build setup script
-
- :param config: The environment variables used in the post build
- process
- :type config: Dictionary
- :returns: config dictionary
- :rtype: Dictionary
- """
- if config.get("ADDITIONAL_SCRIPTS"):
- try:
- platform_function =\
- import_platform_lib(config["ADDITIONAL_SCRIPTS"],
- "post_build_ex")
- functions = {"execute_script": execute_script}
- return platform_function(config, functions)
- except ImportError as error:
- print(config["ADDITIONAL_SCRIPTS"], str(error))
- build_failed(config)
- return None
-
-
-def clean_ex(config):
- """ An extension of the platform cleaning
-
- :param config: The environment variables used in the clean process
- :type config: Dictionary
- :returns: config dictionary
- :rtype: Dictionary
- """
- if config.get("ADDITIONAL_SCRIPTS"):
- try:
- platform_function =\
- import_platform_lib(config["ADDITIONAL_SCRIPTS"],
- "clean_ex")
- functions = {"execute_script": execute_script}
- return platform_function(config, functions)
- except ImportError as error:
- print(config["ADDITIONAL_SCRIPTS"], str(error))
- build_failed(config)
- return None
-
-
-def get_environment_variables(std_out_str, marker):
- """Gets the environment variables from a process
-
- :param std_out_str: The std_out pipe
- :type std_out_str: String
- :param marker: A begining and end mark of environment
- variables printed to std_out
- :type marker: String
- :returns: The environment variables read from the process' std_out pipe
- :rtype: Tuple
- """
- start_env_update = False
- environment_vars = {}
- out_put = ""
- for line in std_out_str.split("\n"):
- if start_env_update and len(line.split("=")) == 2:
- key, value = line.split("=")
- environment_vars[key] = value
- else:
- out_put += "\n" + line.replace(marker, "")
-
- if marker in line:
- if start_env_update:
- start_env_update = False
- else:
- start_env_update = True
- return (out_put, environment_vars)
-
-
-def execute_script(command, env_variables, collect_env=False,
- enable_std_pipe=False, shell=True):
- """launches a process that executes a script/shell command passed to it
-
- :param command: The command/script with its commandline
- arguments to be executed
- :type command: List:String
- :param env_variables: Environment variables passed to the process
- :type env_variables: String
- :param collect_env: Enables the collection of environment variables
- when process execution is done
- :type collect_env: Boolean
- :param enable_std_pipe: Enables process out to be piped to
- :type enable_std_pipe: String
- :returns: a tuple of std_out, stderr , environment variables,
- return code
- :rtype: Tuple: (std_out, stderr , enVar, return_code)
- """
-
- print("Calling " + " ".join(command))
-
- env_marker = '-----env-----'
- env = {}
- kwarg = {"env": env_variables,
- "universal_newlines": True,
- "shell": shell,
- "cwd": env_variables["WORKSPACE"]}
-
- if enable_std_pipe or collect_env:
- kwarg["stdout"] = subprocess.PIPE
- kwarg["stderr"] = subprocess.PIPE
-
- # collect environment variables
- if collect_env:
- # get the binary that prints environment variables based on os
- if os.name == 'nt':
- get_var_command = "set"
- else:
- get_var_command = "env"
- # modify the command to print the environment variables
- if isinstance(command, list):
- command += ["&&", "echo", env_marker, "&&",
- get_var_command, "&&", "echo", env_marker]
- else:
- command += " " + " ".join(["&&", "echo", env_marker,
- "&&", get_var_command,
- "&&", "echo", env_marker])
-
- # execute the command
- execute = subprocess.Popen(command, **kwarg)
- std_out, stderr = execute.communicate()
- code = execute.returncode
-
- # wait for process to be done
- execute.wait()
-
- # if collect environment variables
- if collect_env:
- # get the new environment variables
- std_out, env = get_environment_variables(std_out, env_marker)
- return (std_out, stderr, env, code)
-
-
-def patch_config(config):
- """ An extension of the platform cleaning
-
- :param config: The environment variables used in the build process
- :type config: Dictionary
- :returns: config dictionary
- :rtype: Dictionary
- """
- new_config = {}
- for key in config:
- new_config[str(key)] = str(config[key].replace("/", os.sep))
- return new_config
-
-
-def py_27_fix(config):
- """ Prepares build for python 2.7 => build
- :param config: The environment variables used in the build process
- :type config: Dictionary
- :returns: config dictionary
- :rtype: Dictionary
- """
- if not sys.version_info > (3, 0):
- path_list = []
- # create __init__.py in directories in this path
- if config.get("ADDITIONAL_SCRIPTS"):
- # get the directory
- path_to_directory =\
- os.path.dirname(config.get("ADDITIONAL_SCRIPTS"))
- path = ""
- for directories in path_to_directory.split(os.sep):
- path += directories + os.sep
- init_file = path + os.sep + "__init__.py"
- if not os.path.isfile(init_file):
- open(init_file, 'w').close()
- path_list.append(init_file)
- config["DYNAMIC_BUILD_INIT_FILES"] = ",".join(path_list)
-
- return config
-
-
-def clean(build_config, board=False):
- """Cleans the build workspace
-
- :param config: The environment variables used in the build process
- :type config: Dictionary
- :param board: This flag specifies specific board clean
- :type board: Bool
- :returns: nothing
- """
-
- # patch the config
- build_config = patch_config(build_config)
-
- # get current environment variables
- config = os.environ.copy()
-
- # update it with the build variables
- config.update(build_config)
-
- if config.get('WORKSPACE') is None or not config.get('WORKSPACE'):
- config["WORKSPACE"] =\
- os.path.abspath(os.path.join("..", "..", "..", ""))
-
- # build cleanall
- print("Cleaning directories...")
-
- if board:
- platform_pkg = config.get("PLATFORM_BOARD_PACKAGE", None)
- if platform_pkg is None or\
- not os.path.isdir(os.path.join(config['WORKSPACE'],
- "Build", platform_pkg)):
- print("Platform package not found")
- sys.exit(1)
- else:
- print("Removing " + os.path.join(config['WORKSPACE'],
- "Build", platform_pkg))
- shutil.rmtree(os.path.join(config['WORKSPACE'],
- "Build", platform_pkg))
-
- else:
- if os.path.isdir(os.path.join(config['WORKSPACE'], "Build")):
- print("Removing " + os.path.join(config['WORKSPACE'], "Build"))
- shutil.rmtree(os.path.join(config['WORKSPACE'], "Build"))
-
- if os.path.isdir(os.path.join(config['WORKSPACE'], "Conf")):
- print("Removing " + os.path.join(config['WORKSPACE'], "Conf"))
- shutil.rmtree(os.path.join(config['WORKSPACE'], "Conf"))
-
- print("Cleaning files...")
-
- if os.path.isfile(os.path.join(config['WORKSPACE'],
- config.get("BUILD_REPORT",
- "BuildReport.log"))):
- print("Removing ", os.path.join(config['WORKSPACE'],
- config.get("BUILD_REPORT",
- "BuildReport.log")))
- os.remove(os.path.join(config['WORKSPACE'],
- config.get("BUILD_REPORT", "BuildReport.log")))
-
- print(" All done...")
-
- sys.exit(0)
-
-
-def update_target_file(config):
- """Updates Conf's target file that will be used in the build
-
- :param config: The environment variables used in the build process
- :type config: Dictionary
- :returns: True if update was successful and False if update fails
- :rtype: Boolean
- """
- contents = None
- result = False
- with open(os.path.join(config["CONF_PATH"], "target.txt"), 'r') as target:
- contents = target.readlines()
- options_list = ['ACTIVE_PLATFORM', 'TARGET',
- 'TARGET_ARCH', 'TOOL_CHAIN_TAG', 'BUILD_RULE_CONF']
- modified = []
-
- # remove these options from the config file
- for line in contents:
- if line.replace(" ", "")[0] != '#' and\
- any(opt in line for opt in options_list):
- continue
- modified.append(line)
-
- # replace with config options provided
- string = "{} = {}\n".format("ACTIVE_PLATFORM",
- os.path.join(
- config['WORKSPACE_PLATFORM'],
- config['PLATFORM_BOARD_PACKAGE'],
- config['BOARD'],
- config['PROJECT_DSC']))
- modified.append(string)
-
- string = "{} = {}\n".format("TARGET", config['TARGET'])
- modified.append(string)
-
- string = "TARGET_ARCH = IA32 X64\n"
- modified.append(string)
-
- string = "{} = {}\n".format("TOOL_CHAIN_TAG", config['TOOL_CHAIN_TAG'])
- modified.append(string)
-
- string = "{} = {}\n".format("BUILD_RULE_CONF",
- os.path.join("Conf", "build_rule.txt"))
- modified.append(string)
-
- if modified is not None:
- with open(os.path.join(config["WORKSPACE"],
- "Conf", "target.txt"), 'w') as target:
- for line in modified:
- target.write(line)
- result = True
-
- return result
-
-
-def get_config():
- """Reads the default projects config file
-
- :returns: The config defined in the the Build.cfg file
- :rtype: Dictionary
- """
- path = 'build.cfg'
- if not os.path.isfile(path):
- path = os.path.dirname(__file__)
- path = os.path.join(path, 'build.cfg')
- if not os.path.isfile(path):
- raise IOError("Config file {} not found".format())
- config_file = configparser.RawConfigParser()
- config_file.optionxform = str
- config_file.read(path)
- config_dictionary = {}
- for section in config_file.sections():
- dictionary = dict(config_file.items(section))
- config_dictionary[section] = dictionary
- return config_dictionary
-
-
-def get_platform_config(platform_name, config_data):
- """ Reads the platform specific config file
-
- param platform_name: The name of the platform to be built
- :type platform_name: String
- param configData: The environment variables to be
- used in the build process
- :type configData: Dictionary
- :returns: The config defined in the the Build.cfg file
- :rtype: Dictionary
- """
- config = {}
-
- platform_data = config_data.get("PLATFORMS")
- path = platform_data.get(platform_name)
- if not os.path.isfile(path):
- path = os.path.dirname(__file__)
- path = os.path.join(path, platform_data.get(platform_name))
- if not os.path.isfile(path):
- raise IOError("Config file {} not found".format())
- config_file = configparser.RawConfigParser()
- config_file.optionxform = str
- config_file.read(path)
- for section in config_file.sections():
- config[section] = dict(config_file.items(section))
-
- return config
-
-
-def get_cmd_config_arguments(arguments):
- """Get commandline config arguments
-
- param arguments: The environment variables to be used in the build process
- :type arguments: argparse
- :returns: The config dictionary built from the commandline arguments
- :rtype: Dictionary
- """
- result = {}
- if arguments.capsule is True:
- result["CAPSULE_BUILD"] = "1"
-
- if arguments.performance is True:
- result["PERFORMANCE_BUILD"] = "TRUE"
-
- if arguments.verbose is not None and arguments.verbose > 0:
- result["VERBOSE"] = "TRUE"
-
- if arguments.verbose is not None and arguments.verbose > 1:
- result["VERY_VERBOSE"] = "TRUE"
-
- if arguments.fsp is True:
- result["FSP_WRAPPER_BUILD"] = "TRUE"
-
- if arguments.fspapi is True:
- result["API_MODE_FSP_WRAPPER_BUILD"] = "TRUE"
-
- if not arguments.UseHashCache:
- result['BINARY_CACHE_CMD_LINE'] = ''
- elif arguments.BinCacheDest:
- result['HASH'] = '--hash'
- result['BINARY_CACHE_CMD_LINE'] = '--binary-destination=%s' % arguments.BinCacheDest
- elif arguments.BinCacheSource:
- result['HASH'] = '--hash'
- result['BINARY_CACHE_CMD_LINE'] = '--binary-source=%s' % arguments.BinCacheSource
- else:
- result['BINARY_CACHE_CMD_LINE'] = ''
-
- return result
-
-
-def get_cmd_arguments(build_config):
- """ Get commandline inputs from user
-
- param config_data: The environment variables to be
- used in the build process
- :type config_data: Dictionary
- :returns: The commandline arguments input by the user
- :rtype: argparse object
- """
-
- class PrintPlatforms(argparse.Action):
- """ this is an argparse action that lists the available platforms
- """
- def __call__(self, parser, namespace, values, option_string=None):
- print("Platforms:")
- for key in build_config.get("PLATFORMS"):
- print(" " + key)
- setattr(namespace, self.dest, values)
- sys.exit(0)
-
- # get the build commands
- parser = argparse.ArgumentParser(description="Build Help")
- parser.add_argument('--platform', '-p', dest="platform",
- help='the platform to build',
- choices=build_config.get("PLATFORMS"),
- required=('-l' not in sys.argv and
- '--cleanall' not in sys.argv))
-
- parser.add_argument('--toolchain', '-t', dest="toolchain",
- help="using the Tool Chain Tagname to build \
- the platform,overriding \
- target.txt's TOOL_CHAIN_TAG definition")
-
- parser.add_argument("--DEBUG", '-d', help="debug flag",
- action='store_const', dest="target",
- const="DEBUG", default="DEBUG")
-
- parser.add_argument("--RELEASE", '-r', help="release flag",
- action='store_const',
- dest="target", const="RELEASE")
-
- parser.add_argument("--TEST_RELEASE", '-tr', help="test Release flag",
- action='store_const',
- dest="target", const="TEST_RELEASE")
-
- parser.add_argument("--RELEASE_PDB", '-rp', help="release flag",
- action='store_const', dest="target",
- const="RELEASE_PDB")
-
- parser.add_argument('--list', '-l', action=PrintPlatforms,
- help='lists available platforms', nargs=0)
-
- parser.add_argument('--skiptools', '-s', dest='skip_tools',
- help='skips rebuilding base tools', action='store_true')
-
- parser.add_argument('--cleanall', dest='clean_all',
- help='cleans all', action='store_true')
-
- parser.add_argument('--clean', dest='clean',
- help='cleans specific platform', action='store_true')
-
- parser.add_argument('--verbose', '-v', dest='verbose',
- help='Verbose build log output, specify -vv for very verbose.', action='count')
-
- parser.add_argument("--capsule", help="capsule build enabled",
- action='store_true', dest="capsule")
-
- parser.add_argument("--silent", help="silent build enabled",
- action='store_true', dest="silent")
-
- parser.add_argument("--performance", help="performance build enabled",
- action='store_true', dest="performance")
-
- parser.add_argument("--fsp", help="fsp wrapper build enabled",
- action='store_true', dest="fsp")
-
- parser.add_argument("--fspapi", help="API mode fsp wrapper build enabled",
- action='store_true', dest="fspapi")
-
- parser.add_argument("--hash", action="store_true", dest="UseHashCache", default=False,
- help="Enable hash-based caching during build process.")
-
- parser.add_argument("--binary-destination", help="Generate a cache of binary \
- files in the specified directory.",
- action='store', dest="BinCacheDest")
-
- parser.add_argument("--binary-source", help="Consume a cache of binary files \
- from the specified directory.",
- action='store', dest="BinCacheSource")
-
- return parser.parse_args()
-
-
-def keyboard_interruption(int_signal, int_frame):
- """ Catches a keyboard interruption handler
-
- param int_signal: The signal this handler is called with
- :type int_signal: Signal
- param int_frame: The signal this handler is called with
- :type int_frame: frame
- :rtype: nothing
- """
- print("Signal #: {} Frame: {}".format(int_signal, int_frame))
- print("Quiting...")
- sys.exit(0)
-
-
-def main():
- """ The main function of this module
- :rtype: nothing
- """
- # to quit the build
- signal.signal(signal.SIGINT, keyboard_interruption)
-
- # get general build configurations
- build_config = get_config()
-
- # get commandline parameters
- arguments = get_cmd_arguments(build_config)
-
- if arguments.clean_all:
- clean(build_config.get("DEFAULT_CONFIG"))
-
- # get platform specific config
- platform_config = get_platform_config(arguments.platform, build_config)
-
- # update general build config with platform specific config
- config = build_config.get("DEFAULT_CONFIG")
- config.update(platform_config.get("CONFIG"))
-
- # if user selected clean
- if arguments.clean:
- clean(config, board=True)
-
- # Override config with cmd arguments
- cmd_config_args = get_cmd_config_arguments(arguments)
- config.update(cmd_config_args)
-
- # get pre_build configurations
- config = pre_build(config,
- build_type=arguments.target,
- toolchain=arguments.toolchain,
- silent=arguments.silent,
- skip_tools=arguments.skip_tools)
-
- # build selected platform
- config = build(config)
-
- # post build
- post_build(config)
-
-
-if __name__ == "__main__":
- try:
- EXIT_CODE = 0
- main()
- except Exception as error:
- EXIT_CODE = 1
- traceback.print_exc()
- sys.exit(EXIT_CODE)
+# +# @ build_bios.py +# Builds BIOS using configuration files and dynamically +# imported functions from board directory +# +# Copyright (c) 2019 - 2025, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2021, American Megatrends International LLC.<BR> +# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +""" +This module builds BIOS using configuration files and dynamically +imported functions from board directory +""" + + +import os +import re +import sys +import glob +import signal +import shutil +import argparse +import traceback +import subprocess +from importlib import import_module + +try: + # python 2.7 + import ConfigParser as configparser +except ImportError: + # python 3 + import configparser + + +def pre_build(build_config, build_type="DEBUG", silent=False, toolchain=None, skip_tools=False): + """Sets the environment variables that shall be used for the build + + :param build_config: The build configuration as defined in the JSON + configuration files + :type build_config: Dictionary + :param build_type: The build target, DEBUG, RELEASE, RELEASE_PDB, + TEST_RELEASE + :type build_type: String + :param silent: Enables build in silent mode + :type silent: Boolean + :param toolchain: Specifies the tool chain tag to use for the build + :type toolchain: String + :returns: The updated environment variables + :rtype: Dictionary + """ + + # get current environment variables + config = os.environ.copy() + + # patch the build config + build_config = patch_config(build_config) + + # update the current config with the build config + config.update(build_config) + + # make the config and build python 2.7 compatible + config = py_27_fix(config) + + # Set WORKSPACE environment. + config["WORKSPACE"] = os.path.abspath(os.path.join("..", "..", "..", "")) + print("Set WORKSPACE as: {}".format(config["WORKSPACE"])) + + # Check whether Git has been installed and been added to system path. + try: + subprocess.Popen(["git", "--help"], stdout=subprocess.PIPE) + except OSError: + print("The 'git' command is not recognized.") + print("Please make sure that Git is installed\ + and has been added to system path.") + sys.exit(1) + + # Create the Conf directory under WORKSPACE + if not os.path.isdir(os.path.join(config["WORKSPACE"], "Conf")): + try: + # create directory + os.makedirs(os.path.join(config["WORKSPACE"], "Conf")) + # copy files to it + config_template_path = os.path.join(config["WORKSPACE"], + config["BASE_TOOLS_PATH"], + "Conf") + config_path = os.path.join(config["WORKSPACE"], "Conf") + shutil.copyfile(config_template_path + + os.sep + "target.template", + config_path + os.sep + "target.txt") + shutil.copyfile(config_template_path + + os.sep + "tools_def.template", + config_path + os.sep + "tools_def.txt") + shutil.copyfile(config_template_path + + os.sep + "build_rule.template", + config_path + os.sep + "build_rule.txt") + except OSError: + print("Error while creating Conf") + sys.exit(1) + + # Set other environments. + # Basic Rule: + # Platform override Silicon override Core + # Source override Binary + config["WORKSPACE_PLATFORM"] = os.path.join(config["WORKSPACE"], + config["WORKSPACE_PLATFORM"]) + config["WORKSPACE_SILICON"] = os.path.join(config["WORKSPACE"], + config["WORKSPACE_SILICON"]) + config["WORKSPACE_FEATURES"] = os.path.join(config["WORKSPACE"], + config["WORKSPACE_FEATURES"]) + config["WORKSPACE_FEATURES_INTEL"] = os.path.join(config["WORKSPACE"], + config["WORKSPACE_FEATURES_INTEL"]) + config["WORKSPACE_DRIVERS"] = os.path.join(config["WORKSPACE"], + config["WORKSPACE_DRIVERS"]) + config["WORKSPACE_PLATFORM_BIN"] = \ + os.path.join(config["WORKSPACE"], config["WORKSPACE_PLATFORM_BIN"]) + config["WORKSPACE_SILICON_BIN"] = \ + os.path.join(config["WORKSPACE"], config["WORKSPACE_SILICON_BIN"]) + config["WORKSPACE_FSP_BIN"] = os.path.join(config["WORKSPACE"], + config["WORKSPACE_FSP_BIN"]) + + # add to package path + config["PACKAGES_PATH"] = config["WORKSPACE_PLATFORM"] + config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_SILICON"] + config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_SILICON_BIN"] + config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_FEATURES"] + config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_FEATURES_INTEL"] + # add all feature domains in WORKSPACE_FEATURES_INTEL to package path + for filename in os.listdir(config["WORKSPACE_FEATURES_INTEL"]): + filepath = os.path.join(config["WORKSPACE_FEATURES_INTEL"], filename) + # feature domains folder does not contain dec file + if os.path.isdir(filepath) and \ + not glob.glob(os.path.join(filepath, "*.dec")): + config["PACKAGES_PATH"] += os.pathsep + filepath + config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_DRIVERS"] + config["PACKAGES_PATH"] += os.pathsep + \ + os.path.join(config["WORKSPACE"], config["WORKSPACE_FSP_BIN"]) + config["PACKAGES_PATH"] += os.pathsep + \ + os.path.join(config["WORKSPACE"], config["WORKSPACE_CORE"]) + config["PACKAGES_PATH"] += os.pathsep + os.path.join(config["WORKSPACE"]) + config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_PLATFORM_BIN"] + config["EDK_TOOLS_PATH"] = os.path.join(config["WORKSPACE"], + config["EDK_TOOLS_PATH"]) + config["BASE_TOOLS_PATH"] = config["EDK_TOOLS_PATH"] + config["EDK_TOOLS_BIN"] = os.path.join(config["WORKSPACE"], + config["EDK_TOOLS_BIN"]) + + # + # Board may have different FSP binary between API and Dispatch modes. + # In API mode if FSP_BIN_PKG_FOR_API_MODE is assigned, it should + # override FSP_BIN_PKG. + # + if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE": + if config.get("FSP_BIN_PKG_FOR_API_MODE") is not None: + config['FSP_BIN_PKG'] = config['FSP_BIN_PKG_FOR_API_MODE'] + + config["PLATFORM_FSP_BIN_PACKAGE"] = \ + os.path.join(config['WORKSPACE_FSP_BIN'], config['FSP_BIN_PKG']) + config['PROJECT_DSC'] = os.path.join(config["WORKSPACE_PLATFORM"], + config['PROJECT_DSC']) + config['BOARD_PKG_PCD_DSC'] = os.path.join(config["WORKSPACE_PLATFORM"], + config['BOARD_PKG_PCD_DSC']) + config["CONF_PATH"] = os.path.join(config["WORKSPACE"], "Conf") + + # get the python path + if os.environ.get("PYTHON_HOME") is None: + if os.environ.get("PYTHONPATH") is not None: + config["PYTHON_HOME"] = os.environ.get("PYTHONPATH") + else: + config["PYTHON_HOME"] = os.path.dirname(sys.executable) + config["PYTHONPATH"] = config["PYTHON_HOME"] + + if config.get("PYTHON_HOME") is None or \ + not os.path.exists(config.get("PYTHON_HOME")): + print("PYTHON_HOME environment variable is not found") + sys.exit(1) + + # if python is installed, disable the binary base tools. + # python is installed if this code is running :) + if config.get("PYTHON_HOME") is not None: + if config.get("EDK_TOOLS_BIN") is not None: + del config["EDK_TOOLS_BIN"] + + if os.name == 'nt' and toolchain is not None and \ + toolchain.startswith ('CLANG') and 'BASETOOLS_MINGW_PATH' in config: + config['BASETOOLS_MINGW_BUILD'] = 'TRUE' + if config.get("EDK_SETUP_OPTION"): + config["EDK_SETUP_OPTION"] = config["EDK_SETUP_OPTION"].strip() + " " + "Mingw-w64" + else: + config["EDK_SETUP_OPTION"] = "Mingw-w64" + config["PATH"] = os.path.join(config["BASETOOLS_MINGW_PATH"], + "bin") + os.pathsep + config["PATH"] + del config["CLANG_BIN"] + del config["CLANG_HOST_BIN"] + + # Run edk setup and update config + if os.name == 'nt': + edk2_setup_cmd = [os.path.join(config["EFI_SOURCE"], "edksetup"), + "Rebuild"] + + if config.get("EDK_SETUP_OPTION") and \ + config["EDK_SETUP_OPTION"] != " ": + edk2_setup_cmd.append(config["EDK_SETUP_OPTION"]) + + _, _, result, return_code = execute_script(edk2_setup_cmd, + config, + collect_env=True, + shell=True) + if return_code == 0 and result is not None and isinstance(result, + dict): + config.update(result) + else: + # UNIX environment variable setup + if os.environ.get("PYTHON_COMMAND") is not None: + config["PYTHON_COMMAND"] = os.environ.get("PYTHON_COMMAND") + else: + config["PYTHON_COMMAND"] = sys.executable + + # Add BaseTools shell wrappers to the PATH + config["PATH"] = os.path.join(config["BASE_TOOLS_PATH"], + "BinPipWrappers", "PosixLike") + \ + os.pathsep + config["PATH"] + + # Make BaseTools source + # and enable BaseTools source build + shell = True + command = ["nmake", "-f", os.path.join(config["BASE_TOOLS_PATH"], + "Makefile")] + if os.name == 'nt' and toolchain is not None and \ + toolchain.startswith ('CLANG') and 'BASETOOLS_MINGW_PATH' in config: + command = ["mingw32-make", "-C", os.path.join(config["BASE_TOOLS_PATH"])] + if os.name == "posix": # linux + shell = False + command = ["make", "-C", os.path.join(config["BASE_TOOLS_PATH"])] + + if not skip_tools: + _, _, result, return_code = execute_script(command, config, shell=shell) + if return_code != 0: + # + # If the BaseTools build fails, then run a clean build and retry + # + clean_command = ["nmake", "-f", + os.path.join(config["BASE_TOOLS_PATH"], "Makefile"), + "clean"] + if os.name == 'nt' and toolchain is not None and \ + toolchain.startswith ('CLANG') and 'BASETOOLS_MINGW_PATH' in config: + clean_command = ["mingw32-make", "-C", + os.path.join(config["BASE_TOOLS_PATH"], "clean")] + if os.name == "posix": + clean_command = ["make", "-C", + os.path.join(config["BASE_TOOLS_PATH"]), "clean"] + _, _, result, return_code = execute_script(clean_command, config, + shell=shell) + if return_code != 0: + build_failed(config) + _, _, result, return_code = execute_script(command, config, shell=shell) + if return_code != 0: + build_failed(config) + + # + # build platform silicon tools + # + # save the current workspace + saved_work_directory = config["WORKSPACE"] + # change the workspace to silicon tools directory + config["WORKSPACE"] = os.path.join(config["WORKSPACE_SILICON"], "Tools") + + command = ["nmake"] + if os.name == 'nt' and toolchain is not None and \ + toolchain.startswith ('CLANG') and 'BASETOOLS_MINGW_PATH' in config: + command = ["mingw32-make"] + if os.name == "posix": # linux + command = ["make"] + # add path to generated FitGen binary to + # environment path variable + config["PATH"] += os.pathsep + \ + os.path.join(config["BASE_TOOLS_PATH"], + "Source", "C", "bin") + + # build the silicon tools + _, _, result, return_code = execute_script(command, config, shell=shell) + if return_code != 0: + # + # If the BaseTools build fails, then run a clean build and retry + # + clean_command = ["nmake", "clean"] + if os.name == 'nt' and toolchain is not None and \ + toolchain.startswith ('CLANG') and 'BASETOOLS_MINGW_PATH' in config: + clean_command = ["mingw32-make", "clean"] + if os.name == "posix": + clean_command = ["make", "clean"] + _, _, result, return_code = execute_script(clean_command, config, + shell=shell) + if return_code != 0: + build_failed(config) + _, _, result, return_code = execute_script(command, config, shell=shell) + if return_code != 0: + build_failed(config) + + # restore WORKSPACE environment variable + config["WORKSPACE"] = saved_work_directory + + config["SILENT_MODE"] = 'TRUE' if silent else 'FALSE' + + print("==============================================") + + if os.path.isfile(os.path.join(config['WORKSPACE'], "Prep.log")): + os.remove(os.path.join(config['WORKSPACE'], "Prep.log")) + + config["PROJECT"] = os.path.join(config["PLATFORM_BOARD_PACKAGE"], + config["BOARD"]) + + # Setup Build + # @todo: Need better TOOL_CHAIN_TAG detection + if toolchain is not None: + config["TOOL_CHAIN_TAG"] = toolchain + elif config.get("TOOL_CHAIN_TAG") is None: + if os.name == 'nt': + config["TOOL_CHAIN_TAG"] = "VS2015" + else: + config["TOOL_CHAIN_TAG"] = "GCC5" + + # echo Show CL revision + config["PrepRELEASE"] = build_type + + if build_type == "DEBUG": + config["TARGET"] = 'DEBUG' + config["TARGET_SHORT"] = 'D' + else: + config["TARGET"] = 'RELEASE' + config["TARGET_SHORT"] = 'R' + + # set BUILD_DIR_PATH path + config["BUILD_DIR_PATH"] = os.path.join(config["WORKSPACE"], + 'Build', + config["PROJECT"], + "{}_{}".format( + config["TARGET"], + config["TOOL_CHAIN_TAG"])) + # set BUILD_DIR path + config["BUILD_DIR"] = os.path.join('Build', + config["PROJECT"], + "{}_{}".format( + config["TARGET"], + config["TOOL_CHAIN_TAG"])) + + config["BUILD_X64"] = os.path.join(config["BUILD_DIR_PATH"], 'X64') + config["BUILD_IA32"] = os.path.join(config["BUILD_DIR_PATH"], 'IA32') + + if not os.path.isdir(config["BUILD_DIR_PATH"]): + try: + os.makedirs(config["BUILD_DIR_PATH"]) + except OSError: + print("Error while creating Build folder") + sys.exit(1) + + # Set FSP_WRAPPER_BUILD + if config['FSP_WRAPPER_BUILD'] == "TRUE": + # Create dummy Fsp_Rebased_S_padded.fd to build the BiosInfo.inf + # if it is wrapper build, due to the SECTION inclusion + open(os.path.join(config["WORKSPACE_FSP_BIN"], + config["FSP_BIN_PKG"], + "Fsp_Rebased_S_padded.fd"), 'w').close() + + if not os.path.isdir(config["BUILD_X64"]): + try: + os.mkdir(config["BUILD_X64"]) + except OSError: + print("Error while creating {}".format(config["BUILD_X64"])) + sys.exit(1) + + # update config file with changes + update_target_file(config) + + # Additional pre build scripts for this platform + result = pre_build_ex(config) + if result is not None and isinstance(result, dict): + config.update(result) + + # print user settings + print("BIOS_SIZE_OPTION = {}".format(config["BIOS_SIZE_OPTION"])) + print("EFI_SOURCE = {}".format(config["EFI_SOURCE"])) + print("TARGET = {}".format(config["TARGET"])) + print("TARGET_ARCH = {}".format("IA32 X64")) + print("TOOL_CHAIN_TAG = {}".format(config["TOOL_CHAIN_TAG"])) + print("WORKSPACE = {}".format(config["WORKSPACE"])) + print("WORKSPACE_CORE = {}".format(config["WORKSPACE_CORE"])) + print("EXT_BUILD_FLAGS = {}".format(config["EXT_BUILD_FLAGS"])) + + return config + + +def build(config): + """Builds the BIOS image + + :param config: The environment variables to be used + in the build process + :type config: Dictionary + :returns: nothing + """ + + if config["FSP_WRAPPER_BUILD"] == "TRUE": + pattern = "Fsp_Rebased.*\\.fd$" + file_dir = os.path.join(config['WORKSPACE_FSP_BIN'], + config['FSP_BIN_PKG']) + for item in os.listdir(file_dir): + if re.search(pattern, item): + os.remove(os.path.join(file_dir, item)) + + command = [sys.executable, os.path.join(config['WORKSPACE_PLATFORM'], + config['PLATFORM_PACKAGE'], + 'Tools', 'Fsp', + 'RebaseFspBinBaseAddress.py'), + os.path.join(config['WORKSPACE_PLATFORM'], + config['FLASH_MAP_FDF']), + os.path.join(config['WORKSPACE_FSP_BIN'], + config['FSP_BIN_PKG']), + "Fsp.fd", + "0x0"] + + _, _, _, return_code = execute_script(command, config, shell=False) + + if return_code != 0: + print("ERROR:RebaseFspBinBaseAddress failed") + sys.exit(return_code) + + # create Fsp_Rebased.fd which is Fsp_Rebased_S.fd + + # Fsp_Rebased_M + Fsp_Rebased_T + with open(os.path.join(file_dir, "Fsp_Rebased_S.fd"), 'rb') as fsp_s, \ + open(os.path.join(file_dir, + "Fsp_Rebased_M.fd"), 'rb') as fsp_m, \ + open(os.path.join(file_dir, + "Fsp_Rebased_T.fd"), 'rb') as fsp_t: + + fsp_rebased = fsp_s.read() + fsp_m.read() + fsp_t.read() + with open(os.path.join(file_dir, + "Fsp_Rebased.fd"), 'wb') as new_fsp: + new_fsp.write(fsp_rebased) + + if not os.path.isfile(os.path.join(file_dir, "Fsp_Rebased.fd")): + print("!!! ERROR:failed to create fsp!!!") + sys.exit(1) + + # Output the build variables the user has selected. + print("==========================================") + print(" User Selected build options:") + print(" SILENT_MODE = ", config.get("SILENT_MODE")) + print(" REBUILD_MODE = ", config.get("REBUILD_MODE")) + print(" BUILD_ROM_ONLY = ", config.get("BUILD_ROM_ONLY")) + print(" BINARY_CACHE_CMD_LINE = ", config.get("HASH"), config.get("BINARY_CACHE_CMD_LINE")) + print("==========================================") + + command = ["build", "-n", config["NUMBER_OF_PROCESSORS"]] + + if config["REBUILD_MODE"] and config["REBUILD_MODE"] != "": + command.append(config["REBUILD_MODE"]) + + if config["EXT_BUILD_FLAGS"] and config["EXT_BUILD_FLAGS"] != "": + ext_build_flags = config["EXT_BUILD_FLAGS"].split(" ") + ext_build_flags = [x.strip() for x in ext_build_flags] + ext_build_flags = [x for x in ext_build_flags if x != ""] + command.extend(ext_build_flags) + + if config.get('BINARY_CACHE_CMD_LINE'): + command.append(config['HASH']) + command.append(config['BINARY_CACHE_CMD_LINE']) + + if config.get("SILENT_MODE", "FALSE") == "TRUE": + command.append("--silent") + command.append("--quiet") + + else: + command.append("--log=" + config.get("BUILD_LOG", "Build.log")) + command.append("--report-file=" + + config.get("BUILD_REPORT", "BuildReport.log")) + + if config.get("VERBOSE", "FALSE") == "TRUE": + command.append("--verbose") + + if config.get("VERY_VERBOSE", "FALSE") == "TRUE": + command.append("--debug=1") + + if config.get("MAX_SOCKET") is not None: + command.append("-D") + command.append("MAX_SOCKET=" + config["MAX_SOCKET"]) + + if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE": + #Override PCD to enable API mode FSP wrapper. + command.append("--pcd") + command.append("gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection=1") + + if config.get("PERFORMANCE_BUILD", "FALSE") == "TRUE": + command.append("--pcd") + command.append("gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable=True") + + shell = True + if os.name == "posix": + shell = False + + _, _, _, exit_code = execute_script(command, config, shell=shell) + if exit_code != 0: + build_failed(config) + + # Additional build scripts for this platform + result = build_ex(config) + if result is not None and isinstance(result, dict): + config.update(result) + + return config + + +def post_build(config): + """Post build process of BIOS image + + :param config: The environment variables to be used in the build process + :type config: Dictionary + :returns: nothing + """ + print("Running post_build to complete the build process.") + board_fd = config["BOARD"].upper() + final_fd = os.path.join(config["BUILD_DIR_PATH"], "FV", + "{}.fd".format(board_fd)) + + if config["BIOS_INFO_GUID"]: + # Generate the fit table + print("Generating FIT ...") + if os.path.isfile(final_fd): + temp_fd = os.path.join(config["BUILD_DIR_PATH"], "FV", + "{}_.fd".format(board_fd)) + shell = True + command = ["FitGen", "-D", + final_fd, temp_fd, "-NA", + "-I", config["BIOS_INFO_GUID"]] #@todo: Need mechanism to add additional options to the FitGen command line + + if os.name == "posix": # linux + shell = False + + _, _, result, return_code = execute_script(command, config, shell=shell) + if return_code != 0: + print("Error while generating fit") + else: + # copy output to final binary + shutil.copyfile(temp_fd, final_fd) + # remove temp file + os.remove(temp_fd) + else: + print("{} does not exist".format(final_fd)) + # remove temp file + + # Additional build scripts for this platform + result = post_build_ex(config) + if result is not None and isinstance(result, dict): + config.update(result) + + # cleanup + pattern = "Fsp_Rebased.*\\.fd$" + file_dir = os.path.join(config['WORKSPACE_FSP_BIN'], + config['FSP_BIN_PKG']) + for item in os.listdir(file_dir): + if re.search(pattern, item): + os.remove(os.path.join(file_dir, item)) + + if config.get("DYNAMIC_BUILD_INIT_FILES") is not None: + for item in config["DYNAMIC_BUILD_INIT_FILES"].split(","): + try: + os.remove(item) # remove __init__.py + os.remove(item + "c") # remove __init__.pyc as well + except OSError: + pass + + print("Done") + if os.path.isfile(final_fd): + print("Fd file can be found at {}".format(final_fd)) + +def build_failed(config): + """Displays results when build fails + + :param config: The environment variables used in the build process + :type config: Dictionary + :returns: nothing + """ + print(" The EDKII BIOS Build has failed!") + # clean up + if config.get("DYNAMIC_BUILD_INIT_FILES") is not None: + for item in config["DYNAMIC_BUILD_INIT_FILES"].split(","): + if os.path.isfile(item): + try: + os.remove(item) # remove __init__.py + os.remove(item + "c") # remove __init__.pyc as well + except OSError: + pass + sys.exit(1) + + +def import_platform_lib(path, function): + """Imports custom functions for the platforms being built + + :param path: the location of the custom build script to be executed + :type path: String + :param path: the function to be executed + :type path: String + :returns: nothing + """ + if path.endswith(".py"): + path = path[:-3] + path = path.replace(os.sep, ".") + module = import_module(path) + lib = getattr(module, function) + return lib + + +def pre_build_ex(config): + """ An extension of the pre_build process as defined platform + specific pre_build setup script + + :param config: The environment variables used in the pre build process + :type config: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + if config.get("ADDITIONAL_SCRIPTS"): + try: + platform_function =\ + import_platform_lib(config["ADDITIONAL_SCRIPTS"], + "pre_build_ex") + functions = {"execute_script": execute_script} + return platform_function(config, functions) + except ImportError as error: + print(config["ADDITIONAL_SCRIPTS"], str(error)) + build_failed(config) + return None + + +def build_ex(config): + """ An extension of the build process as defined platform + specific build setup script + + :param config: The environment variables used in the build process + :type config: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + if config.get("ADDITIONAL_SCRIPTS"): + try: + platform_function =\ + import_platform_lib(config["ADDITIONAL_SCRIPTS"], + "build_ex") + functions = {"execute_script": execute_script} + return platform_function(config, functions) + except ImportError as error: + print("error", config["ADDITIONAL_SCRIPTS"], str(error)) + build_failed(config) + return None + + +def post_build_ex(config): + """ An extension of the post build process as defined platform + specific build setup script + + :param config: The environment variables used in the post build + process + :type config: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + if config.get("ADDITIONAL_SCRIPTS"): + try: + platform_function =\ + import_platform_lib(config["ADDITIONAL_SCRIPTS"], + "post_build_ex") + functions = {"execute_script": execute_script} + return platform_function(config, functions) + except ImportError as error: + print(config["ADDITIONAL_SCRIPTS"], str(error)) + build_failed(config) + return None + + +def clean_ex(config): + """ An extension of the platform cleaning + + :param config: The environment variables used in the clean process + :type config: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + if config.get("ADDITIONAL_SCRIPTS"): + try: + platform_function =\ + import_platform_lib(config["ADDITIONAL_SCRIPTS"], + "clean_ex") + functions = {"execute_script": execute_script} + return platform_function(config, functions) + except ImportError as error: + print(config["ADDITIONAL_SCRIPTS"], str(error)) + build_failed(config) + return None + + +def get_environment_variables(std_out_str, marker): + """Gets the environment variables from a process + + :param std_out_str: The std_out pipe + :type std_out_str: String + :param marker: A begining and end mark of environment + variables printed to std_out + :type marker: String + :returns: The environment variables read from the process' std_out pipe + :rtype: Tuple + """ + start_env_update = False + environment_vars = {} + out_put = "" + for line in std_out_str.split("\n"): + if start_env_update and len(line.split("=")) == 2: + key, value = line.split("=") + environment_vars[key] = value + else: + out_put += "\n" + line.replace(marker, "") + + if marker in line: + if start_env_update: + start_env_update = False + else: + start_env_update = True + return (out_put, environment_vars) + + +def execute_script(command, env_variables, collect_env=False, + enable_std_pipe=False, shell=True): + """launches a process that executes a script/shell command passed to it + + :param command: The command/script with its commandline + arguments to be executed + :type command: List:String + :param env_variables: Environment variables passed to the process + :type env_variables: String + :param collect_env: Enables the collection of environment variables + when process execution is done + :type collect_env: Boolean + :param enable_std_pipe: Enables process out to be piped to + :type enable_std_pipe: String + :returns: a tuple of std_out, stderr , environment variables, + return code + :rtype: Tuple: (std_out, stderr , enVar, return_code) + """ + + print("Calling " + " ".join(command)) + + env_marker = '-----env-----' + env = {} + kwarg = {"env": env_variables, + "universal_newlines": True, + "shell": shell, + "cwd": env_variables["WORKSPACE"]} + + if enable_std_pipe or collect_env: + kwarg["stdout"] = subprocess.PIPE + kwarg["stderr"] = subprocess.PIPE + + # collect environment variables + if collect_env: + # get the binary that prints environment variables based on os + if os.name == 'nt': + get_var_command = "set" + else: + get_var_command = "env" + # modify the command to print the environment variables + if isinstance(command, list): + command += ["&&", "echo", env_marker, "&&", + get_var_command, "&&", "echo", env_marker] + else: + command += " " + " ".join(["&&", "echo", env_marker, + "&&", get_var_command, + "&&", "echo", env_marker]) + + # execute the command + execute = subprocess.Popen(command, **kwarg) + std_out, stderr = execute.communicate() + code = execute.returncode + + # wait for process to be done + execute.wait() + + # if collect environment variables + if collect_env: + # get the new environment variables + std_out, env = get_environment_variables(std_out, env_marker) + return (std_out, stderr, env, code) + + +def patch_config(config): + """ An extension of the platform cleaning + + :param config: The environment variables used in the build process + :type config: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + new_config = {} + for key in config: + new_config[str(key)] = str(config[key].replace("/", os.sep)) + return new_config + + +def py_27_fix(config): + """ Prepares build for python 2.7 => build + :param config: The environment variables used in the build process + :type config: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + if not sys.version_info > (3, 0): + path_list = [] + # create __init__.py in directories in this path + if config.get("ADDITIONAL_SCRIPTS"): + # get the directory + path_to_directory =\ + os.path.dirname(config.get("ADDITIONAL_SCRIPTS")) + path = "" + for directories in path_to_directory.split(os.sep): + path += directories + os.sep + init_file = path + os.sep + "__init__.py" + if not os.path.isfile(init_file): + open(init_file, 'w').close() + path_list.append(init_file) + config["DYNAMIC_BUILD_INIT_FILES"] = ",".join(path_list) + + return config + + +def clean(build_config, board=False): + """Cleans the build workspace + + :param config: The environment variables used in the build process + :type config: Dictionary + :param board: This flag specifies specific board clean + :type board: Bool + :returns: nothing + """ + + # patch the config + build_config = patch_config(build_config) + + # get current environment variables + config = os.environ.copy() + + # update it with the build variables + config.update(build_config) + + if config.get('WORKSPACE') is None or not config.get('WORKSPACE'): + config["WORKSPACE"] =\ + os.path.abspath(os.path.join("..", "..", "..", "")) + + # build cleanall + print("Cleaning directories...") + + if board: + platform_pkg = config.get("PLATFORM_BOARD_PACKAGE", None) + if platform_pkg is None or\ + not os.path.isdir(os.path.join(config['WORKSPACE'], + "Build", platform_pkg)): + print("Platform package not found") + sys.exit(1) + else: + print("Removing " + os.path.join(config['WORKSPACE'], + "Build", platform_pkg)) + shutil.rmtree(os.path.join(config['WORKSPACE'], + "Build", platform_pkg)) + + else: + if os.path.isdir(os.path.join(config['WORKSPACE'], "Build")): + print("Removing " + os.path.join(config['WORKSPACE'], "Build")) + shutil.rmtree(os.path.join(config['WORKSPACE'], "Build")) + + if os.path.isdir(os.path.join(config['WORKSPACE'], "Conf")): + print("Removing " + os.path.join(config['WORKSPACE'], "Conf")) + shutil.rmtree(os.path.join(config['WORKSPACE'], "Conf")) + + print("Cleaning files...") + + if os.path.isfile(os.path.join(config['WORKSPACE'], + config.get("BUILD_REPORT", + "BuildReport.log"))): + print("Removing ", os.path.join(config['WORKSPACE'], + config.get("BUILD_REPORT", + "BuildReport.log"))) + os.remove(os.path.join(config['WORKSPACE'], + config.get("BUILD_REPORT", "BuildReport.log"))) + + print(" All done...") + + sys.exit(0) + + +def update_target_file(config): + """Updates Conf's target file that will be used in the build + + :param config: The environment variables used in the build process + :type config: Dictionary + :returns: True if update was successful and False if update fails + :rtype: Boolean + """ + contents = None + result = False + with open(os.path.join(config["CONF_PATH"], "target.txt"), 'r') as target: + contents = target.readlines() + options_list = ['ACTIVE_PLATFORM', 'TARGET', + 'TARGET_ARCH', 'TOOL_CHAIN_TAG', 'BUILD_RULE_CONF'] + modified = [] + + # remove these options from the config file + for line in contents: + if line.replace(" ", "")[0] != '#' and\ + any(opt in line for opt in options_list): + continue + modified.append(line) + + # replace with config options provided + string = "{} = {}\n".format("ACTIVE_PLATFORM", + os.path.join( + config['WORKSPACE_PLATFORM'], + config['PLATFORM_BOARD_PACKAGE'], + config['BOARD'], + config['PROJECT_DSC'])) + modified.append(string) + + string = "{} = {}\n".format("TARGET", config['TARGET']) + modified.append(string) + + string = "TARGET_ARCH = IA32 X64\n" + modified.append(string) + + string = "{} = {}\n".format("TOOL_CHAIN_TAG", config['TOOL_CHAIN_TAG']) + modified.append(string) + + string = "{} = {}\n".format("BUILD_RULE_CONF", + os.path.join("Conf", "build_rule.txt")) + modified.append(string) + + if modified is not None: + with open(os.path.join(config["WORKSPACE"], + "Conf", "target.txt"), 'w') as target: + for line in modified: + target.write(line) + result = True + + return result + + +def get_config(): + """Reads the default projects config file + + :returns: The config defined in the the Build.cfg file + :rtype: Dictionary + """ + path = 'build.cfg' + if not os.path.isfile(path): + path = os.path.dirname(__file__) + path = os.path.join(path, 'build.cfg') + if not os.path.isfile(path): + raise IOError("Config file {} not found".format()) + config_file = configparser.RawConfigParser() + config_file.optionxform = str + config_file.read(path) + config_dictionary = {} + for section in config_file.sections(): + dictionary = dict(config_file.items(section)) + config_dictionary[section] = dictionary + return config_dictionary + + +def get_platform_config(platform_name, config_data): + """ Reads the platform specific config file + + param platform_name: The name of the platform to be built + :type platform_name: String + param configData: The environment variables to be + used in the build process + :type configData: Dictionary + :returns: The config defined in the the Build.cfg file + :rtype: Dictionary + """ + config = {} + + platform_data = config_data.get("PLATFORMS") + path = platform_data.get(platform_name) + if not os.path.isfile(path): + path = os.path.dirname(__file__) + path = os.path.join(path, platform_data.get(platform_name)) + if not os.path.isfile(path): + raise IOError("Config file {} not found".format()) + config_file = configparser.RawConfigParser() + config_file.optionxform = str + config_file.read(path) + for section in config_file.sections(): + config[section] = dict(config_file.items(section)) + + return config + + +def get_cmd_config_arguments(arguments): + """Get commandline config arguments + + param arguments: The environment variables to be used in the build process + :type arguments: argparse + :returns: The config dictionary built from the commandline arguments + :rtype: Dictionary + """ + result = {} + if arguments.capsule is True: + result["CAPSULE_BUILD"] = "1" + + if arguments.performance is True: + result["PERFORMANCE_BUILD"] = "TRUE" + + if arguments.verbose is not None and arguments.verbose > 0: + result["VERBOSE"] = "TRUE" + + if arguments.verbose is not None and arguments.verbose > 1: + result["VERY_VERBOSE"] = "TRUE" + + if arguments.fsp is True: + result["FSP_WRAPPER_BUILD"] = "TRUE" + + if arguments.fspapi is True: + result["API_MODE_FSP_WRAPPER_BUILD"] = "TRUE" + + if not arguments.UseHashCache: + result['BINARY_CACHE_CMD_LINE'] = '' + elif arguments.BinCacheDest: + result['HASH'] = '--hash' + result['BINARY_CACHE_CMD_LINE'] = '--binary-destination=%s' % arguments.BinCacheDest + elif arguments.BinCacheSource: + result['HASH'] = '--hash' + result['BINARY_CACHE_CMD_LINE'] = '--binary-source=%s' % arguments.BinCacheSource + else: + result['BINARY_CACHE_CMD_LINE'] = '' + + return result + + +def get_cmd_arguments(build_config): + """ Get commandline inputs from user + + param config_data: The environment variables to be + used in the build process + :type config_data: Dictionary + :returns: The commandline arguments input by the user + :rtype: argparse object + """ + + class PrintPlatforms(argparse.Action): + """ this is an argparse action that lists the available platforms + """ + def __call__(self, parser, namespace, values, option_string=None): + print("Platforms:") + for key in build_config.get("PLATFORMS"): + print(" " + key) + setattr(namespace, self.dest, values) + sys.exit(0) + + # get the build commands + parser = argparse.ArgumentParser(description="Build Help") + parser.add_argument('--platform', '-p', dest="platform", + help='the platform to build', + choices=build_config.get("PLATFORMS"), + required=('-l' not in sys.argv and + '--cleanall' not in sys.argv)) + + parser.add_argument('--toolchain', '-t', dest="toolchain", + help="using the Tool Chain Tagname to build \ + the platform,overriding \ + target.txt's TOOL_CHAIN_TAG definition") + + parser.add_argument("--DEBUG", '-d', help="debug flag", + action='store_const', dest="target", + const="DEBUG", default="DEBUG") + + parser.add_argument("--RELEASE", '-r', help="release flag", + action='store_const', + dest="target", const="RELEASE") + + parser.add_argument("--TEST_RELEASE", '-tr', help="test Release flag", + action='store_const', + dest="target", const="TEST_RELEASE") + + parser.add_argument("--RELEASE_PDB", '-rp', help="release flag", + action='store_const', dest="target", + const="RELEASE_PDB") + + parser.add_argument('--list', '-l', action=PrintPlatforms, + help='lists available platforms', nargs=0) + + parser.add_argument('--skiptools', '-s', dest='skip_tools', + help='skips rebuilding base tools', action='store_true') + + parser.add_argument('--cleanall', dest='clean_all', + help='cleans all', action='store_true') + + parser.add_argument('--clean', dest='clean', + help='cleans specific platform', action='store_true') + + parser.add_argument('--verbose', '-v', dest='verbose', + help='Verbose build log output, specify -vv for very verbose.', action='count') + + parser.add_argument("--capsule", help="capsule build enabled", + action='store_true', dest="capsule") + + parser.add_argument("--silent", help="silent build enabled", + action='store_true', dest="silent") + + parser.add_argument("--performance", help="performance build enabled", + action='store_true', dest="performance") + + parser.add_argument("--fsp", help="fsp wrapper build enabled", + action='store_true', dest="fsp") + + parser.add_argument("--fspapi", help="API mode fsp wrapper build enabled", + action='store_true', dest="fspapi") + + parser.add_argument("--hash", action="store_true", dest="UseHashCache", default=False, + help="Enable hash-based caching during build process.") + + parser.add_argument("--binary-destination", help="Generate a cache of binary \ + files in the specified directory.", + action='store', dest="BinCacheDest") + + parser.add_argument("--binary-source", help="Consume a cache of binary files \ + from the specified directory.", + action='store', dest="BinCacheSource") + + return parser.parse_args() + + +def keyboard_interruption(int_signal, int_frame): + """ Catches a keyboard interruption handler + + param int_signal: The signal this handler is called with + :type int_signal: Signal + param int_frame: The signal this handler is called with + :type int_frame: frame + :rtype: nothing + """ + print("Signal #: {} Frame: {}".format(int_signal, int_frame)) + print("Quiting...") + sys.exit(0) + + +def main(): + """ The main function of this module + :rtype: nothing + """ + # to quit the build + signal.signal(signal.SIGINT, keyboard_interruption) + + # get general build configurations + build_config = get_config() + + # get commandline parameters + arguments = get_cmd_arguments(build_config) + + if arguments.clean_all: + clean(build_config.get("DEFAULT_CONFIG")) + + # get platform specific config + platform_config = get_platform_config(arguments.platform, build_config) + + # update general build config with platform specific config + config = build_config.get("DEFAULT_CONFIG") + config.update(platform_config.get("CONFIG")) + + # if user selected clean + if arguments.clean: + clean(config, board=True) + + # Override config with cmd arguments + cmd_config_args = get_cmd_config_arguments(arguments) + config.update(cmd_config_args) + + # get pre_build configurations + config = pre_build(config, + build_type=arguments.target, + toolchain=arguments.toolchain, + silent=arguments.silent, + skip_tools=arguments.skip_tools) + + # build selected platform + config = build(config) + + # post build + post_build(config) + + +if __name__ == "__main__": + try: + EXIT_CODE = 0 + main() + except Exception as error: + EXIT_CODE = 1 + traceback.print_exc() + sys.exit(EXIT_CODE) diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h index 2c421c1a6d..db67101838 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h @@ -71,6 +71,7 @@ typedef enum { // TypeBoardPortTemplate = 0x80, // 0x80 TypeJunctionCity, + TypeTucana, // 0x82 TypeAowanda, EndOfVendorPlatformTypeEnum } EFI_PLATFORM_TYPE; |