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authorKhasim Syed Mohammed <khasim.mohammed@arm.com>2022-01-24 18:55:31 +0300
committerSami Mujawar <sami.mujawar@arm.com>2022-01-24 19:04:45 +0300
commit91a5e5bb15ce83e3deb575944730dd98f4523a70 (patch)
treef5cd0ba38223aeb42a4e4ec46e8f5bd53a3a72fe /Features/Intel/Debugging/PostCodeDebugFeaturePkg/Library
parent805059812997198da82d3c971314262f3acb248c (diff)
downloadedk2-platforms-91a5e5bb15ce83e3deb575944730dd98f4523a70.tar.xz
Silicon/ARM/NeoverseN1Soc: Port PCI Segment Library
The BasePCISegment Library in MdePkg doesn't allow configuring multiple segments required for PCIe and CCIX root port enumeration. Therefore, a custom PCI Segment library is adapted from SynQuacerPciSegmentLib and ported for N1Sdp. In addition to this, the hardware has few other limitations which affects the access to the PCIe root port: 1. ECAM space is not contiguous, root port ECAM (BDF = 0:0:0) is isolated from rest of the downstream hierarchy ECAM space. 2. Root port ECAM space is not capable of 8bit/16bit writes. 3. A slave error is generated when host accesses the configuration space of non-available device or unimplemented function on a given bus. The description of the workarounds included for these limitations can be found in the corresponding files of this patch. Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com> Reviewed-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
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