diff options
| author | Abdul Lateef Attar <AbdulLateef.Attar@amd.com> | 2026-09-26 07:55:12 +0300 |
|---|---|---|
| committer | Abdul Lateef Attar <80956128+abdattar@users.noreply.github.com> | 2026-09-29 09:11:04 +0300 |
| commit | ed046a0e13a3201ede559f12fef8724ac25dfa2a (patch) | |
| tree | cd4aa6b283d622278d1a367725196339c25724b8 /Features/Intel/Debugging/PostCodeDebugFeaturePkg/Include | |
| parent | 82bd066d1921df99baac8318bfd0d6f012434d79 (diff) | |
| download | edk2-platforms-ed046a0e13a3201ede559f12fef8724ac25dfa2a.tar.xz | |
AmdMinBoardPkg/SetCacheMtrrLib: Fix VGA/ROM3 cacheability and TOM underflow
Change the legacy VGA range (0xA0000-0xC0000) from Uncacheable to
WriteThrough. Guard the TOM1-derived WriteBack MTRR range against
TOM1 <= 1MB instead of unconditionally subtracting, avoiding a UINT64
underflow into a huge bogus range. Explicitly mark the ROM3 SPI/flash
MMIO window (read from the FCH PMIOA base-address registers) as
Uncacheable in SetCacheMtrrAfterEndOfPei(), which was previously left
with whatever attribute the default MTRR left it in.
Add the missing FCH_PMIOA_REG64 (AcpiPmTmrBlk) register offset to
AgesaModulePkg's FchRegistersCommon.h - this package's copy is a
hand-curated subset of AGESA's full register header and only had
FCH_PMIOA_REG60 defined, so SetCacheMtrrAfterEndOfPei()'s new ROM3
base-address read failed to build.
Signed-off-by: Abdul Lateef Attar <AbdulLateef.Attar@amd.com>
Diffstat (limited to 'Features/Intel/Debugging/PostCodeDebugFeaturePkg/Include')
0 files changed, 0 insertions, 0 deletions