diff options
| author | Nhi Pham <nhi@os.amperecomputing.com> | 2024-09-19 18:59:13 +0300 |
|---|---|---|
| committer | Nhi Pham <npham@amperecomputing.com> | 2024-09-25 07:04:08 +0300 |
| commit | 847cca700284040636f691e05ac7febe844e07f2 (patch) | |
| tree | 51737b7615620851ee571822e70b0c13c6aed125 | |
| parent | 27456d3b8329d0e1fca1e6f6618194f4be2abf37 (diff) | |
| download | edk2-platforms-847cca700284040636f691e05ac7febe844e07f2.tar.xz | |
AmpereAltraPkg: Apply uncrustify changes
This applies uncrustify changes to .c/.h files in the AmpereAltraPkg
package.
Signed-off-by: Nhi Pham <nhi@os.amperecomputing.com>
76 files changed, 4210 insertions, 4061 deletions
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.c index c8ea60dc7a..de2b071b41 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/ATFHobPei/ATFHobPeim.c @@ -22,7 +22,7 @@ BuildPlatformInformationHob ( VOID
)
{
- VOID *Hob;
+ VOID *Hob;
/* The ATF HOB handoff base is at PcdSystemMemoryBase */
Hob = GetNextGuidHob (
@@ -41,8 +41,8 @@ BuildPlatformInformationHob ( EFI_STATUS
EFIAPI
InitializeATFHobPeim (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
BuildPlatformInformationHob ();
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.c index 4536010a6f..fb24ac9536 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.c @@ -32,16 +32,16 @@ #include "AcpiConfigDxe.h"
-#define ACPI_VARSTORE_ATTRIBUTES EFI_VARIABLE_BOOTSERVICE_ACCESS | \
+#define ACPI_VARSTORE_ATTRIBUTES EFI_VARIABLE_BOOTSERVICE_ACCESS |\
EFI_VARIABLE_RUNTIME_ACCESS | \
EFI_VARIABLE_NON_VOLATILE
-CHAR16 AcpiVarstoreDataName[] = L"AcpiConfigNVData";
+CHAR16 AcpiVarstoreDataName[] = L"AcpiConfigNVData";
-EFI_HANDLE mDriverHandle = NULL;
-ACPI_CONFIG_PRIVATE_DATA *mPrivateData = NULL;
+EFI_HANDLE mDriverHandle = NULL;
+ACPI_CONFIG_PRIVATE_DATA *mPrivateData = NULL;
-HII_VENDOR_DEVICE_PATH mAcpiConfigHiiVendorDevicePath = {
+HII_VENDOR_DEVICE_PATH mAcpiConfigHiiVendorDevicePath = {
{
{
HARDWARE_DEVICE_PATH,
@@ -92,38 +92,39 @@ HII_VENDOR_DEVICE_PATH mAcpiConfigHiiVendorDevicePath = { EFI_STATUS
EFIAPI
ExtractConfig (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN CONST EFI_STRING Request,
- OUT EFI_STRING *Progress,
- OUT EFI_STRING *Results
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Request,
+ OUT EFI_STRING *Progress,
+ OUT EFI_STRING *Results
)
{
- EFI_STATUS Status;
- UINTN BufferSize;
- ACPI_CONFIG_PRIVATE_DATA *PrivateData;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- EFI_STRING ConfigRequest;
- EFI_STRING ConfigRequestHdr;
- UINTN Size;
- BOOLEAN AllocatedRequest;
-
- if (Progress == NULL || Results == NULL) {
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ ACPI_CONFIG_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STRING ConfigRequest;
+ EFI_STRING ConfigRequestHdr;
+ UINTN Size;
+ BOOLEAN AllocatedRequest;
+
+ if ((Progress == NULL) || (Results == NULL)) {
return EFI_INVALID_PARAMETER;
}
+
//
// Initialize the local variables.
//
- ConfigRequestHdr = NULL;
- ConfigRequest = NULL;
- Size = 0;
- *Progress = Request;
- AllocatedRequest = FALSE;
+ ConfigRequestHdr = NULL;
+ ConfigRequest = NULL;
+ Size = 0;
+ *Progress = Request;
+ AllocatedRequest = FALSE;
if ((Request != NULL) && !HiiIsConfigHdrMatch (Request, &gAcpiConfigFormSetGuid, AcpiVarstoreDataName)) {
return EFI_NOT_FOUND;
}
- PrivateData = ACPI_CONFIG_PRIVATE_FROM_THIS (This);
+ PrivateData = ACPI_CONFIG_PRIVATE_FROM_THIS (This);
HiiConfigRouting = PrivateData->HiiConfigRouting;
//
@@ -131,13 +132,13 @@ ExtractConfig ( // Try to get the current setting from variable.
//
BufferSize = sizeof (ACPI_CONFIG_VARSTORE_DATA);
- Status = gRT->GetVariable (
- AcpiVarstoreDataName,
- &gAcpiConfigFormSetGuid,
- NULL,
- &BufferSize,
- &PrivateData->Configuration
- );
+ Status = gRT->GetVariable (
+ AcpiVarstoreDataName,
+ &gAcpiConfigFormSetGuid,
+ NULL,
+ &BufferSize,
+ &PrivateData->Configuration
+ );
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
@@ -145,7 +146,7 @@ ExtractConfig ( //
// Convert buffer data to <ConfigResp> by helper function BlockToConfig()
//
- BufferSize = sizeof (ACPI_CONFIG_VARSTORE_DATA);
+ BufferSize = sizeof (ACPI_CONFIG_VARSTORE_DATA);
ConfigRequest = Request;
if ((Request == NULL) || (StrStr (Request, L"OFFSET") == NULL)) {
//
@@ -158,12 +159,13 @@ ExtractConfig ( AcpiVarstoreDataName,
PrivateData->DriverHandle
);
- Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);
+ Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);
ConfigRequest = AllocateZeroPool (Size);
ASSERT (ConfigRequest != NULL);
if (ConfigRequest == NULL) {
return EFI_OUT_OF_RESOURCES;
}
+
AllocatedRequest = TRUE;
UnicodeSPrint (ConfigRequest, Size, L"%s&OFFSET=0&WIDTH=%016LX", ConfigRequestHdr, (UINT64)BufferSize);
FreePool (ConfigRequestHdr);
@@ -222,23 +224,23 @@ ExtractConfig ( EFI_STATUS
EFIAPI
RouteConfig (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN CONST EFI_STRING Configuration,
- OUT EFI_STRING *Progress
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Configuration,
+ OUT EFI_STRING *Progress
)
{
- EFI_STATUS Status;
- UINTN BufferSize;
- ACPI_CONFIG_PRIVATE_DATA *PrivateData;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ ACPI_CONFIG_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- if (Configuration == NULL || Progress == NULL) {
+ if ((Configuration == NULL) || (Progress == NULL)) {
return EFI_INVALID_PARAMETER;
}
- PrivateData = ACPI_CONFIG_PRIVATE_FROM_THIS (This);
+ PrivateData = ACPI_CONFIG_PRIVATE_FROM_THIS (This);
HiiConfigRouting = PrivateData->HiiConfigRouting;
- *Progress = Configuration;
+ *Progress = Configuration;
//
// Check routing data in <ConfigHdr>.
@@ -252,13 +254,13 @@ RouteConfig ( // Get Buffer Storage data from EFI variable
//
BufferSize = sizeof (ACPI_CONFIG_VARSTORE_DATA);
- Status = gRT->GetVariable (
- AcpiVarstoreDataName,
- &gAcpiConfigFormSetGuid,
- NULL,
- &BufferSize,
- &PrivateData->Configuration
- );
+ Status = gRT->GetVariable (
+ AcpiVarstoreDataName,
+ &gAcpiConfigFormSetGuid,
+ NULL,
+ &BufferSize,
+ &PrivateData->Configuration
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -267,13 +269,13 @@ RouteConfig ( // Convert <ConfigResp> to buffer data by helper function ConfigToBlock()
//
BufferSize = sizeof (ACPI_CONFIG_VARSTORE_DATA);
- Status = HiiConfigRouting->ConfigToBlock (
- HiiConfigRouting,
- Configuration,
- (UINT8 *)&PrivateData->Configuration,
- &BufferSize,
- Progress
- );
+ Status = HiiConfigRouting->ConfigToBlock (
+ HiiConfigRouting,
+ Configuration,
+ (UINT8 *)&PrivateData->Configuration,
+ &BufferSize,
+ Progress
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -313,12 +315,12 @@ RouteConfig ( EFI_STATUS
EFIAPI
DriverCallback (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN EFI_BROWSER_ACTION Action,
- IN EFI_QUESTION_ID QuestionId,
- IN UINT8 Type,
- IN EFI_IFR_TYPE_VALUE *Value,
- OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN EFI_BROWSER_ACTION Action,
+ IN EFI_QUESTION_ID QuestionId,
+ IN UINT8 Type,
+ IN EFI_IFR_TYPE_VALUE *Value,
+ OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
)
{
if (Action != EFI_BROWSER_ACTION_CHANGING) {
@@ -327,10 +329,11 @@ DriverCallback ( //
return EFI_UNSUPPORTED;
}
- if (((Value == NULL)
- && (Action != EFI_BROWSER_ACTION_FORM_OPEN)
- && (Action != EFI_BROWSER_ACTION_FORM_CLOSE))
- || (ActionRequest == NULL))
+
+ if ( ( (Value == NULL)
+ && (Action != EFI_BROWSER_ACTION_FORM_OPEN)
+ && (Action != EFI_BROWSER_ACTION_FORM_CLOSE))
+ || (ActionRequest == NULL))
{
return EFI_INVALID_PARAMETER;
}
@@ -341,11 +344,11 @@ DriverCallback ( STATIC
EFI_STATUS
UpdateCPPCConfig (
- IN ACPI_CONFIG_PRIVATE_DATA *PrivateData
+ IN ACPI_CONFIG_PRIVATE_DATA *PrivateData
)
{
- EFI_STATUS Status;
- CHAR8 Buffer[64];
+ EFI_STATUS Status;
+ CHAR8 Buffer[64];
ASSERT (PrivateData != NULL);
@@ -364,11 +367,11 @@ UpdateCPPCConfig ( STATIC
EFI_STATUS
UpdateLPIConfig (
- IN ACPI_CONFIG_PRIVATE_DATA *PrivateData
+ IN ACPI_CONFIG_PRIVATE_DATA *PrivateData
)
{
- EFI_STATUS Status;
- CHAR8 Buffer[64];
+ EFI_STATUS Status;
+ CHAR8 Buffer[64];
ASSERT (PrivateData != NULL);
@@ -387,16 +390,16 @@ UpdateLPIConfig ( STATIC
VOID
UpdateAcpiOnReadyToBoot (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- EFI_STATUS Status;
- EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol;
- EFI_ACPI_DESCRIPTION_HEADER *Table;
- EFI_ACPI_HANDLE TableHandle;
- UINTN TableKey;
- UINTN TableIndex;
+ EFI_STATUS Status;
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol;
+ EFI_ACPI_DESCRIPTION_HEADER *Table;
+ EFI_ACPI_HANDLE TableHandle;
+ UINTN TableKey;
+ UINTN TableIndex;
ASSERT (mPrivateData != NULL);
@@ -416,13 +419,13 @@ UpdateAcpiOnReadyToBoot ( mPrivateData->AcpiSdtProtocol = AcpiSdtProtocol;
TableIndex = 0;
- Status = AcpiLocateTableBySignature (
- AcpiSdtProtocol,
- EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
- &TableIndex,
- &Table,
- &TableKey
- );
+ Status = AcpiLocateTableBySignature (
+ AcpiSdtProtocol,
+ EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ &TableIndex,
+ &Table,
+ &TableKey
+ );
ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status)) {
return;
@@ -486,20 +489,20 @@ AcpiConfigUnload ( EFI_STATUS
EFIAPI
AcpiConfigEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- EFI_HII_HANDLE HiiHandle;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- UINTN BufferSize;
- ACPI_CONFIG_VARSTORE_DATA *Configuration;
- BOOLEAN ActionFlag;
- EFI_STRING ConfigRequestHdr;
- EFI_EVENT ReadyToBootEvent;
- PLATFORM_INFO_HOB *PlatformHob;
- VOID *Hob;
+ EFI_STATUS Status;
+ EFI_HII_HANDLE HiiHandle;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ UINTN BufferSize;
+ ACPI_CONFIG_VARSTORE_DATA *Configuration;
+ BOOLEAN ActionFlag;
+ EFI_STRING ConfigRequestHdr;
+ EFI_EVENT ReadyToBootEvent;
+ PLATFORM_INFO_HOB *PlatformHob;
+ VOID *Hob;
//
// Initialize the local variables.
@@ -517,8 +520,8 @@ AcpiConfigEntryPoint ( mPrivateData->Signature = ACPI_CONFIG_PRIVATE_SIGNATURE;
mPrivateData->ConfigAccess.ExtractConfig = ExtractConfig;
- mPrivateData->ConfigAccess.RouteConfig = RouteConfig;
- mPrivateData->ConfigAccess.Callback = DriverCallback;
+ mPrivateData->ConfigAccess.RouteConfig = RouteConfig;
+ mPrivateData->ConfigAccess.Callback = DriverCallback;
//
// Get the Platform HOB
@@ -529,6 +532,7 @@ AcpiConfigEntryPoint ( AcpiConfigUnload ();
return EFI_DEVICE_ERROR;
}
+
PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
mPrivateData->PlatformHob = PlatformHob;
@@ -540,6 +544,7 @@ AcpiConfigEntryPoint ( if (EFI_ERROR (Status)) {
return Status;
}
+
mPrivateData->HiiConfigRouting = HiiConfigRouting;
Status = gBS->InstallMultipleProtocolInterfaces (
@@ -591,7 +596,7 @@ AcpiConfigEntryPoint ( ASSERT (ConfigRequestHdr != NULL);
BufferSize = sizeof (ACPI_CONFIG_VARSTORE_DATA);
- Status = gRT->GetVariable (AcpiVarstoreDataName, &gAcpiConfigFormSetGuid, NULL, &BufferSize, Configuration);
+ Status = gRT->GetVariable (AcpiVarstoreDataName, &gAcpiConfigFormSetGuid, NULL, &BufferSize, Configuration);
if (EFI_ERROR (Status)) {
//
// Store zero data Buffer Storage to EFI variable
@@ -607,6 +612,7 @@ AcpiConfigEntryPoint ( AcpiConfigUnload ();
return Status;
}
+
//
// EFI variable for NV config doesn't exit, we should build this variable
// based on default values stored in IFR
@@ -626,6 +632,7 @@ AcpiConfigEntryPoint ( return EFI_INVALID_PARAMETER;
}
}
+
FreePool (ConfigRequestHdr);
Status = gBS->CreateEventEx (
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.h index 8a2cc2f5e6..1725e37bca 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.h +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/AcpiConfigDxe/AcpiConfigDxe.h @@ -12,37 +12,37 @@ //
// This is the generated IFR binary data for each formset defined in VFR.
//
-extern UINT8 AcpiConfigVfrBin[];
+extern UINT8 AcpiConfigVfrBin[];
//
// This is the generated String package data for all .UNI files.
//
-extern UINT8 AcpiConfigDxeStrings[];
+extern UINT8 AcpiConfigDxeStrings[];
//
// Signature: Ampere Computing ACPI Configuration
//
-#define ACPI_CONFIG_PRIVATE_SIGNATURE SIGNATURE_32 ('A', 'C', 'A', 'C')
+#define ACPI_CONFIG_PRIVATE_SIGNATURE SIGNATURE_32 ('A', 'C', 'A', 'C')
typedef struct {
- UINTN Signature;
+ UINTN Signature;
- EFI_HANDLE DriverHandle;
- EFI_HII_HANDLE HiiHandle;
- ACPI_CONFIG_VARSTORE_DATA Configuration;
- PLATFORM_INFO_HOB *PlatformHob;
- EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol;
- EFI_ACPI_HANDLE AcpiTableHandle;
+ EFI_HANDLE DriverHandle;
+ EFI_HII_HANDLE HiiHandle;
+ ACPI_CONFIG_VARSTORE_DATA Configuration;
+ PLATFORM_INFO_HOB *PlatformHob;
+ EFI_ACPI_SDT_PROTOCOL *AcpiSdtProtocol;
+ EFI_ACPI_HANDLE AcpiTableHandle;
//
// Consumed protocol
//
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
//
// Produced protocol
//
- EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
+ EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
} ACPI_CONFIG_PRIVATE_DATA;
#define ACPI_CONFIG_PRIVATE_FROM_THIS(a) CR (a, ACPI_CONFIG_PRIVATE_DATA, ConfigAccess, ACPI_CONFIG_PRIVATE_SIGNATURE)
@@ -53,8 +53,8 @@ typedef struct { /// HII specific Vendor Device Path definition.
///
typedef struct {
- VENDOR_DEVICE_PATH VendorDevicePath;
- EFI_DEVICE_PATH_PROTOCOL End;
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
} HII_VENDOR_DEVICE_PATH;
#pragma pack()
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressDxe/BootProgressDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressDxe/BootProgressDxe.c index f101591d8c..9780569854 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressDxe/BootProgressDxe.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressDxe/BootProgressDxe.c @@ -22,8 +22,8 @@ #include <Protocol/ReportStatusCodeHandler.h>
typedef struct {
- UINT8 Byte;
- EFI_STATUS_CODE_VALUE Value;
+ UINT8 Byte;
+ EFI_STATUS_CODE_VALUE Value;
} STATUS_CODE_TO_CHECKPOINT;
typedef enum {
@@ -34,7 +34,7 @@ typedef enum { BootProgressStateMax
} BOOT_PROGRESS_STATE;
-UINT32 DxeProgressCode[] = {
+UINT32 DxeProgressCode[] = {
(EFI_SOFTWARE_DXE_CORE | EFI_SW_DXE_CORE_PC_ENTRY_POINT), // DXE Core is started
(EFI_COMPUTING_UNIT_CHIPSET | EFI_CHIPSET_PC_DXE_HB_INIT), // PCI host bridge initialization
(EFI_SOFTWARE_DXE_CORE | EFI_SW_DXE_CORE_PC_HANDOFF_TO_NEXT), // Boot Device Selection (BDS) phase is startedÂ
@@ -68,7 +68,7 @@ UINT32 DxeProgressCode[] = { 0 // Must ended by 0
};
-UINT32 DxeErrorCode[] = {
+UINT32 DxeErrorCode[] = {
(EFI_SOFTWARE_DXE_CORE | EFI_SW_DXE_CORE_EC_NO_ARCH), // Some of the Architectural Protocols are not available
(EFI_IO_BUS_PCI | EFI_IOB_EC_RESOURCE_CONFLICT), // PCI resource allocation error. Out of Resources
(EFI_PERIPHERAL_LOCAL_CONSOLE | EFI_P_EC_NOT_DETECTED), // No Console Output Devices are found
@@ -81,27 +81,29 @@ UINT32 DxeErrorCode[] = { 0 // Must end by 0
};
-EFI_RSC_HANDLER_PROTOCOL *mRscHandlerProtocol = NULL;
+EFI_RSC_HANDLER_PROTOCOL *mRscHandlerProtocol = NULL;
-STATIC UINT8 mBootstate = BootStart;
+STATIC UINT8 mBootstate = BootStart;
-STATIC BOOLEAN mEndOfDxe = FALSE;
+STATIC BOOLEAN mEndOfDxe = FALSE;
STATIC
BOOLEAN
StatusCodeFilter (
- UINT32 *Map,
- EFI_STATUS_CODE_VALUE Value
+ UINT32 *Map,
+ EFI_STATUS_CODE_VALUE Value
)
{
- UINTN Index = 0;
+ UINTN Index = 0;
while (Map[Index] != 0) {
if (Map[Index] == Value) {
return TRUE;
}
+
Index++;
}
+
return FALSE;
}
@@ -126,17 +128,17 @@ StatusCodeFilter ( EFI_STATUS
EFIAPI
BootProgressListenerDxe (
- IN EFI_STATUS_CODE_TYPE CodeType,
- IN EFI_STATUS_CODE_VALUE Value,
- IN UINT32 Instance,
- IN EFI_GUID *CallerId,
- IN EFI_STATUS_CODE_DATA *Data
+ IN EFI_STATUS_CODE_TYPE CodeType,
+ IN EFI_STATUS_CODE_VALUE Value,
+ IN UINT32 Instance,
+ IN EFI_GUID *CallerId,
+ IN EFI_STATUS_CODE_DATA *Data
)
{
EFI_STATUS Status;
UINT8 BootStage;
BOOLEAN IsProgress = FALSE;
- BOOLEAN IsError = FALSE;
+ BOOLEAN IsError = FALSE;
if ((CodeType & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) {
IsProgress = StatusCodeFilter (DxeProgressCode, Value);
@@ -162,7 +164,7 @@ BootProgressListenerDxe ( if (IsError) {
mBootstate = BootFailed;
- } else if ((Value == (EFI_SOFTWARE_EFI_BOOT_SERVICE | EFI_SW_BS_PC_EXIT_BOOT_SERVICES))
+ } else if ( (Value == (EFI_SOFTWARE_EFI_BOOT_SERVICE | EFI_SW_BS_PC_EXIT_BOOT_SERVICES))
|| (Value == (EFI_SOFTWARE_DXE_CORE | EFI_SW_DXE_CORE_PC_HANDOFF_TO_NEXT)))
{
/* Set boot complete when reach to Exit Boot Service event or DXE Core Handoff To Next */
@@ -184,8 +186,8 @@ BootProgressListenerDxe ( mEndOfDxe = TRUE;
}
- if (Value == (EFI_SOFTWARE_EFI_BOOT_SERVICE | EFI_SW_BS_PC_EXIT_BOOT_SERVICES) &&
- mRscHandlerProtocol != NULL)
+ if ((Value == (EFI_SOFTWARE_EFI_BOOT_SERVICE | EFI_SW_BS_PC_EXIT_BOOT_SERVICES)) &&
+ (mRscHandlerProtocol != NULL))
{
mRscHandlerProtocol->Unregister (BootProgressListenerDxe);
}
@@ -193,7 +195,6 @@ BootProgressListenerDxe ( return EFI_SUCCESS;
}
-
/**
The module Entry Point of the Firmware Performance Data Table DXE driver.
@@ -207,11 +208,11 @@ BootProgressListenerDxe ( EFI_STATUS
EFIAPI
BootProgressDxeEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// Get Report Status Code Handler Protocol.
@@ -225,6 +226,7 @@ BootProgressDxeEntryPoint ( if (!EFI_ERROR (Status)) {
Status = mRscHandlerProtocol->Register (BootProgressListenerDxe, TPL_HIGH_LEVEL);
}
+
ASSERT_EFI_ERROR (Status);
return EFI_SUCCESS;
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressPeim/BootProgressPeim.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressPeim/BootProgressPeim.c index 098302fcbd..8c96491d6c 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressPeim/BootProgressPeim.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/BootProgress/BootProgressPeim/BootProgressPeim.c @@ -28,7 +28,7 @@ typedef enum { BootProgressStateMax
} BOOT_PROGRESS_STATE;
-UINT32 PeiProgressStatusCode[] = {
+UINT32 PeiProgressStatusCode[] = {
// Regular boot
(EFI_SOFTWARE_PEI_CORE | EFI_SW_PEI_CORE_PC_ENTRY_POINT), // PEI Core is started
(EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_PC_POWER_ON_INIT), // Pre-memory CPU initialization is started
@@ -54,7 +54,7 @@ UINT32 PeiProgressStatusCode[] = { 0 // Must end with 0
};
-UINT32 PeiErrorStatusCode[] = {
+UINT32 PeiErrorStatusCode[] = {
// Regular boot
(EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_EC_INVALID_TYPE), // Memory initialization error. Invalid memory type
(EFI_COMPUTING_UNIT_MEMORY | EFI_CU_MEMORY_EC_INVALID_SPEED), // Memory initialization error. Incompatible memory speed
@@ -86,21 +86,22 @@ UINT32 PeiErrorStatusCode[] = { };
// Should always be BootStart when start
-STATIC UINT8 mBootstate = BootStart;
+STATIC UINT8 mBootstate = BootStart;
STATIC
BOOLEAN
StatusCodeFilter (
- UINT32 *Map,
- EFI_STATUS_CODE_VALUE Value
+ UINT32 *Map,
+ EFI_STATUS_CODE_VALUE Value
)
{
- UINTN Index = 0;
+ UINTN Index = 0;
while (Map[Index] != 0) {
if (Map[Index] == Value) {
return TRUE;
}
+
Index++;
}
@@ -130,16 +131,16 @@ StatusCodeFilter ( EFI_STATUS
EFIAPI
BootProgressListenerPei (
- IN CONST EFI_PEI_SERVICES **PeiServices,
- IN EFI_STATUS_CODE_TYPE CodeType,
- IN EFI_STATUS_CODE_VALUE Value,
- IN UINT32 Instance,
- IN CONST EFI_GUID *CallerId,
- IN CONST EFI_STATUS_CODE_DATA *Data
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_STATUS_CODE_TYPE CodeType,
+ IN EFI_STATUS_CODE_VALUE Value,
+ IN UINT32 Instance,
+ IN CONST EFI_GUID *CallerId,
+ IN CONST EFI_STATUS_CODE_DATA *Data
)
{
- BOOLEAN IsProgress = FALSE;
- BOOLEAN IsError = FALSE;
+ BOOLEAN IsProgress = FALSE;
+ BOOLEAN IsError = FALSE;
if ((CodeType & EFI_STATUS_CODE_TYPE_MASK) == EFI_PROGRESS_CODE) {
IsProgress = StatusCodeFilter (PeiProgressStatusCode, Value);
@@ -187,12 +188,12 @@ BootProgressListenerPei ( EFI_STATUS
EFIAPI
BootProgressPeiEntryPoint (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- EFI_STATUS Status;
- EFI_PEI_RSC_HANDLER_PPI *RscHandler;
+ EFI_STATUS Status;
+ EFI_PEI_RSC_HANDLER_PPI *RscHandler;
Status = PeiServicesLocatePpi (
&gEfiPeiRscHandlerPpiGuid,
@@ -205,6 +206,7 @@ BootProgressPeiEntryPoint ( if (!EFI_ERROR (Status)) {
Status = RscHandler->Register (BootProgressListenerPei);
}
+
ASSERT_EFI_ERROR (Status);
return EFI_SUCCESS;
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.c index 7ce8c165c2..2c57d99922 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.c @@ -38,10 +38,10 @@ #define NEAR_ATOMIC_DISABLE_DEFAULT 0x00 /* Enable Near Atomic */
#define CPU_SLC_REPLACE_POLICY 0x00 /* eLRU */
-EFI_HANDLE mDriverHandle = NULL;
-CPU_CONFIG_PRIVATE_DATA *mPrivateData = NULL;
+EFI_HANDLE mDriverHandle = NULL;
+CPU_CONFIG_PRIVATE_DATA *mPrivateData = NULL;
-HII_VENDOR_DEVICE_PATH mCpuConfigHiiVendorDevicePath = {
+HII_VENDOR_DEVICE_PATH mCpuConfigHiiVendorDevicePath = {
{
{
HARDWARE_DEVICE_PATH,
@@ -66,11 +66,11 @@ HII_VENDOR_DEVICE_PATH mCpuConfigHiiVendorDevicePath = { STATIC
EFI_STATUS
CpuNvParamGet (
- OUT CPU_VARSTORE_DATA *Configuration
+ OUT CPU_VARSTORE_DATA *Configuration
)
{
- EFI_STATUS Status;
- UINT32 Value;
+ EFI_STATUS Status;
+ UINT32 Value;
ASSERT (Configuration != NULL);
@@ -92,11 +92,11 @@ CpuNvParamGet ( STATIC
EFI_STATUS
CpuNvParamSet (
- IN CPU_VARSTORE_DATA *Configuration
+ IN CPU_VARSTORE_DATA *Configuration
)
{
- EFI_STATUS Status;
- UINT32 Value;
+ EFI_STATUS Status;
+ UINT32 Value;
ASSERT (Configuration != NULL);
@@ -107,7 +107,7 @@ CpuNvParamSet ( );
ASSERT_EFI_ERROR (Status);
- if (EFI_ERROR (Status) || Value != Configuration->CpuSubNumaMode) {
+ if (EFI_ERROR (Status) || (Value != Configuration->CpuSubNumaMode)) {
Status = NVParamSet (
NV_SI_SUBNUMA_MODE,
NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
@@ -130,8 +130,8 @@ SetupDefaultSettings ( VOID
)
{
- EFI_STATUS Status;
- UINT32 Value;
+ EFI_STATUS Status;
+ UINT32 Value;
//
// Subnuma Mode
@@ -224,48 +224,49 @@ SetupDefaultSettings ( EFI_STATUS
EFIAPI
CpuConfigExtractConfig (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN CONST EFI_STRING Request,
- OUT EFI_STRING *Progress,
- OUT EFI_STRING *Results
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Request,
+ OUT EFI_STRING *Progress,
+ OUT EFI_STRING *Results
)
{
- EFI_STATUS Status;
- UINTN BufferSize;
- CPU_CONFIG_PRIVATE_DATA *PrivateData;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- EFI_STRING ConfigRequest;
- EFI_STRING ConfigRequestHdr;
- UINTN Size;
- BOOLEAN AllocatedRequest;
-
- if (Progress == NULL || Results == NULL) {
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ CPU_CONFIG_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STRING ConfigRequest;
+ EFI_STRING ConfigRequestHdr;
+ UINTN Size;
+ BOOLEAN AllocatedRequest;
+
+ if ((Progress == NULL) || (Results == NULL)) {
return EFI_INVALID_PARAMETER;
}
+
//
// Initialize the local variables.
//
- ConfigRequestHdr = NULL;
- ConfigRequest = NULL;
- Size = 0;
- *Progress = Request;
- AllocatedRequest = FALSE;
+ ConfigRequestHdr = NULL;
+ ConfigRequest = NULL;
+ Size = 0;
+ *Progress = Request;
+ AllocatedRequest = FALSE;
if ((Request != NULL) && !HiiIsConfigHdrMatch (Request, &gCpuConfigFormSetGuid, CPU_CONFIG_VARIABLE_NAME)) {
return EFI_NOT_FOUND;
}
- PrivateData = CPU_CONFIG_PRIVATE_FROM_THIS (This);
+ PrivateData = CPU_CONFIG_PRIVATE_FROM_THIS (This);
HiiConfigRouting = PrivateData->HiiConfigRouting;
BufferSize = sizeof (CPU_VARSTORE_DATA);
- Status = gRT->GetVariable (
- CPU_CONFIG_VARIABLE_NAME,
- &gCpuConfigFormSetGuid,
- NULL,
- &BufferSize,
- &PrivateData->Configuration
- );
+ Status = gRT->GetVariable (
+ CPU_CONFIG_VARIABLE_NAME,
+ &gCpuConfigFormSetGuid,
+ NULL,
+ &BufferSize,
+ &PrivateData->Configuration
+ );
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
@@ -277,10 +278,11 @@ CpuConfigExtractConfig ( if (EFI_ERROR (Status)) {
return Status;
}
+
//
// Convert buffer data to <ConfigResp> by helper function BlockToConfig()
//
- BufferSize = sizeof (CPU_VARSTORE_DATA);
+ BufferSize = sizeof (CPU_VARSTORE_DATA);
ConfigRequest = Request;
if ((Request == NULL) || (StrStr (Request, L"OFFSET") == NULL)) {
//
@@ -289,12 +291,13 @@ CpuConfigExtractConfig ( // followed by "&OFFSET=0&WIDTH=WWWWWWWWWWWWWWWW" followed by a Null-terminator
//
ConfigRequestHdr = HiiConstructConfigHdr (&gCpuConfigFormSetGuid, CPU_CONFIG_VARIABLE_NAME, PrivateData->DriverHandle);
- Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);
- ConfigRequest = AllocateZeroPool (Size);
+ Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);
+ ConfigRequest = AllocateZeroPool (Size);
ASSERT (ConfigRequest != NULL);
if (ConfigRequest == NULL) {
return EFI_OUT_OF_RESOURCES;
}
+
AllocatedRequest = TRUE;
UnicodeSPrint (ConfigRequest, Size, L"%s&OFFSET=0&WIDTH=%016LX", ConfigRequestHdr, (UINT64)BufferSize);
FreePool (ConfigRequestHdr);
@@ -353,23 +356,23 @@ CpuConfigExtractConfig ( EFI_STATUS
EFIAPI
CpuConfigRouteConfig (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN CONST EFI_STRING Configuration,
- OUT EFI_STRING *Progress
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Configuration,
+ OUT EFI_STRING *Progress
)
{
- EFI_STATUS Status;
- UINTN BufferSize;
- CPU_CONFIG_PRIVATE_DATA *PrivateData;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ CPU_CONFIG_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- if (Configuration == NULL || Progress == NULL) {
+ if ((Configuration == NULL) || (Progress == NULL)) {
return EFI_INVALID_PARAMETER;
}
- PrivateData = CPU_CONFIG_PRIVATE_FROM_THIS (This);
+ PrivateData = CPU_CONFIG_PRIVATE_FROM_THIS (This);
HiiConfigRouting = PrivateData->HiiConfigRouting;
- *Progress = Configuration;
+ *Progress = Configuration;
//
// Check routing data in <ConfigHdr>.
@@ -380,13 +383,13 @@ CpuConfigRouteConfig ( }
BufferSize = sizeof (CPU_VARSTORE_DATA);
- Status = gRT->GetVariable (
- CPU_CONFIG_VARIABLE_NAME,
- &gCpuConfigFormSetGuid,
- NULL,
- &BufferSize,
- &PrivateData->Configuration
- );
+ Status = gRT->GetVariable (
+ CPU_CONFIG_VARIABLE_NAME,
+ &gCpuConfigFormSetGuid,
+ NULL,
+ &BufferSize,
+ &PrivateData->Configuration
+ );
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
@@ -403,13 +406,13 @@ CpuConfigRouteConfig ( // Convert <ConfigResp> to buffer data by helper function ConfigToBlock()
//
BufferSize = sizeof (CPU_VARSTORE_DATA);
- Status = HiiConfigRouting->ConfigToBlock (
- HiiConfigRouting,
- Configuration,
- (UINT8 *)&PrivateData->Configuration,
- &BufferSize,
- Progress
- );
+ Status = HiiConfigRouting->ConfigToBlock (
+ HiiConfigRouting,
+ Configuration,
+ (UINT8 *)&PrivateData->Configuration,
+ &BufferSize,
+ Progress
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -457,17 +460,17 @@ CpuConfigRouteConfig ( EFI_STATUS
EFIAPI
CpuConfigCallback (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN EFI_BROWSER_ACTION Action,
- IN EFI_QUESTION_ID QuestionId,
- IN UINT8 Type,
- IN EFI_IFR_TYPE_VALUE *Value,
- OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN EFI_BROWSER_ACTION Action,
+ IN EFI_QUESTION_ID QuestionId,
+ IN UINT8 Type,
+ IN EFI_IFR_TYPE_VALUE *Value,
+ OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
)
{
CPU_VARSTORE_DATA *Configuration;
- if (((Value == NULL) && (Action != EFI_BROWSER_ACTION_FORM_OPEN) && (Action != EFI_BROWSER_ACTION_FORM_CLOSE))||
+ if (((Value == NULL) && (Action != EFI_BROWSER_ACTION_FORM_OPEN) && (Action != EFI_BROWSER_ACTION_FORM_CLOSE)) ||
(ActionRequest == NULL))
{
return EFI_INVALID_PARAMETER;
@@ -484,11 +487,11 @@ CpuConfigCallback ( //
// Disable SLC as L3$ option if the CPU configuration is 1P monolithic mode
//
- if (!IsSlaveSocketActive () && Configuration->CpuSubNumaMode == CPU_SUBNUMA_MODE_MONO) {
+ if (!IsSlaveSocketActive () && (Configuration->CpuSubNumaMode == CPU_SUBNUMA_MODE_MONO)) {
Configuration->CpuSlcAsL3Permitted = CPU_SLC_AS_L3_PERMITTED_YES;
} else {
Configuration->CpuSlcAsL3Permitted = CPU_SLC_AS_L3_PERMITTED_NO;
- Configuration->CpuSlcAsL3 = CPU_SLC_AS_L3_DISABLE;
+ Configuration->CpuSlcAsL3 = CPU_SLC_AS_L3_DISABLE;
}
//
@@ -532,17 +535,17 @@ CpuConfigUnload ( EFI_STATUS
CpuConfigDxeEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- EFI_HII_HANDLE HiiHandle;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- BOOLEAN ActionFlag;
- CPU_VARSTORE_DATA *Configuration;
- EFI_STRING ConfigRequestHdr;
- UINTN BufferSize;
+ EFI_STATUS Status;
+ EFI_HII_HANDLE HiiHandle;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ BOOLEAN ActionFlag;
+ CPU_VARSTORE_DATA *Configuration;
+ EFI_STRING ConfigRequestHdr;
+ UINTN BufferSize;
//
// With the fresh system, the NVParam value is invalid (0xFFFFFFFF).
@@ -565,8 +568,8 @@ CpuConfigDxeEntryPoint ( mPrivateData->Signature = CPU_CONFIG_PRIVATE_SIGNATURE;
mPrivateData->ConfigAccess.ExtractConfig = CpuConfigExtractConfig;
- mPrivateData->ConfigAccess.RouteConfig = CpuConfigRouteConfig;
- mPrivateData->ConfigAccess.Callback = CpuConfigCallback;
+ mPrivateData->ConfigAccess.RouteConfig = CpuConfigRouteConfig;
+ mPrivateData->ConfigAccess.Callback = CpuConfigCallback;
//
// Locate ConfigRouting protocol
@@ -575,6 +578,7 @@ CpuConfigDxeEntryPoint ( if (EFI_ERROR (Status)) {
return Status;
}
+
mPrivateData->HiiConfigRouting = HiiConfigRouting;
Status = gBS->InstallMultipleProtocolInterfaces (
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.h index 77e691978d..30e68297e6 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.h +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/CpuConfigDxe/CpuConfigDxe.h @@ -14,25 +14,25 @@ //
// This is the generated IFR binary data for each formset defined in VFR.
//
-extern UINT8 CpuConfigVfrBin[];
+extern UINT8 CpuConfigVfrBin[];
//
// This is the generated String package data for all .UNI files.
//
-extern UINT8 CpuConfigDxeStrings[];
+extern UINT8 CpuConfigDxeStrings[];
-#define CPU_CONFIG_PRIVATE_SIGNATURE SIGNATURE_32 ('C', 'P', 'U', '_')
+#define CPU_CONFIG_PRIVATE_SIGNATURE SIGNATURE_32 ('C', 'P', 'U', '_')
typedef struct {
- UINTN Signature;
+ UINTN Signature;
- EFI_HANDLE DriverHandle;
- EFI_HII_HANDLE HiiHandle;
- CPU_VARSTORE_DATA Configuration;
+ EFI_HANDLE DriverHandle;
+ EFI_HII_HANDLE HiiHandle;
+ CPU_VARSTORE_DATA Configuration;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
+ EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
} CPU_CONFIG_PRIVATE_DATA;
#define CPU_CONFIG_PRIVATE_FROM_THIS(a) CR (a, CPU_CONFIG_PRIVATE_DATA, ConfigAccess, CPU_CONFIG_PRIVATE_SIGNATURE)
@@ -43,8 +43,8 @@ typedef struct { /// HII specific Vendor Device Path definition.
///
typedef struct {
- VENDOR_DEVICE_PATH VendorDevicePath;
- EFI_DEVICE_PATH_PROTOCOL End;
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
} HII_VENDOR_DEVICE_PATH;
#pragma pack()
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.c index 2bb01b686a..3367b6b391 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/DebugInfoPei/DebugInfoPei.c @@ -22,10 +22,10 @@ #include <NVParamDef.h>
-#define GB_SCALE_FACTOR 1073741824
-#define MB_SCALE_FACTOR 1048576
-#define KB_SCALE_FACTOR 1024
-#define MHZ_SCALE_FACTOR 1000000
+#define GB_SCALE_FACTOR 1073741824
+#define MB_SCALE_FACTOR 1048576
+#define KB_SCALE_FACTOR 1024
+#define MHZ_SCALE_FACTOR 1000000
/**
Print any existence NVRAM.
@@ -35,11 +35,11 @@ PrintNVRAM ( VOID
)
{
- EFI_STATUS Status;
- NVPARAM Idx;
- UINT32 Val;
- UINT16 ACLRd = NV_PERM_ALL;
- BOOLEAN Flag;
+ EFI_STATUS Status;
+ NVPARAM Idx;
+ UINT32 Val;
+ UINT16 ACLRd = NV_PERM_ALL;
+ BOOLEAN Flag;
Flag = FALSE;
for (Idx = NV_PREBOOT_PARAM_START; Idx <= NV_PREBOOT_PARAM_MAX; Idx += NVPARAM_SIZE) {
@@ -49,6 +49,7 @@ PrintNVRAM ( DebugPrint (DEBUG_INIT, "Pre-boot Configuration Setting:\n");
Flag = TRUE;
}
+
DebugPrint (DEBUG_INIT, " %04X: 0x%X (%d)\n", (UINT32)Idx, Val, Val);
}
}
@@ -61,6 +62,7 @@ PrintNVRAM ( DebugPrint (DEBUG_INIT, "Manufacturer Configuration Setting:\n");
Flag = TRUE;
}
+
DebugPrint (DEBUG_INIT, " %04X: 0x%X (%d)\n", (UINT32)Idx, Val, Val);
}
}
@@ -73,6 +75,7 @@ PrintNVRAM ( DebugPrint (DEBUG_INIT, "User Configuration Setting:\n");
Flag = TRUE;
}
+
DebugPrint (DEBUG_INIT, " %04X: 0x%X (%d)\n", (UINT32)Idx, Val, Val);
}
}
@@ -85,6 +88,7 @@ PrintNVRAM ( DebugPrint (DEBUG_INIT, "Board Configuration Setting:\n");
Flag = TRUE;
}
+
DebugPrint (DEBUG_INIT, " %04X: 0x%X (%d)\n", (UINT32)Idx, Val, Val);
}
}
@@ -93,28 +97,28 @@ PrintNVRAM ( STATIC
CHAR8 *
GetCCIXLinkSpeed (
- IN UINTN Speed
+ IN UINTN Speed
)
{
switch (Speed) {
- case 1:
- return "2.5 GT/s";
+ case 1:
+ return "2.5 GT/s";
- case 2:
- return "5 GT/s";
+ case 2:
+ return "5 GT/s";
- case 3:
- return "8 GT/s";
+ case 3:
+ return "8 GT/s";
- case 4:
- case 6:
- return "16 GT/s";
+ case 4:
+ case 6:
+ return "16 GT/s";
- case 0xa:
- return "20 GT/s";
+ case 0xa:
+ return "20 GT/s";
- case 0xf:
- return "25 GT/s";
+ case 0xf:
+ return "25 GT/s";
}
return "Unknown";
@@ -150,17 +154,20 @@ PrintSystemInfo ( DebugPrint (DEBUG_INIT, " Number of active sockets : %d\n", GetNumberOfActiveSockets ());
DebugPrint (DEBUG_INIT, " Number of active cores : %d\n", GetNumberOfActiveCores ());
if (IsSlaveSocketActive ()) {
- DebugPrint (DEBUG_INIT,
+ DebugPrint (
+ DEBUG_INIT,
" Inter Socket Connection 0 : Width: x%d / Speed %a\n",
PlatformHob->Link2PWidth[0],
GetCCIXLinkSpeed (PlatformHob->Link2PSpeed[0])
);
- DebugPrint (DEBUG_INIT,
+ DebugPrint (
+ DEBUG_INIT,
" Inter Socket Connection 1 : Width: x%d / Speed %a\n",
PlatformHob->Link2PWidth[1],
GetCCIXLinkSpeed (PlatformHob->Link2PSpeed[1])
);
}
+
for (Idx = 0; Idx < GetNumberOfActiveSockets (); Idx++) {
DebugPrint (DEBUG_INIT, " Socket[%d]: Core voltage : %d\n", Idx, PlatformHob->CoreVoltage[Idx]);
DebugPrint (DEBUG_INIT, " Socket[%d]: SCU ProductID : %X\n", Idx, PlatformHob->ScuProductId[Idx]);
@@ -198,8 +205,8 @@ PrintSystemInfo ( EFI_STATUS
EFIAPI
DebugInfoPeiEntryPoint (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
PrintSystemInfo ();
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c index 5bb03a0b00..c9161f30bb 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashFvbDxe/FlashFvbDxe.c @@ -18,11 +18,11 @@ // These temporary buffers are used to calculate and convert linear virtual
// to physical address
//
-STATIC UINT64 mNvFlashBase;
-STATIC UINT32 mNvFlashSize;
-STATIC UINT32 mFlashBlockSize;
-STATIC UINT64 mNvStorageBase;
-STATIC UINT64 mNvStorageSize;
+STATIC UINT64 mNvFlashBase;
+STATIC UINT32 mNvFlashSize;
+STATIC UINT32 mFlashBlockSize;
+STATIC UINT64 mNvStorageBase;
+STATIC UINT64 mNvStorageSize;
/**
Fixup internal data so that EFI can be call in virtual mode.
@@ -35,8 +35,8 @@ STATIC UINT64 mNvStorageSize; VOID
EFIAPI
FlashFvbAddressChangeEvent (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
EfiConvertPointer (0x0, (VOID **)&mNvStorageBase);
@@ -60,8 +60,8 @@ FlashFvbAddressChangeEvent ( EFI_STATUS
EFIAPI
FlashFvbDxeGetAttributes (
- IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
- OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_FVB_ATTRIBUTES_2 *Attributes
)
{
ASSERT (Attributes != NULL);
@@ -103,8 +103,8 @@ FlashFvbDxeGetAttributes ( EFI_STATUS
EFIAPI
FlashFvbDxeSetAttributes (
- IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
- IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
)
{
return EFI_SUCCESS; // ignore for now
@@ -130,8 +130,8 @@ FlashFvbDxeSetAttributes ( EFI_STATUS
EFIAPI
FlashFvbDxeGetPhysicalAddress (
- IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
- OUT EFI_PHYSICAL_ADDRESS *Address
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ OUT EFI_PHYSICAL_ADDRESS *Address
)
{
ASSERT (Address != NULL);
@@ -170,13 +170,13 @@ FlashFvbDxeGetPhysicalAddress ( EFI_STATUS
EFIAPI
FlashFvbDxeGetBlockSize (
- IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
- IN EFI_LBA Lba,
- OUT UINTN *BlockSize,
- OUT UINTN *NumberOfBlocks
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ OUT UINTN *BlockSize,
+ OUT UINTN *NumberOfBlocks
)
{
- UINTN TotalNvStorageBlocks;
+ UINTN TotalNvStorageBlocks;
ASSERT (BlockSize != NULL);
ASSERT (NumberOfBlocks != NULL);
@@ -189,7 +189,7 @@ FlashFvbDxeGetBlockSize ( }
*NumberOfBlocks = TotalNvStorageBlocks - (UINTN)Lba;
- *BlockSize = mFlashBlockSize;
+ *BlockSize = mFlashBlockSize;
return EFI_SUCCESS;
}
@@ -244,14 +244,14 @@ FlashFvbDxeGetBlockSize ( EFI_STATUS
EFIAPI
FlashFvbDxeRead (
- IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
- IN EFI_LBA Lba,
- IN UINTN Offset,
- IN OUT UINTN *NumBytes,
- IN OUT UINT8 *Buffer
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN OUT UINT8 *Buffer
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (NumBytes != NULL);
ASSERT (Buffer != NULL);
@@ -335,14 +335,14 @@ FlashFvbDxeRead ( EFI_STATUS
EFIAPI
FlashFvbDxeWrite (
- IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
- IN EFI_LBA Lba,
- IN UINTN Offset,
- IN OUT UINTN *NumBytes,
- IN UINT8 *Buffer
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN EFI_LBA Lba,
+ IN UINTN Offset,
+ IN OUT UINTN *NumBytes,
+ IN UINT8 *Buffer
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (NumBytes != NULL);
ASSERT (Buffer != NULL);
@@ -418,14 +418,14 @@ FlashFvbDxeWrite ( EFI_STATUS
EFIAPI
FlashFvbDxeErase (
- IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
+ IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
...
)
{
- VA_LIST Args;
- EFI_LBA Start;
- UINTN Length;
- EFI_STATUS Status;
+ VA_LIST Args;
+ EFI_LBA Start;
+ UINTN Length;
+ EFI_STATUS Status;
Status = EFI_SUCCESS;
@@ -452,7 +452,7 @@ FlashFvbDxeErase ( return EFI_SUCCESS;
}
-EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL mFlashFvbProtocol = {
+EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL mFlashFvbProtocol = {
FlashFvbDxeGetAttributes,
FlashFvbDxeSetAttributes,
FlashFvbDxeGetPhysicalAddress,
@@ -465,20 +465,20 @@ EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL mFlashFvbProtocol = { EFI_STATUS
EFIAPI
FlashFvbDxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- EFI_HANDLE FvbHandle = NULL;
- EFI_EVENT VirtualAddressChangeEvent;
+ EFI_STATUS Status;
+ EFI_HANDLE FvbHandle = NULL;
+ EFI_EVENT VirtualAddressChangeEvent;
// Get NV store FV info
mFlashBlockSize = FixedPcdGet32 (PcdFvBlockSize);
- mNvStorageBase = PcdGet64 (PcdFlashNvStorageVariableBase64);
- mNvStorageSize = FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
- FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
- FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize);
+ mNvStorageBase = PcdGet64 (PcdFlashNvStorageVariableBase64);
+ mNvStorageSize = FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize);
DEBUG ((
DEBUG_INFO,
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.c index 87a1239b85..711f364be2 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/FlashPei/FlashPei.c @@ -28,24 +28,24 @@ EFI_STATUS
EFIAPI
FlashPeiEntryPoint (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- CHAR8 BuildUuid[PcdGetSize (PcdPlatformConfigUuid)];
- CHAR8 StoredUuid[PcdGetSize (PcdPlatformConfigUuid)];
- EFI_STATUS Status;
- UINTN FWNvRamStartOffset;
- UINT32 FWNvRamSize;
- UINTN NvRamAddress;
- UINT32 NvRamSize;
+ CHAR8 BuildUuid[PcdGetSize (PcdPlatformConfigUuid)];
+ CHAR8 StoredUuid[PcdGetSize (PcdPlatformConfigUuid)];
+ EFI_STATUS Status;
+ UINTN FWNvRamStartOffset;
+ UINT32 FWNvRamSize;
+ UINTN NvRamAddress;
+ UINT32 NvRamSize;
CopyMem ((VOID *)BuildUuid, PcdGetPtr (PcdPlatformConfigUuid), sizeof (BuildUuid));
NvRamAddress = PcdGet64 (PcdFlashNvStorageVariableBase64);
- NvRamSize = FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
- FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
- FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize);
+ NvRamSize = FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+ FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize);
DEBUG ((
DEBUG_INFO,
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoNvramLib.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoNvramLib.c index 056d006dec..f5c5479874 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoNvramLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoNvramLib.c @@ -13,11 +13,11 @@ #include "MemInfoScreen.h"
#include "NVParamDef.h"
-#define DDR_NVPARAM_ERRCTRL_DE_FIELD_SHIFT 0
-#define DDR_NVPARAM_ERRCTRL_DE_FIELD_MASK 0x1
+#define DDR_NVPARAM_ERRCTRL_DE_FIELD_SHIFT 0
+#define DDR_NVPARAM_ERRCTRL_DE_FIELD_MASK 0x1
-#define DDR_NVPARAM_ERRCTRL_FI_FIELD_SHIFT 1
-#define DDR_NVPARAM_ERRCTRL_FI_FIELD_MASK 0x2
+#define DDR_NVPARAM_ERRCTRL_FI_FIELD_SHIFT 1
+#define DDR_NVPARAM_ERRCTRL_FI_FIELD_MASK 0x2
/**
This is function collects meminfo from NVParam
@@ -29,11 +29,11 @@ **/
EFI_STATUS
MemInfoNvparamGet (
- OUT MEM_INFO_VARSTORE_DATA *VarStoreConfig
+ OUT MEM_INFO_VARSTORE_DATA *VarStoreConfig
)
{
- UINT32 Value;
- EFI_STATUS Status;
+ UINT32 Value;
+ EFI_STATUS Status;
ASSERT (VarStoreConfig != NULL);
@@ -122,10 +122,10 @@ MemInfoNvparamGet ( &Value
);
if (EFI_ERROR (Status)) {
- VarStoreConfig->FGRMode = DDR_DEFAULT_FGR_MODE;
+ VarStoreConfig->FGRMode = DDR_DEFAULT_FGR_MODE;
VarStoreConfig->Refresh2x = DDR_DEFAULT_REFRESH2X_MODE;
} else {
- VarStoreConfig->FGRMode = DDR_FGR_MODE_GET (Value);
+ VarStoreConfig->FGRMode = DDR_FGR_MODE_GET (Value);
VarStoreConfig->Refresh2x = DDR_REFRESH_2X_GET (Value);
}
@@ -154,11 +154,11 @@ MemInfoNvparamGet ( **/
EFI_STATUS
MemInfoNvparamSet (
- IN MEM_INFO_VARSTORE_DATA *VarStoreConfig
+ IN MEM_INFO_VARSTORE_DATA *VarStoreConfig
)
{
- EFI_STATUS Status;
- UINT32 Value, TmpValue, Value2, Update;
+ EFI_STATUS Status;
+ UINT32 Value, TmpValue, Value2, Update;
ASSERT (VarStoreConfig != NULL);
@@ -168,7 +168,7 @@ MemInfoNvparamSet ( NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
&Value
);
- if (EFI_ERROR (Status) || Value != VarStoreConfig->DDRSpeedSel) {
+ if (EFI_ERROR (Status) || (Value != VarStoreConfig->DDRSpeedSel)) {
Status = NVParamSet (
NV_SI_DDR_SPEED,
NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
@@ -215,7 +215,7 @@ MemInfoNvparamSet ( NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
&Value
);
- if (EFI_ERROR (Status) || Value != TmpValue ) {
+ if (EFI_ERROR (Status) || (Value != TmpValue)) {
Status = NVParamSet (
NV_SI_DDR_ERRCTRL,
NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
@@ -229,12 +229,12 @@ MemInfoNvparamSet ( /* Set slave's 32bit region */
TmpValue = VarStoreConfig->Slave32bit;
- Status = NVParamGet (
- NV_SI_DDR_SLAVE_32BIT_MEM_EN,
- NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
- &Value
- );
- if (EFI_ERROR (Status) || Value != TmpValue ) {
+ Status = NVParamGet (
+ NV_SI_DDR_SLAVE_32BIT_MEM_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status) || (Value != TmpValue)) {
if (TmpValue == 0) {
/* Default is disabled so just clear nvparam */
Status = NVParamClr (
@@ -249,6 +249,7 @@ MemInfoNvparamSet ( TmpValue
);
}
+
if (EFI_ERROR (Status)) {
return Status;
}
@@ -256,12 +257,12 @@ MemInfoNvparamSet ( /* Set Scrub patrol */
TmpValue = VarStoreConfig->ScrubPatrol;
- Status = NVParamGet (
- NV_SI_DDR_SCRUB_EN,
- NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
- &Value
- );
- if (EFI_ERROR (Status) || Value != TmpValue ) {
+ Status = NVParamGet (
+ NV_SI_DDR_SCRUB_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status) || (Value != TmpValue)) {
if (TmpValue == DDR_DEFAULT_SCRUB_PATROL_DURATION) {
Status = NVParamClr (
NV_SI_DDR_SCRUB_EN,
@@ -275,6 +276,7 @@ MemInfoNvparamSet ( TmpValue
);
}
+
if (EFI_ERROR (Status)) {
return Status;
}
@@ -282,12 +284,12 @@ MemInfoNvparamSet ( /* Demand Scrub */
TmpValue = VarStoreConfig->DemandScrub;
- Status = NVParamGet (
- NV_SI_DDR_WR_BACK_EN,
- NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
- &Value
- );
- if (EFI_ERROR (Status) || Value != TmpValue ) {
+ Status = NVParamGet (
+ NV_SI_DDR_WR_BACK_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU |NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status) || (Value != TmpValue)) {
if (TmpValue == DDR_DEFAULT_DEMAND_SCRUB) {
Status = NVParamClr (
NV_SI_DDR_WR_BACK_EN,
@@ -301,6 +303,7 @@ MemInfoNvparamSet ( TmpValue
);
}
+
if (EFI_ERROR (Status)) {
return Status;
}
@@ -308,12 +311,12 @@ MemInfoNvparamSet ( /* Write CRC */
TmpValue = VarStoreConfig->WriteCrc;
- Status = NVParamGet (
- NV_SI_DDR_CRC_MODE,
- NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
- &Value
- );
- if (EFI_ERROR (Status) || Value != TmpValue ) {
+ Status = NVParamGet (
+ NV_SI_DDR_CRC_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
+ if (EFI_ERROR (Status) || (Value != TmpValue)) {
if (TmpValue == DDR_DEFAULT_WRITE_CRC) {
Status = NVParamClr (
NV_SI_DDR_CRC_MODE,
@@ -327,32 +330,33 @@ MemInfoNvparamSet ( TmpValue
);
}
+
if (EFI_ERROR (Status)) {
return Status;
}
}
/* Write FGR/Refresh2X */
- Value = 0;
- Update = 0;
+ Value = 0;
+ Update = 0;
TmpValue = VarStoreConfig->FGRMode;
- Status = NVParamGet (
- NV_SI_DDR_REFRESH_GRANULARITY,
- NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
- &Value
- );
+ Status = NVParamGet (
+ NV_SI_DDR_REFRESH_GRANULARITY,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
Value2 = DDR_FGR_MODE_GET (Value);
- if ((EFI_ERROR (Status) && TmpValue != DDR_DEFAULT_FGR_MODE)
- || Value2 != TmpValue)
+ if ( (EFI_ERROR (Status) && (TmpValue != DDR_DEFAULT_FGR_MODE))
+ || (Value2 != TmpValue))
{
DDR_FGR_MODE_SET (Value, TmpValue);
Update = 1;
}
- Value2 = DDR_REFRESH_2X_GET (Value);
+ Value2 = DDR_REFRESH_2X_GET (Value);
TmpValue = VarStoreConfig->Refresh2x;
- if ((EFI_ERROR (Status) && TmpValue != DDR_DEFAULT_REFRESH2X_MODE)
- || Value2 != TmpValue)
+ if ( (EFI_ERROR (Status) && (TmpValue != DDR_DEFAULT_REFRESH2X_MODE))
+ || (Value2 != TmpValue))
{
DDR_REFRESH_2X_SET (Value, TmpValue);
Update = 1;
@@ -371,22 +375,22 @@ MemInfoNvparamSet ( }
/* Write NVDIMM-N Mode selection */
- Value = 0;
+ Value = 0;
TmpValue = VarStoreConfig->NvdimmModeSel;
- Status = NVParamGet (
- NV_SI_NVDIMM_MODE,
- NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
- &Value
- );
+ Status = NVParamGet (
+ NV_SI_NVDIMM_MODE,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &Value
+ );
Value2 = Value & DDR_NVDIMM_MODE_SEL_MASK; /* Mask out valid bit */
- if (EFI_ERROR (Status) || Value2 != TmpValue ) {
+ if (EFI_ERROR (Status) || (Value2 != TmpValue)) {
if (TmpValue == DDR_DEFAULT_NVDIMM_MODE_SEL) {
Status = NVParamClr (
NV_SI_NVDIMM_MODE,
NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC
);
} else {
- Value = TmpValue | DDR_NVDIMM_MODE_SEL_VALID_BIT; /* Add valid bit */
+ Value = TmpValue | DDR_NVDIMM_MODE_SEL_VALID_BIT; /* Add valid bit */
Status = NVParamSet (
NV_SI_NVDIMM_MODE,
NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
@@ -394,6 +398,7 @@ MemInfoNvparamSet ( Value
);
}
+
if (EFI_ERROR (Status)) {
return Status;
}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.c index 2161ac51d5..8fce65724f 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.c @@ -19,13 +19,13 @@ #include "MemInfoScreen.h"
-#define MAX_STRING_SIZE 64
-#define GB_SCALE_FACTOR (1024*1024*1024)
-#define MB_SCALE_FACTOR (1024*1024)
+#define MAX_STRING_SIZE 64
+#define GB_SCALE_FACTOR (1024*1024*1024)
+#define MB_SCALE_FACTOR (1024*1024)
-EFI_GUID gMemInfoFormSetGuid = MEM_INFO_FORM_SET_GUID;
+EFI_GUID gMemInfoFormSetGuid = MEM_INFO_FORM_SET_GUID;
-HII_VENDOR_DEVICE_PATH mHiiVendorDevicePath = {
+HII_VENDOR_DEVICE_PATH mHiiVendorDevicePath = {
{
{
HARDWARE_DEVICE_PATH,
@@ -47,8 +47,8 @@ HII_VENDOR_DEVICE_PATH mHiiVendorDevicePath = { }
};
-EFI_HANDLE DriverHandle = NULL;
-MEM_INFO_SCREEN_PRIVATE_DATA *mPrivateData = NULL;
+EFI_HANDLE DriverHandle = NULL;
+MEM_INFO_SCREEN_PRIVATE_DATA *mPrivateData = NULL;
/**
This function allows a caller to extract the current configuration for one
@@ -75,36 +75,36 @@ MEM_INFO_SCREEN_PRIVATE_DATA *mPrivateData = NULL; EFI_STATUS
EFIAPI
ExtractConfig (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN CONST EFI_STRING Request,
- OUT EFI_STRING *Progress,
- OUT EFI_STRING *Results
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Request,
+ OUT EFI_STRING *Progress,
+ OUT EFI_STRING *Results
)
{
- EFI_STATUS Status;
- UINTN BufferSize;
- MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- EFI_STRING ConfigRequest;
- EFI_STRING ConfigRequestHdr;
- UINTN Size;
- CHAR16 *StrPointer;
- BOOLEAN AllocatedRequest;
-
- if (Progress == NULL || Results == NULL) {
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STRING ConfigRequest;
+ EFI_STRING ConfigRequestHdr;
+ UINTN Size;
+ CHAR16 *StrPointer;
+ BOOLEAN AllocatedRequest;
+
+ if ((Progress == NULL) || (Results == NULL)) {
return EFI_INVALID_PARAMETER;
}
//
// Initialize the local variables.
//
- ConfigRequestHdr = NULL;
- ConfigRequest = NULL;
- Size = 0;
- *Progress = Request;
- AllocatedRequest = FALSE;
+ ConfigRequestHdr = NULL;
+ ConfigRequest = NULL;
+ Size = 0;
+ *Progress = Request;
+ AllocatedRequest = FALSE;
- PrivateData = MEM_INFO_SCREEN_PRIVATE_FROM_THIS (This);
+ PrivateData = MEM_INFO_SCREEN_PRIVATE_FROM_THIS (This);
HiiConfigRouting = PrivateData->HiiConfigRouting;
//
@@ -112,7 +112,7 @@ ExtractConfig ( // Try to get the current setting from variable.
//
BufferSize = sizeof (MEM_INFO_VARSTORE_DATA);
- Status = MemInfoNvparamGet (&PrivateData->VarStoreConfig);
+ Status = MemInfoNvparamGet (&PrivateData->VarStoreConfig);
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
@@ -127,8 +127,8 @@ ExtractConfig ( // followed by "&OFFSET=0&WIDTH=WWWWWWWWWWWWWWWW" followed by a Null-terminator
//
ConfigRequestHdr = HiiConstructConfigHdr (&gMemInfoFormSetGuid, MEM_INFO_VARSTORE_NAME, PrivateData->DriverHandle);
- Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);
- ConfigRequest = AllocateZeroPool (Size);
+ Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);
+ ConfigRequest = AllocateZeroPool (Size);
ASSERT (ConfigRequest != NULL);
AllocatedRequest = TRUE;
UnicodeSPrint (ConfigRequest, Size, L"%s&OFFSET=0&WIDTH=%016LX", ConfigRequestHdr, (UINT64)BufferSize);
@@ -159,9 +159,10 @@ ExtractConfig ( if (StrPointer == NULL) {
return EFI_INVALID_PARAMETER;
}
+
if (StrStr (StrPointer, L"&") == NULL) {
- Size = (StrLen (Request) + 32 + 1) * sizeof (CHAR16);
- ConfigRequest = AllocateZeroPool (Size);
+ Size = (StrLen (Request) + 32 + 1) * sizeof (CHAR16);
+ ConfigRequest = AllocateZeroPool (Size);
ASSERT (ConfigRequest != NULL);
AllocatedRequest = TRUE;
UnicodeSPrint (ConfigRequest, Size, L"%s&OFFSET=0&WIDTH=%016LX", Request, (UINT64)BufferSize);
@@ -201,6 +202,7 @@ ExtractConfig ( if (ConfigRequestHdr != NULL) {
FreePool (ConfigRequestHdr);
}
+
//
// Set Progress string to the original request string.
//
@@ -231,23 +233,23 @@ ExtractConfig ( EFI_STATUS
EFIAPI
RouteConfig (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN CONST EFI_STRING Configuration,
- OUT EFI_STRING *Progress
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Configuration,
+ OUT EFI_STRING *Progress
)
{
- EFI_STATUS Status;
- UINTN BufferSize;
- MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- if (Configuration == NULL || Progress == NULL) {
+ if ((Configuration == NULL) || (Progress == NULL)) {
return EFI_INVALID_PARAMETER;
}
- PrivateData = MEM_INFO_SCREEN_PRIVATE_FROM_THIS (This);
+ PrivateData = MEM_INFO_SCREEN_PRIVATE_FROM_THIS (This);
HiiConfigRouting = PrivateData->HiiConfigRouting;
- *Progress = Configuration;
+ *Progress = Configuration;
//
// Check routing data in <ConfigHdr>.
@@ -279,13 +281,13 @@ RouteConfig ( // Convert <ConfigResp> to buffer data by helper function ConfigToBlock()
//
BufferSize = sizeof (MEM_INFO_VARSTORE_DATA);
- Status = HiiConfigRouting->ConfigToBlock (
- HiiConfigRouting,
- Configuration,
- (UINT8 *)&PrivateData->VarStoreConfig,
- &BufferSize,
- Progress
- );
+ Status = HiiConfigRouting->ConfigToBlock (
+ HiiConfigRouting,
+ Configuration,
+ (UINT8 *)&PrivateData->VarStoreConfig,
+ &BufferSize,
+ Progress
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -318,99 +320,100 @@ RouteConfig ( EFI_STATUS
EFIAPI
DriverCallback (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN EFI_BROWSER_ACTION Action,
- IN EFI_QUESTION_ID QuestionId,
- IN UINT8 Type,
- IN EFI_IFR_TYPE_VALUE *Value,
- OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN EFI_BROWSER_ACTION Action,
+ IN EFI_QUESTION_ID QuestionId,
+ IN UINT8 Type,
+ IN EFI_IFR_TYPE_VALUE *Value,
+ OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
)
{
- if (((Value == NULL) && (Action != EFI_BROWSER_ACTION_FORM_OPEN)
- && (Action != EFI_BROWSER_ACTION_FORM_CLOSE))
- || (ActionRequest == NULL))
+ if ( ( (Value == NULL) && (Action != EFI_BROWSER_ACTION_FORM_OPEN)
+ && (Action != EFI_BROWSER_ACTION_FORM_CLOSE))
+ || (ActionRequest == NULL))
{
return EFI_INVALID_PARAMETER;
}
switch (Action) {
- case EFI_BROWSER_ACTION_FORM_OPEN:
- case EFI_BROWSER_ACTION_FORM_CLOSE:
- break;
-
- case EFI_BROWSER_ACTION_DEFAULT_STANDARD:
- case EFI_BROWSER_ACTION_DEFAULT_MANUFACTURING:
- {
- switch (QuestionId) {
- case MEM_INFO_DDR_SPEED_SEL_QUESTION_ID:
- //
- // DDR speed selection default to auto
- //
- Value->u32 = 0;
- break;
-
- case MEM_INFO_FORM_PERFORMANCE_ECC_QUESTION_ID:
- //
- // ECC mode default to be enabled
- //
- Value->u32 = EccAuto;
- break;
-
- case MEM_INFO_FORM_PERFORMANCE_ERR_CTRL_DE_QUESTION_ID:
- //
- // ErrCtrl_DE default to be enabled
- //
- Value->u32 = ErrCtlrDeEnable;
- break;
-
- case MEM_INFO_FORM_PERFORMANCE_ERR_CTRL_FI_QUESTION_ID:
- //
- // ErrCtrl_FI default to be enabled
- //
- Value->u32 = ErrCtlrDeEnable;
- break;
-
- case MEM_INFO_DDR_SLAVE_32BIT_QUESTION_ID:
- //
- // Slave's 32bit region to be disabled
- //
- Value->u32 = 0;
+ case EFI_BROWSER_ACTION_FORM_OPEN:
+ case EFI_BROWSER_ACTION_FORM_CLOSE:
break;
- case MEM_INFO_DDR_SCRUB_PATROL_QUESTION_ID:
- Value->u32 = DDR_DEFAULT_SCRUB_PATROL_DURATION;
- break;
-
- case MEM_INFO_DDR_DEMAND_SCRUB_QUESTION_ID:
- Value->u32 = DDR_DEFAULT_DEMAND_SCRUB;
- break;
-
- case MEM_INFO_DDR_WRITE_CRC_QUESTION_ID:
- Value->u32 = DDR_DEFAULT_WRITE_CRC;
- break;
-
- case MEM_INFO_FGR_MODE_QUESTION_ID:
- Value->u32 = DDR_DEFAULT_FGR_MODE;
- break;
-
- case MEM_INFO_REFRESH2X_MODE_QUESTION_ID:
- Value->u32 = DDR_DEFAULT_REFRESH2X_MODE;
- break;
+ case EFI_BROWSER_ACTION_DEFAULT_STANDARD:
+ case EFI_BROWSER_ACTION_DEFAULT_MANUFACTURING:
+ {
+ switch (QuestionId) {
+ case MEM_INFO_DDR_SPEED_SEL_QUESTION_ID:
+ //
+ // DDR speed selection default to auto
+ //
+ Value->u32 = 0;
+ break;
+
+ case MEM_INFO_FORM_PERFORMANCE_ECC_QUESTION_ID:
+ //
+ // ECC mode default to be enabled
+ //
+ Value->u32 = EccAuto;
+ break;
+
+ case MEM_INFO_FORM_PERFORMANCE_ERR_CTRL_DE_QUESTION_ID:
+ //
+ // ErrCtrl_DE default to be enabled
+ //
+ Value->u32 = ErrCtlrDeEnable;
+ break;
+
+ case MEM_INFO_FORM_PERFORMANCE_ERR_CTRL_FI_QUESTION_ID:
+ //
+ // ErrCtrl_FI default to be enabled
+ //
+ Value->u32 = ErrCtlrDeEnable;
+ break;
+
+ case MEM_INFO_DDR_SLAVE_32BIT_QUESTION_ID:
+ //
+ // Slave's 32bit region to be disabled
+ //
+ Value->u32 = 0;
+ break;
+
+ case MEM_INFO_DDR_SCRUB_PATROL_QUESTION_ID:
+ Value->u32 = DDR_DEFAULT_SCRUB_PATROL_DURATION;
+ break;
+
+ case MEM_INFO_DDR_DEMAND_SCRUB_QUESTION_ID:
+ Value->u32 = DDR_DEFAULT_DEMAND_SCRUB;
+ break;
+
+ case MEM_INFO_DDR_WRITE_CRC_QUESTION_ID:
+ Value->u32 = DDR_DEFAULT_WRITE_CRC;
+ break;
+
+ case MEM_INFO_FGR_MODE_QUESTION_ID:
+ Value->u32 = DDR_DEFAULT_FGR_MODE;
+ break;
+
+ case MEM_INFO_REFRESH2X_MODE_QUESTION_ID:
+ Value->u32 = DDR_DEFAULT_REFRESH2X_MODE;
+ break;
+
+ case MEM_INFO_FORM_NVDIMM_MODE_SEL_QUESTION_ID:
+ Value->u32 = DDR_DEFAULT_NVDIMM_MODE_SEL;
+ break;
+ }
- case MEM_INFO_FORM_NVDIMM_MODE_SEL_QUESTION_ID:
- Value->u32 = DDR_DEFAULT_NVDIMM_MODE_SEL;
break;
}
- }
- break;
- case EFI_BROWSER_ACTION_RETRIEVE:
- case EFI_BROWSER_ACTION_CHANGING:
- case EFI_BROWSER_ACTION_SUBMITTED:
- break;
+ case EFI_BROWSER_ACTION_RETRIEVE:
+ case EFI_BROWSER_ACTION_CHANGING:
+ case EFI_BROWSER_ACTION_SUBMITTED:
+ break;
- default:
- return EFI_UNSUPPORTED;
+ default:
+ return EFI_UNSUPPORTED;
}
return EFI_SUCCESS;
@@ -421,10 +424,10 @@ UpdateMemInfo ( PLATFORM_INFO_HOB *PlatformHob
)
{
- MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData = mPrivateData;
- CHAR16 Str[MAX_STRING_SIZE];
- EFI_HOB_RESOURCE_DESCRIPTOR *ResHob;
- UINT64 Size;
+ MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData = mPrivateData;
+ CHAR16 Str[MAX_STRING_SIZE];
+ EFI_HOB_RESOURCE_DESCRIPTOR *ResHob;
+ UINT64 Size;
/* Update Total memory */
UnicodeSPrint (Str, sizeof (Str), L"%d GB", PlatformHob->DramInfo.TotalSize / GB_SCALE_FACTOR);
@@ -436,14 +439,16 @@ UpdateMemInfo ( );
/* Update effective memory */
- Size = 0;
+ Size = 0;
ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR);
while (ResHob != NULL) {
if ((ResHob->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY)) {
Size += ResHob->ResourceLength;
}
- ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR,(VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
+
+ ResHob = (EFI_HOB_RESOURCE_DESCRIPTOR *)GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, (VOID *)((UINTN)ResHob + ResHob->Header.HobLength));
}
+
UnicodeSPrint (Str, sizeof (Str), L"%d GB", Size / GB_SCALE_FACTOR);
HiiSetString (
PrivateData->HiiHandle,
@@ -591,7 +596,7 @@ AddFgrModeSelection ( STRING_TOKEN (STR_MEM_INFO_FGR_MODE_HELP), // Question help text
EFI_IFR_FLAG_CALLBACK | EFI_IFR_FLAG_RESET_REQUIRED, // Question flag
EFI_IFR_NUMERIC_SIZE_4, // Data type of Question Value
- OptionsOpCodeHandle, // Option Opcode list
+ OptionsOpCodeHandle, // Option Opcode list
NULL // Default Opcode is NULl
);
@@ -606,11 +611,11 @@ AddDimmListInfo ( VOID *StartOpCodeHandle
)
{
- MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData = mPrivateData;
- CHAR16 Str[MAX_STRING_SIZE], Str1[MAX_STRING_SIZE];
- UINTN Count;
- PLATFORM_DIMM_INFO *DimmInfo;
- EFI_STRING_ID StringId;
+ MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData = mPrivateData;
+ CHAR16 Str[MAX_STRING_SIZE], Str1[MAX_STRING_SIZE];
+ UINTN Count;
+ PLATFORM_DIMM_INFO *DimmInfo;
+ EFI_STRING_ID StringId;
//
// Display DIMM list info
@@ -626,33 +631,34 @@ AddDimmListInfo ( for (Count = 0; Count < PlatformHob->DimmList.BoardDimmSlots; Count++) {
DimmInfo = &PlatformHob->DimmList.Dimm[Count].Info;
switch (DimmInfo->DimmType) {
- case UDIMM:
- UnicodeSPrint (Str, sizeof (Str), L"%s", L"UDIMM");
- break;
+ case UDIMM:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"UDIMM");
+ break;
- case RDIMM:
- UnicodeSPrint (Str, sizeof (Str), L"%s", L"RDIMM");
- break;
+ case RDIMM:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"RDIMM");
+ break;
- case SODIMM:
- UnicodeSPrint (Str, sizeof (Str), L"%s", L"SODIMM");
- break;
+ case SODIMM:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"SODIMM");
+ break;
- case LRDIMM:
- UnicodeSPrint (Str, sizeof (Str), L"%s", L"LRDIMM");
- break;
+ case LRDIMM:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"LRDIMM");
+ break;
- case RSODIMM:
- UnicodeSPrint (Str, sizeof (Str), L"%s", L"RSODIMM");
- break;
+ case RSODIMM:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"RSODIMM");
+ break;
- case NVRDIMM:
- UnicodeSPrint (Str, sizeof (Str), L"%s", L"NV-RDIMM");
- break;
+ case NVRDIMM:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"NV-RDIMM");
+ break;
- default:
- UnicodeSPrint (Str, sizeof (Str), L"Unknown Type");
+ default:
+ UnicodeSPrint (Str, sizeof (Str), L"Unknown Type");
}
+
if (DimmInfo->DimmStatus == DIMM_INSTALLED_OPERATIONAL) {
UnicodeSPrint (Str1, sizeof (Str1), L"Slot %2d: %d GB %s Installed&Operational", Count + 1, DimmInfo->DimmSize, Str);
} else if (DimmInfo->DimmStatus == DIMM_NOT_INSTALLED) {
@@ -714,14 +720,14 @@ MemInfoMainScreen ( //
// Create Hii Extend Label OpCode as the start opcode
//
- StartLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (StartOpCodeHandle, &gEfiIfrTianoGuid, NULL, sizeof (EFI_IFR_GUID_LABEL));
+ StartLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (StartOpCodeHandle, &gEfiIfrTianoGuid, NULL, sizeof (EFI_IFR_GUID_LABEL));
StartLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
StartLabel->Number = LABEL_UPDATE;
//
// Create Hii Extend Label OpCode as the end opcode
//
- EndLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (EndOpCodeHandle, &gEfiIfrTianoGuid, NULL, sizeof (EFI_IFR_GUID_LABEL));
+ EndLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (EndOpCodeHandle, &gEfiIfrTianoGuid, NULL, sizeof (EFI_IFR_GUID_LABEL));
EndLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
EndLabel->Number = LABEL_END;
@@ -824,16 +830,16 @@ MemInfoMainPerformanceScreen ( PLATFORM_INFO_HOB *PlatformHob
)
{
- EFI_STATUS Status;
- MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData = mPrivateData;
- VOID *StartOpCodeHandle;
- VOID *OptionsEccOpCodeHandle, *OptionsScrubOpCodeHandle;
- EFI_IFR_GUID_LABEL *StartLabel;
- VOID *EndOpCodeHandle;
- EFI_IFR_GUID_LABEL *EndLabel;
- EFI_STRING_ID StringId;
- CHAR16 Str[MAX_STRING_SIZE];
- UINTN Idx;
+ EFI_STATUS Status;
+ MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData = mPrivateData;
+ VOID *StartOpCodeHandle;
+ VOID *OptionsEccOpCodeHandle, *OptionsScrubOpCodeHandle;
+ EFI_IFR_GUID_LABEL *StartLabel;
+ VOID *EndOpCodeHandle;
+ EFI_IFR_GUID_LABEL *EndLabel;
+ EFI_STRING_ID StringId;
+ CHAR16 Str[MAX_STRING_SIZE];
+ UINTN Idx;
Status = EFI_SUCCESS;
@@ -849,14 +855,14 @@ MemInfoMainPerformanceScreen ( //
// Create Hii Extend Label OpCode as the start opcode
//
- StartLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (StartOpCodeHandle, &gEfiIfrTianoGuid, NULL, sizeof (EFI_IFR_GUID_LABEL));
+ StartLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (StartOpCodeHandle, &gEfiIfrTianoGuid, NULL, sizeof (EFI_IFR_GUID_LABEL));
StartLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
StartLabel->Number = LABEL_UPDATE;
//
// Create Hii Extend Label OpCode as the end opcode
//
- EndLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (EndOpCodeHandle, &gEfiIfrTianoGuid, NULL, sizeof (EFI_IFR_GUID_LABEL));
+ EndLabel = (EFI_IFR_GUID_LABEL *)HiiCreateGuidOpCode (EndOpCodeHandle, &gEfiIfrTianoGuid, NULL, sizeof (EFI_IFR_GUID_LABEL));
EndLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
EndLabel->Number = LABEL_END;
@@ -1048,16 +1054,16 @@ MemInfoMainNvdimmScreen ( PLATFORM_INFO_HOB *PlatformHob
)
{
- EFI_STATUS Status;
- MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData;
- VOID *StartOpCodeHandle;
- VOID *OptionsOpCodeHandle;
- EFI_IFR_GUID_LABEL *StartLabel;
- VOID *EndOpCodeHandle;
- EFI_IFR_GUID_LABEL *EndLabel;
- CHAR16 Str[MAX_STRING_SIZE];
+ EFI_STATUS Status;
+ MEM_INFO_SCREEN_PRIVATE_DATA *PrivateData;
+ VOID *StartOpCodeHandle;
+ VOID *OptionsOpCodeHandle;
+ EFI_IFR_GUID_LABEL *StartLabel;
+ VOID *EndOpCodeHandle;
+ EFI_IFR_GUID_LABEL *EndLabel;
+ CHAR16 Str[MAX_STRING_SIZE];
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
PrivateData = mPrivateData;
if (PlatformHob == NULL) {
@@ -1101,21 +1107,21 @@ MemInfoMainNvdimmScreen ( // Update Current NVDIMM-N Mode title Socket0
//
switch (PlatformHob->DramInfo.NvdimmMode[0]) {
- case 0:
- UnicodeSPrint (Str, sizeof (Str), L"%s", L"Non-NVDIMM");
- break;
+ case 0:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Non-NVDIMM");
+ break;
- case 1:
- UnicodeSPrint (Str, sizeof (Str), L"%s", L"Non-Hashed");
- break;
+ case 1:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Non-Hashed");
+ break;
- case 2:
- UnicodeSPrint (Str, sizeof (Str), L"%s", L"Hashed");
- break;
+ case 2:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Hashed");
+ break;
- default:
- UnicodeSPrint (Str, sizeof (Str), L"%s", L"Unknown");
- break;
+ default:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Unknown");
+ break;
}
HiiSetString (
@@ -1137,21 +1143,21 @@ MemInfoMainNvdimmScreen ( //
if (IsSlaveSocketActive ()) {
switch (PlatformHob->DramInfo.NvdimmMode[1]) {
- case 0:
- UnicodeSPrint (Str, sizeof (Str), L"%s", L"Non-NVDIMM");
- break;
+ case 0:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Non-NVDIMM");
+ break;
- case 1:
- UnicodeSPrint (Str, sizeof (Str), L"%s", L"Non-Hashed");
- break;
+ case 1:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Non-Hashed");
+ break;
- case 2:
- UnicodeSPrint (Str, sizeof (Str), L"%s", L"Hashed");
- break;
+ case 2:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Hashed");
+ break;
- default:
- UnicodeSPrint (Str, sizeof (Str), L"%s", L"Unknown");
- break;
+ default:
+ UnicodeSPrint (Str, sizeof (Str), L"%s", L"Unknown");
+ break;
}
HiiSetString (
@@ -1168,6 +1174,7 @@ MemInfoMainNvdimmScreen ( STRING_TOKEN (STR_MEM_INFO_NVDIMM_CUR_MODE_SK1_VALUE)
);
}
+
//
// Create Option OpCode to NVDIMM-N Mode Selection
//
@@ -1256,6 +1263,7 @@ MemInfoScreenSetup ( if (Hob == NULL) {
return EFI_DEVICE_ERROR;
}
+
PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
Status = MemInfoMainScreen (PlatformHob);
@@ -1278,15 +1286,15 @@ MemInfoScreenSetup ( EFI_STATUS
MemInfoScreenInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- EFI_HII_HANDLE HiiHandle;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- BOOLEAN ActionFlag;
- EFI_STRING ConfigRequestHdr;
+ EFI_STATUS Status;
+ EFI_HII_HANDLE HiiHandle;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ BOOLEAN ActionFlag;
+ EFI_STRING ConfigRequestHdr;
//
// Initialize driver private data
@@ -1299,8 +1307,8 @@ MemInfoScreenInitialize ( mPrivateData->Signature = MEM_INFO_SCREEN_PRIVATE_DATA_SIGNATURE;
mPrivateData->ConfigAccess.ExtractConfig = ExtractConfig;
- mPrivateData->ConfigAccess.RouteConfig = RouteConfig;
- mPrivateData->ConfigAccess.Callback = DriverCallback;
+ mPrivateData->ConfigAccess.RouteConfig = RouteConfig;
+ mPrivateData->ConfigAccess.Callback = DriverCallback;
//
// Locate ConfigRouting protocol
@@ -1309,6 +1317,7 @@ MemInfoScreenInitialize ( if (EFI_ERROR (Status)) {
return Status;
}
+
mPrivateData->HiiConfigRouting = HiiConfigRouting;
Status = gBS->InstallMultipleProtocolInterfaces (
@@ -1357,6 +1366,7 @@ MemInfoScreenInitialize ( MemInfoScreenUnload (ImageHandle);
return EFI_INVALID_PARAMETER;
}
+
FreePool (ConfigRequestHdr);
Status = MemInfoScreenSetup ();
@@ -1367,7 +1377,7 @@ MemInfoScreenInitialize ( EFI_STATUS
MemInfoScreenUnload (
- IN EFI_HANDLE ImageHandle
+ IN EFI_HANDLE ImageHandle
)
{
ASSERT (mPrivateData != NULL);
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.h index 9a06068902..fe80c40b5a 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.h +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreen.h @@ -25,14 +25,14 @@ // This data array is ready to be used as input of HiiAddPackages() to
// create a packagelist (which contains Form packages, String packages, etc).
//
-extern UINT8 MemInfoScreenVfrBin[];
+extern UINT8 MemInfoScreenVfrBin[];
//
// This is the generated String package data for all .UNI files.
// This data array is ready to be used as input of HiiAddPackages() to
// create a packagelist (which contains Form packages, String packages, etc).
//
-extern UINT8 MemInfoDxeStrings[];
+extern UINT8 MemInfoDxeStrings[];
typedef enum {
EccDisabled = 0,
@@ -54,72 +54,72 @@ typedef enum { ErrCtlrFiMax
} DDR_ERROR_CTRL_MODE_FI;
-#define MEM_INFO_DDR_SPEED_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, DDRSpeedSel)
-#define MEM_INFO_ECC_MODE_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, EccMode)
-#define MEM_INFO_ERR_CTRL_DE_MODE_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, ErrCtrl_DE)
-#define MEM_INFO_ERR_CTRL_FI_MODE_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, ErrCtrl_FI)
-#define MEM_INFO_ERR_SLAVE_32BIT_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, Slave32bit)
-#define MEM_INFO_DDR_SCRUB_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, ScrubPatrol)
-#define MEM_INFO_DDR_DEMAND_SCRUB_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, DemandScrub)
-#define MEM_INFO_DDR_WRITE_CRC_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, WriteCrc)
-#define MEM_INFO_FGR_MODE_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, FGRMode)
-#define MEM_INFO_REFRESH2X_MODE_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, Refresh2x)
-#define MEM_INFO_NVDIMM_MODE_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, NvdimmModeSel)
-
-#define MEM_INFO_SCREEN_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('M', 'E', 'M', 'i')
-
-#define MEM_INFO_DDR_SPEED_SEL_QUESTION_ID 0x8001
-#define MEM_INFO_FORM_PERFORMANCE_QUESTION_ID 0x8002
-#define MEM_INFO_FORM_PERFORMANCE_ECC_QUESTION_ID 0x8003
-#define MEM_INFO_FORM_PERFORMANCE_ERR_CTRL_DE_QUESTION_ID 0x8004
-#define MEM_INFO_FORM_PERFORMANCE_ERR_CTRL_FI_QUESTION_ID 0x8005
-#define MEM_INFO_DDR_SLAVE_32BIT_QUESTION_ID 0x8006
-#define MEM_INFO_DDR_SCRUB_PATROL_QUESTION_ID 0x8007
-#define MEM_INFO_DDR_DEMAND_SCRUB_QUESTION_ID 0x8008
-#define MEM_INFO_DDR_WRITE_CRC_QUESTION_ID 0x8009
-#define MEM_INFO_FGR_MODE_QUESTION_ID 0x800A
-#define MEM_INFO_REFRESH2X_MODE_QUESTION_ID 0x800B
-#define MEM_INFO_FORM_NVDIMM_QUESTION_ID 0x800C
-#define MEM_INFO_FORM_NVDIMM_MODE_SEL_QUESTION_ID 0x800D
-
-#define MAX_NUMBER_OF_HOURS_IN_A_DAY 24
-
-#define DDR_DEFAULT_SCRUB_PATROL_DURATION 24
-#define DDR_DEFAULT_DEMAND_SCRUB 1
-#define DDR_DEFAULT_WRITE_CRC 0
-#define DDR_DEFAULT_FGR_MODE 0
-#define DDR_DEFAULT_REFRESH2X_MODE 0
-#define DDR_DEFAULT_NVDIMM_MODE_SEL 3
-
-#define DDR_FGR_MODE_GET(Value) ((Value) & 0x3) /* Bit 0, 1 */
-#define DDR_FGR_MODE_SET(Dst, Src) do { Dst = (((Dst) & ~0x3) | ((Src) & 0x3)); } while (0)
-
-#define DDR_REFRESH_2X_GET(Value) ((Value) & 0x10000) >> 16 /* Bit 16 only */
-#define DDR_REFRESH_2X_SET(Dst, Src) do { Dst = (((Dst) & ~0x10000) | ((Src) & 0x1) << 16); } while (0)
-
-#define DDR_NVDIMM_MODE_SEL_MASK 0x7FFFFFFF
-#define DDR_NVDIMM_MODE_SEL_VALID_BIT BIT31
+#define MEM_INFO_DDR_SPEED_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, DDRSpeedSel)
+#define MEM_INFO_ECC_MODE_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, EccMode)
+#define MEM_INFO_ERR_CTRL_DE_MODE_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, ErrCtrl_DE)
+#define MEM_INFO_ERR_CTRL_FI_MODE_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, ErrCtrl_FI)
+#define MEM_INFO_ERR_SLAVE_32BIT_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, Slave32bit)
+#define MEM_INFO_DDR_SCRUB_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, ScrubPatrol)
+#define MEM_INFO_DDR_DEMAND_SCRUB_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, DemandScrub)
+#define MEM_INFO_DDR_WRITE_CRC_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, WriteCrc)
+#define MEM_INFO_FGR_MODE_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, FGRMode)
+#define MEM_INFO_REFRESH2X_MODE_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, Refresh2x)
+#define MEM_INFO_NVDIMM_MODE_SEL_OFFSET OFFSET_OF (MEM_INFO_VARSTORE_DATA, NvdimmModeSel)
+
+#define MEM_INFO_SCREEN_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('M', 'E', 'M', 'i')
+
+#define MEM_INFO_DDR_SPEED_SEL_QUESTION_ID 0x8001
+#define MEM_INFO_FORM_PERFORMANCE_QUESTION_ID 0x8002
+#define MEM_INFO_FORM_PERFORMANCE_ECC_QUESTION_ID 0x8003
+#define MEM_INFO_FORM_PERFORMANCE_ERR_CTRL_DE_QUESTION_ID 0x8004
+#define MEM_INFO_FORM_PERFORMANCE_ERR_CTRL_FI_QUESTION_ID 0x8005
+#define MEM_INFO_DDR_SLAVE_32BIT_QUESTION_ID 0x8006
+#define MEM_INFO_DDR_SCRUB_PATROL_QUESTION_ID 0x8007
+#define MEM_INFO_DDR_DEMAND_SCRUB_QUESTION_ID 0x8008
+#define MEM_INFO_DDR_WRITE_CRC_QUESTION_ID 0x8009
+#define MEM_INFO_FGR_MODE_QUESTION_ID 0x800A
+#define MEM_INFO_REFRESH2X_MODE_QUESTION_ID 0x800B
+#define MEM_INFO_FORM_NVDIMM_QUESTION_ID 0x800C
+#define MEM_INFO_FORM_NVDIMM_MODE_SEL_QUESTION_ID 0x800D
+
+#define MAX_NUMBER_OF_HOURS_IN_A_DAY 24
+
+#define DDR_DEFAULT_SCRUB_PATROL_DURATION 24
+#define DDR_DEFAULT_DEMAND_SCRUB 1
+#define DDR_DEFAULT_WRITE_CRC 0
+#define DDR_DEFAULT_FGR_MODE 0
+#define DDR_DEFAULT_REFRESH2X_MODE 0
+#define DDR_DEFAULT_NVDIMM_MODE_SEL 3
+
+#define DDR_FGR_MODE_GET(Value) ((Value) & 0x3) /* Bit 0, 1 */
+#define DDR_FGR_MODE_SET(Dst, Src) do { Dst = (((Dst) & ~0x3) | ((Src) & 0x3)); } while (0)
+
+#define DDR_REFRESH_2X_GET(Value) ((Value) & 0x10000) >> 16 /* Bit 16 only */
+#define DDR_REFRESH_2X_SET(Dst, Src) do { Dst = (((Dst) & ~0x10000) | ((Src) & 0x1) << 16); } while (0)
+
+#define DDR_NVDIMM_MODE_SEL_MASK 0x7FFFFFFF
+#define DDR_NVDIMM_MODE_SEL_VALID_BIT BIT31
typedef struct {
- UINTN Signature;
+ UINTN Signature;
- EFI_HANDLE DriverHandle;
- EFI_HII_HANDLE HiiHandle;
- MEM_INFO_VARSTORE_DATA VarStoreConfig;
+ EFI_HANDLE DriverHandle;
+ EFI_HII_HANDLE HiiHandle;
+ MEM_INFO_VARSTORE_DATA VarStoreConfig;
//
// Consumed protocol
//
- EFI_HII_DATABASE_PROTOCOL *HiiDatabase;
- EFI_HII_STRING_PROTOCOL *HiiString;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *HiiKeywordHandler;
- EFI_FORM_BROWSER2_PROTOCOL *FormBrowser2;
+ EFI_HII_DATABASE_PROTOCOL *HiiDatabase;
+ EFI_HII_STRING_PROTOCOL *HiiString;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *HiiKeywordHandler;
+ EFI_FORM_BROWSER2_PROTOCOL *FormBrowser2;
//
// Produced protocol
//
- EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
+ EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
} MEM_INFO_SCREEN_PRIVATE_DATA;
#define MEM_INFO_SCREEN_PRIVATE_FROM_THIS(a) CR (a, MEM_INFO_SCREEN_PRIVATE_DATA, ConfigAccess, MEM_INFO_SCREEN_PRIVATE_DATA_SIGNATURE)
@@ -130,31 +130,31 @@ typedef struct { /// HII specific Vendor Device Path definition.
///
typedef struct {
- VENDOR_DEVICE_PATH VendorDevicePath;
- EFI_DEVICE_PATH_PROTOCOL End;
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
} HII_VENDOR_DEVICE_PATH;
#pragma pack()
EFI_STATUS
MemInfoScreenInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
);
EFI_STATUS
MemInfoScreenUnload (
- IN EFI_HANDLE ImageHandle
+ IN EFI_HANDLE ImageHandle
);
EFI_STATUS
MemInfoNvparamGet (
- OUT MEM_INFO_VARSTORE_DATA *VarStoreConfig
+ OUT MEM_INFO_VARSTORE_DATA *VarStoreConfig
);
EFI_STATUS
MemInfoNvparamSet (
- IN MEM_INFO_VARSTORE_DATA *VarStoreConfig
+ IN MEM_INFO_VARSTORE_DATA *VarStoreConfig
);
#endif /* MEM_INFO_SCREEN_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenNVDataStruct.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenNVDataStruct.h index 75960c3678..c68e844106 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenNVDataStruct.h +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/MemInfoDxe/MemInfoScreenNVDataStruct.h @@ -9,13 +9,13 @@ #ifndef MEM_INFO_SCREEN_NV_DATA_STRUCT_H_
#define MEM_INFO_SCREEN_NV_DATA_STRUCT_H_
-#define MEM_INFO_VARSTORE_NAME L"MemInfoIfrNVData"
-#define MEM_INFO_VARSTORE_ID 0x1234
-#define MEM_INFO_FORM_ID 0x1235
-#define MEM_INFO_FORM_PERFORMANCE_ID 0x1236
-#define MEM_INFO_FORM_NVDIMM_ID 0x1237
-#define MEM_INFO_FORM_SET_GUID { 0xd58338ee, 0xe9f7, 0x4d8d, { 0xa7, 0x08, 0xdf, 0xb2, 0xc6, 0x66, 0x1d, 0x61 } }
-#define MEM_INFO_FORM_SET_PERFORMANCE_GUID { 0x4a072c78, 0x42f9, 0x11ea, { 0xb7, 0x7f, 0x2e, 0x28, 0xce, 0x88, 0x12, 0x62 } }
+#define MEM_INFO_VARSTORE_NAME L"MemInfoIfrNVData"
+#define MEM_INFO_VARSTORE_ID 0x1234
+#define MEM_INFO_FORM_ID 0x1235
+#define MEM_INFO_FORM_PERFORMANCE_ID 0x1236
+#define MEM_INFO_FORM_NVDIMM_ID 0x1237
+#define MEM_INFO_FORM_SET_GUID { 0xd58338ee, 0xe9f7, 0x4d8d, { 0xa7, 0x08, 0xdf, 0xb2, 0xc6, 0x66, 0x1d, 0x61 } }
+#define MEM_INFO_FORM_SET_PERFORMANCE_GUID { 0x4a072c78, 0x42f9, 0x11ea, { 0xb7, 0x7f, 0x2e, 0x28, 0xce, 0x88, 0x12, 0x62 } }
#pragma pack(1)
@@ -23,24 +23,24 @@ // NV data structure definition
//
typedef struct {
- UINT32 DDRSpeedSel;
- UINT32 EccMode;
- UINT32 ErrCtrl_DE;
- UINT32 ErrCtrl_FI;
- UINT32 Slave32bit;
- UINT32 ScrubPatrol;
- UINT32 DemandScrub;
- UINT32 WriteCrc;
- UINT32 FGRMode;
- UINT32 Refresh2x;
- UINT32 NvdimmModeSel;
+ UINT32 DDRSpeedSel;
+ UINT32 EccMode;
+ UINT32 ErrCtrl_DE;
+ UINT32 ErrCtrl_FI;
+ UINT32 Slave32bit;
+ UINT32 ScrubPatrol;
+ UINT32 DemandScrub;
+ UINT32 WriteCrc;
+ UINT32 FGRMode;
+ UINT32 Refresh2x;
+ UINT32 NvdimmModeSel;
} MEM_INFO_VARSTORE_DATA;
//
// Labels definition
//
-#define LABEL_UPDATE 0x2223
-#define LABEL_END 0x2224
+#define LABEL_UPDATE 0x2223
+#define LABEL_END 0x2224
#pragma pack()
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c index bf4395d48d..f0b19f4f6a 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/PcieInitPei.c @@ -23,27 +23,27 @@ #include "RootComplexNVParam.h"
-#define TCU_OFFSET 0
-#define SNPSRAM_OFFSET 0x9000
-#define HB_CSR_OFFSET 0x01000000
-#define PCIE0_CSR_OFFSET 0x01010000
-#define SERDES_CSR_OFFSET 0x01200000
-#define MMCONFIG_OFFSET 0x10000000
-
-#define PCIE_CSR_SIZE 0x10000
-
-STATIC AC01_ROOT_COMPLEX mRootComplexList[AC01_PCIE_MAX_ROOT_COMPLEX];
-STATIC UINT64 mCsrBase[AC01_PCIE_MAX_ROOT_COMPLEX] = { AC01_PCIE_CSR_BASE_LIST };
-STATIC UINT64 mMmio32Base[AC01_PCIE_MAX_ROOT_COMPLEX] = { AC01_PCIE_MMIO32_BASE_LIST };
-STATIC UINT64 mMmio32Base1P[AC01_PCIE_MAX_ROOT_COMPLEX] = { AC01_PCIE_MMIO32_BASE_1P_LIST };
-STATIC UINT64 mMmio32Size[AC01_PCIE_MAX_ROOT_COMPLEX] = { AC01_PCIE_MMIO32_SIZE_LIST };
-STATIC UINT64 mMmio32Size1P[AC01_PCIE_MAX_ROOT_COMPLEX] = { AC01_PCIE_MMIO32_SIZE_1P_LIST };
-STATIC UINT64 mMmioBase[AC01_PCIE_MAX_ROOT_COMPLEX] = { AC01_PCIE_MMIO_BASE_LIST };
-STATIC UINT64 mMmioSize[AC01_PCIE_MAX_ROOT_COMPLEX] = { AC01_PCIE_MMIO_SIZE_LIST };
+#define TCU_OFFSET 0
+#define SNPSRAM_OFFSET 0x9000
+#define HB_CSR_OFFSET 0x01000000
+#define PCIE0_CSR_OFFSET 0x01010000
+#define SERDES_CSR_OFFSET 0x01200000
+#define MMCONFIG_OFFSET 0x10000000
+
+#define PCIE_CSR_SIZE 0x10000
+
+STATIC AC01_ROOT_COMPLEX mRootComplexList[AC01_PCIE_MAX_ROOT_COMPLEX];
+STATIC UINT64 mCsrBase[AC01_PCIE_MAX_ROOT_COMPLEX] = { AC01_PCIE_CSR_BASE_LIST };
+STATIC UINT64 mMmio32Base[AC01_PCIE_MAX_ROOT_COMPLEX] = { AC01_PCIE_MMIO32_BASE_LIST };
+STATIC UINT64 mMmio32Base1P[AC01_PCIE_MAX_ROOT_COMPLEX] = { AC01_PCIE_MMIO32_BASE_1P_LIST };
+STATIC UINT64 mMmio32Size[AC01_PCIE_MAX_ROOT_COMPLEX] = { AC01_PCIE_MMIO32_SIZE_LIST };
+STATIC UINT64 mMmio32Size1P[AC01_PCIE_MAX_ROOT_COMPLEX] = { AC01_PCIE_MMIO32_SIZE_1P_LIST };
+STATIC UINT64 mMmioBase[AC01_PCIE_MAX_ROOT_COMPLEX] = { AC01_PCIE_MMIO_BASE_LIST };
+STATIC UINT64 mMmioSize[AC01_PCIE_MAX_ROOT_COMPLEX] = { AC01_PCIE_MMIO_SIZE_LIST };
AC01_ROOT_COMPLEX_TYPE
GetRootComplexType (
- UINT8 RootComplexId
+ UINT8 RootComplexId
)
{
if (IsAc01Processor ()) {
@@ -55,40 +55,40 @@ GetRootComplexType ( VOID
ConfigureRootComplex (
- BOOLEAN IsConfigFound,
- ROOT_COMPLEX_CONFIG_VARSTORE_DATA RootComplexConfig
+ BOOLEAN IsConfigFound,
+ ROOT_COMPLEX_CONFIG_VARSTORE_DATA RootComplexConfig
)
{
- UINT8 RCIndex;
- UINT8 PcieIndex;
- AC01_ROOT_COMPLEX *RootComplex;
+ UINT8 RCIndex;
+ UINT8 PcieIndex;
+ AC01_ROOT_COMPLEX *RootComplex;
for (RCIndex = 0; RCIndex < AC01_PCIE_MAX_ROOT_COMPLEX; RCIndex++) {
- RootComplex = &mRootComplexList[RCIndex];
- RootComplex->Active = IsConfigFound ? RootComplexConfig.RCStatus[RCIndex] : TRUE;
- RootComplex->DevMapLow = IsConfigFound ? RootComplexConfig.RCBifurcationLow[RCIndex] : 0;
- RootComplex->DevMapHigh = IsConfigFound ? RootComplexConfig.RCBifurcationHigh[RCIndex] : 0;
- RootComplex->Socket = RCIndex / AC01_PCIE_MAX_RCS_PER_SOCKET;
- RootComplex->ID = RCIndex % AC01_PCIE_MAX_RCS_PER_SOCKET;
- RootComplex->CsrBase = mCsrBase[RCIndex];
- RootComplex->TcuBase = RootComplex->CsrBase + TCU_OFFSET;
- RootComplex->HostBridgeBase = RootComplex->CsrBase + HB_CSR_OFFSET;
- RootComplex->SerdesBase = RootComplex->CsrBase + SERDES_CSR_OFFSET;
- RootComplex->MmcfgBase = RootComplex->CsrBase + MMCONFIG_OFFSET;
- RootComplex->MmioBase = mMmioBase[RCIndex];
- RootComplex->MmioSize = mMmioSize[RCIndex];
- RootComplex->Mmio32Base = mMmio32Base[RCIndex];
- RootComplex->Mmio32Size = mMmio32Size[RCIndex];
- RootComplex->Type = GetRootComplexType (RootComplex->ID);
+ RootComplex = &mRootComplexList[RCIndex];
+ RootComplex->Active = IsConfigFound ? RootComplexConfig.RCStatus[RCIndex] : TRUE;
+ RootComplex->DevMapLow = IsConfigFound ? RootComplexConfig.RCBifurcationLow[RCIndex] : 0;
+ RootComplex->DevMapHigh = IsConfigFound ? RootComplexConfig.RCBifurcationHigh[RCIndex] : 0;
+ RootComplex->Socket = RCIndex / AC01_PCIE_MAX_RCS_PER_SOCKET;
+ RootComplex->ID = RCIndex % AC01_PCIE_MAX_RCS_PER_SOCKET;
+ RootComplex->CsrBase = mCsrBase[RCIndex];
+ RootComplex->TcuBase = RootComplex->CsrBase + TCU_OFFSET;
+ RootComplex->HostBridgeBase = RootComplex->CsrBase + HB_CSR_OFFSET;
+ RootComplex->SerdesBase = RootComplex->CsrBase + SERDES_CSR_OFFSET;
+ RootComplex->MmcfgBase = RootComplex->CsrBase + MMCONFIG_OFFSET;
+ RootComplex->MmioBase = mMmioBase[RCIndex];
+ RootComplex->MmioSize = mMmioSize[RCIndex];
+ RootComplex->Mmio32Base = mMmio32Base[RCIndex];
+ RootComplex->Mmio32Size = mMmio32Size[RCIndex];
+ RootComplex->Type = GetRootComplexType (RootComplex->ID);
RootComplex->MaxPcieController = (RootComplex->Type == RootComplexTypeB)
? MaxPcieControllerOfRootComplexB : MaxPcieControllerOfRootComplexA;
RootComplex->Logical = BoardPcieGetSegmentNumber (RootComplex);
for (PcieIndex = 0; PcieIndex < RootComplex->MaxPcieController; PcieIndex++) {
- RootComplex->Pcie[PcieIndex].ID = PcieIndex;
- RootComplex->Pcie[PcieIndex].CsrBase = RootComplex->CsrBase + PCIE0_CSR_OFFSET + PcieIndex * PCIE_CSR_SIZE;
+ RootComplex->Pcie[PcieIndex].ID = PcieIndex;
+ RootComplex->Pcie[PcieIndex].CsrBase = RootComplex->CsrBase + PCIE0_CSR_OFFSET + PcieIndex * PCIE_CSR_SIZE;
RootComplex->Pcie[PcieIndex].SnpsRamBase = RootComplex->Pcie[PcieIndex].CsrBase + SNPSRAM_OFFSET;
- RootComplex->Pcie[PcieIndex].DevNum = PcieIndex + 1;
+ RootComplex->Pcie[PcieIndex].DevNum = PcieIndex + 1;
}
ParseRootComplexNVParamData (RootComplex);
@@ -124,11 +124,11 @@ BuildRootComplexData ( VOID
)
{
- BOOLEAN IsConfigFound;
- EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;
- EFI_STATUS Status;
- ROOT_COMPLEX_CONFIG_VARSTORE_DATA RootComplexConfig;
- UINTN DataSize;
+ BOOLEAN IsConfigFound;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;
+ EFI_STATUS Status;
+ ROOT_COMPLEX_CONFIG_VARSTORE_DATA RootComplexConfig;
+ UINTN DataSize;
IsConfigFound = FALSE;
ZeroMem ((VOID *)&RootComplexConfig, sizeof (ROOT_COMPLEX_CONFIG_VARSTORE_DATA));
@@ -144,14 +144,14 @@ BuildRootComplexData ( );
if (!EFI_ERROR (Status)) {
DataSize = sizeof (RootComplexConfig);
- Status = VariablePpi->GetVariable (
- VariablePpi,
- ROOT_COMPLEX_CONFIG_VARSTORE_NAME,
- &gRootComplexConfigFormSetGuid,
- NULL,
- &DataSize,
- &RootComplexConfig
- );
+ Status = VariablePpi->GetVariable (
+ VariablePpi,
+ ROOT_COMPLEX_CONFIG_VARSTORE_NAME,
+ &gRootComplexConfigFormSetGuid,
+ NULL,
+ &DataSize,
+ &RootComplexConfig
+ );
if (!EFI_ERROR (Status)) {
IsConfigFound = TRUE;
}
@@ -176,13 +176,13 @@ BuildRootComplexData ( EFI_STATUS
EFIAPI
PcieInitEntry (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- AC01_ROOT_COMPLEX *RootComplex;
- EFI_STATUS Status;
- UINT8 Index;
+ AC01_ROOT_COMPLEX *RootComplex;
+ EFI_STATUS Status;
+ UINT8 Index;
BuildRootComplexData ();
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c index 199929bfdb..1573313d45 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.c @@ -64,10 +64,10 @@ typedef enum { STATIC
BOOLEAN
IsEmptyRC (
- AC01_ROOT_COMPLEX *RootComplex
+ AC01_ROOT_COMPLEX *RootComplex
)
{
- UINT8 Idx;
+ UINT8 Idx;
for (Idx = PcieController0; Idx < MaxPcieController; Idx++) {
if (RootComplex->Pcie[Idx].Active) {
@@ -80,115 +80,120 @@ IsEmptyRC ( VOID
SetRootComplexBifurcation (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN UINT8 RPStart,
- IN DEV_MAP_MODE DevMap
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN UINT8 RPStart,
+ IN DEV_MAP_MODE DevMap
)
{
- UINT8 MaxWidth;
+ UINT8 MaxWidth;
- if (RPStart != PcieController0 && RPStart != PcieController4) {
+ if ((RPStart != PcieController0) && (RPStart != PcieController4)) {
return;
}
- if (RootComplex->Type != RootComplexTypeB && RPStart == PcieController4) {
+ if ((RootComplex->Type != RootComplexTypeB) && (RPStart == PcieController4)) {
return;
}
- if (RootComplex->Type == RootComplexTypeA && RootComplex->Pcie[RPStart].MaxWidth == LINK_WIDTH_X16) {
+ if ((RootComplex->Type == RootComplexTypeA) && (RootComplex->Pcie[RPStart].MaxWidth == LINK_WIDTH_X16)) {
RootComplex->Pcie[RPStart + 1].MaxWidth = LINK_WIDTH_X4;
RootComplex->Pcie[RPStart + 2].MaxWidth = LINK_WIDTH_X8;
RootComplex->Pcie[RPStart + 3].MaxWidth = LINK_WIDTH_X4;
}
- if (RootComplex->Type == RootComplexTypeB && RootComplex->Pcie[RPStart].MaxWidth == LINK_WIDTH_X8) {
+ if ((RootComplex->Type == RootComplexTypeB) && (RootComplex->Pcie[RPStart].MaxWidth == LINK_WIDTH_X8)) {
RootComplex->Pcie[RPStart + 1].MaxWidth = LINK_WIDTH_X2;
RootComplex->Pcie[RPStart + 2].MaxWidth = LINK_WIDTH_X4;
RootComplex->Pcie[RPStart + 3].MaxWidth = LINK_WIDTH_X2;
}
switch (DevMap) {
- case DevMapMode2:
- MaxWidth = (RootComplex->Type == RootComplexTypeA) ? LINK_WIDTH_X8 : LINK_WIDTH_X4;
- RootComplex->Pcie[RPStart].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart], MaxWidth);
- RootComplex->Pcie[RPStart + 1].Active = FALSE;
- RootComplex->Pcie[RPStart + 2].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart + 2], MaxWidth);
- RootComplex->Pcie[RPStart + 2].Active = TRUE;
- RootComplex->Pcie[RPStart + 3].Active = FALSE;
- break;
-
- case DevMapMode3:
- MaxWidth = (RootComplex->Type == RootComplexTypeA) ? LINK_WIDTH_X8 : LINK_WIDTH_X4;
- RootComplex->Pcie[RPStart].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart], MaxWidth);
- RootComplex->Pcie[RPStart + 1].Active = FALSE;
- MaxWidth = (RootComplex->Type == RootComplexTypeA) ? LINK_WIDTH_X4 : LINK_WIDTH_X2;
- RootComplex->Pcie[RPStart + 2].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart + 2], MaxWidth);
- RootComplex->Pcie[RPStart + 2].Active = TRUE;
- RootComplex->Pcie[RPStart + 3].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart + 3], MaxWidth);
- RootComplex->Pcie[RPStart + 3].Active = TRUE;
- break;
-
- case DevMapModeAuto:
- case DevMapMode4:
- MaxWidth = (RootComplex->Type == RootComplexTypeA) ? LINK_WIDTH_X4 : LINK_WIDTH_X2;
- RootComplex->Pcie[RPStart].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart], MaxWidth);
- RootComplex->Pcie[RPStart + 1].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart + 1], MaxWidth);
- RootComplex->Pcie[RPStart + 1].Active = TRUE;
- RootComplex->Pcie[RPStart + 2].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart + 2], MaxWidth);
- RootComplex->Pcie[RPStart + 2].Active = TRUE;
- RootComplex->Pcie[RPStart + 3].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart + 3], MaxWidth);
- RootComplex->Pcie[RPStart + 3].Active = TRUE;
- break;
-
- case DevMapMode1:
- default:
- MaxWidth = (RootComplex->Type == RootComplexTypeA) ? LINK_WIDTH_X16 : LINK_WIDTH_X8;
- RootComplex->Pcie[RPStart].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart], MaxWidth);
- RootComplex->Pcie[RPStart + 1].Active = FALSE;
- RootComplex->Pcie[RPStart + 2].Active = FALSE;
- RootComplex->Pcie[RPStart + 3].Active = FALSE;
- break;
+ case DevMapMode2:
+ MaxWidth = (RootComplex->Type == RootComplexTypeA) ? LINK_WIDTH_X8 : LINK_WIDTH_X4;
+ RootComplex->Pcie[RPStart].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart], MaxWidth);
+ RootComplex->Pcie[RPStart + 1].Active = FALSE;
+ RootComplex->Pcie[RPStart + 2].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart + 2], MaxWidth);
+ RootComplex->Pcie[RPStart + 2].Active = TRUE;
+ RootComplex->Pcie[RPStart + 3].Active = FALSE;
+ break;
+
+ case DevMapMode3:
+ MaxWidth = (RootComplex->Type == RootComplexTypeA) ? LINK_WIDTH_X8 : LINK_WIDTH_X4;
+ RootComplex->Pcie[RPStart].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart], MaxWidth);
+ RootComplex->Pcie[RPStart + 1].Active = FALSE;
+ MaxWidth = (RootComplex->Type == RootComplexTypeA) ? LINK_WIDTH_X4 : LINK_WIDTH_X2;
+ RootComplex->Pcie[RPStart + 2].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart + 2], MaxWidth);
+ RootComplex->Pcie[RPStart + 2].Active = TRUE;
+ RootComplex->Pcie[RPStart + 3].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart + 3], MaxWidth);
+ RootComplex->Pcie[RPStart + 3].Active = TRUE;
+ break;
+
+ case DevMapModeAuto:
+ case DevMapMode4:
+ MaxWidth = (RootComplex->Type == RootComplexTypeA) ? LINK_WIDTH_X4 : LINK_WIDTH_X2;
+ RootComplex->Pcie[RPStart].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart], MaxWidth);
+ RootComplex->Pcie[RPStart + 1].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart + 1], MaxWidth);
+ RootComplex->Pcie[RPStart + 1].Active = TRUE;
+ RootComplex->Pcie[RPStart + 2].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart + 2], MaxWidth);
+ RootComplex->Pcie[RPStart + 2].Active = TRUE;
+ RootComplex->Pcie[RPStart + 3].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart + 3], MaxWidth);
+ RootComplex->Pcie[RPStart + 3].Active = TRUE;
+ break;
+
+ case DevMapMode1:
+ default:
+ MaxWidth = (RootComplex->Type == RootComplexTypeA) ? LINK_WIDTH_X16 : LINK_WIDTH_X8;
+ RootComplex->Pcie[RPStart].MaxWidth = PCIE_GET_MAX_WIDTH (RootComplex->Pcie[RPStart], MaxWidth);
+ RootComplex->Pcie[RPStart + 1].Active = FALSE;
+ RootComplex->Pcie[RPStart + 2].Active = FALSE;
+ RootComplex->Pcie[RPStart + 3].Active = FALSE;
+ break;
}
}
DEV_MAP_MODE
GetDefaultDevMap (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN BOOLEAN IsGetDevMapLow
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN BOOLEAN IsGetDevMapLow
)
{
- UINT8 StartIndex;
- DEV_MAP_MODE DevMapMode;
+ UINT8 StartIndex;
+ DEV_MAP_MODE DevMapMode;
DevMapMode = DevMapMode4;
StartIndex = IsGetDevMapLow ? PcieController0 : PcieController4;
- while (DevMapMode >= DevMapMode1)
- {
+ while (DevMapMode >= DevMapMode1) {
switch (DevMapMode) {
- case DevMapMode4:
- if (RootComplex->Pcie[StartIndex].Active
- && RootComplex->Pcie[StartIndex + 1].Active
- && RootComplex->Pcie[StartIndex + 2].Active
- && RootComplex->Pcie[StartIndex + 3].Active) {
- return DevMapMode4;
- }
- break;
- case DevMapMode3:
- if (RootComplex->Pcie[StartIndex].Active
- && RootComplex->Pcie[StartIndex + 2].Active
- && RootComplex->Pcie[StartIndex + 3].Active) {
- return DevMapMode3;
- }
- break;
- case DevMapMode2:
- if (RootComplex->Pcie[StartIndex].Active
- && RootComplex->Pcie[StartIndex + 2].Active) {
- return DevMapMode2;
- }
- break;
- default:
- return DevMapMode1;
+ case DevMapMode4:
+ if ( RootComplex->Pcie[StartIndex].Active
+ && RootComplex->Pcie[StartIndex + 1].Active
+ && RootComplex->Pcie[StartIndex + 2].Active
+ && RootComplex->Pcie[StartIndex + 3].Active)
+ {
+ return DevMapMode4;
+ }
+
+ break;
+ case DevMapMode3:
+ if ( RootComplex->Pcie[StartIndex].Active
+ && RootComplex->Pcie[StartIndex + 2].Active
+ && RootComplex->Pcie[StartIndex + 3].Active)
+ {
+ return DevMapMode3;
+ }
+
+ break;
+ case DevMapMode2:
+ if ( RootComplex->Pcie[StartIndex].Active
+ && RootComplex->Pcie[StartIndex + 2].Active)
+ {
+ return DevMapMode2;
+ }
+
+ break;
+ default:
+ return DevMapMode1;
}
DevMapMode--;
@@ -199,7 +204,7 @@ GetDefaultDevMap ( VOID
GetDevMap (
- IN OUT AC01_ROOT_COMPLEX *RootComplex
+ IN OUT AC01_ROOT_COMPLEX *RootComplex
)
{
//
@@ -208,6 +213,7 @@ GetDevMap ( if (RootComplex->DefaultDevMapLow != DevMapModeAuto) {
RootComplex->DefaultDevMapLow = GetDefaultDevMap (RootComplex, TRUE);
}
+
if (RootComplex->DevMapLow == 0) {
RootComplex->DevMapLow = RootComplex->DefaultDevMapLow;
}
@@ -216,7 +222,7 @@ GetDevMap ( // Get default Devmap high and configure Devmap high accordingly.
//
RootComplex->DefaultDevMapHigh = IsAc01Processor () ? GetDefaultDevMap (RootComplex, FALSE) : DevMapMode1;
- if (RootComplex->Type == RootComplexTypeB && RootComplex->DevMapHigh == 0) {
+ if ((RootComplex->Type == RootComplexTypeB) && (RootComplex->DevMapHigh == 0)) {
RootComplex->DevMapHigh = RootComplex->DefaultDevMapHigh;
}
@@ -231,7 +237,7 @@ GetDevMap ( UINT8
GetMaxController (
- IN AC01_ROOT_COMPLEX *RootComplex
+ IN AC01_ROOT_COMPLEX *RootComplex
)
{
if (IsAc01Processor ()) {
@@ -243,39 +249,38 @@ GetMaxController ( NVPARAM
CalculateNvParamOffset (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN UINT8 PaddingOrder,
- IN UINT8 StartIndex,
- IN UINT64 StartOffset
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN UINT8 PaddingOrder,
+ IN UINT8 StartIndex,
+ IN UINT64 StartOffset
)
{
- UINT8 NeededPadding;
- INT8 PositionFromStartIndex;
- NVPARAM NvParamOffset;
+ UINT8 NeededPadding;
+ INT8 PositionFromStartIndex;
+ NVPARAM NvParamOffset;
-
- NeededPadding = RootComplex->ID - PaddingOrder;
+ NeededPadding = RootComplex->ID - PaddingOrder;
PositionFromStartIndex = (RootComplex->ID - StartIndex) + NeededPadding;
- NvParamOffset = StartOffset + PositionFromStartIndex * NV_PARAM_ENTRYSIZE;
+ NvParamOffset = StartOffset + PositionFromStartIndex * NV_PARAM_ENTRYSIZE;
return NvParamOffset;
}
EFI_STATUS_CODE_TYPE
GetNvParamOffsetLane (
- IN AC01_ROOT_COMPLEX *RootComplex,
- OUT NVPARAM *NvParamOffset
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ OUT NVPARAM *NvParamOffset
)
{
- BOOLEAN IsAc01;
- BOOLEAN IsRootComplexTypeA;
- BOOLEAN IsSocket0;
- UINT8 StartIndex;
- UINT64 StartOffset;
- UINT8 PaddingOrder;
-
- IsSocket0 = RootComplex->Socket == 0 ? TRUE : FALSE;
- IsAc01 = IsAc01Processor ();
+ BOOLEAN IsAc01;
+ BOOLEAN IsRootComplexTypeA;
+ BOOLEAN IsSocket0;
+ UINT8 StartIndex;
+ UINT64 StartOffset;
+ UINT8 PaddingOrder;
+
+ IsSocket0 = RootComplex->Socket == 0 ? TRUE : FALSE;
+ IsAc01 = IsAc01Processor ();
IsRootComplexTypeA = RootComplex->Type == RootComplexTypeA ? TRUE : FALSE;
if (!IsAc01 && (RootComplex->ID >= MaxPcieControllerOfRootComplexA)) {
@@ -283,12 +288,12 @@ GetNvParamOffsetLane ( // Altra Max are not sequential arrangement with NV_SI_RO_BOARD_S0_RCA0_CFG
// so the start index will be the first Root Complex ID which using these NVParams
// (NV_SI_RO_BOARD_S0_RCA4_CFG to NV_SI_RO_BOARD_S0_RCA7_CFG) to support Altra Max processor.
- StartIndex = 4;
- StartOffset = IsSocket0 ? NV_SI_RO_BOARD_S0_RCA4_CFG : NV_SI_RO_BOARD_S1_RCA4_CFG;
+ StartIndex = 4;
+ StartOffset = IsSocket0 ? NV_SI_RO_BOARD_S0_RCA4_CFG : NV_SI_RO_BOARD_S1_RCA4_CFG;
PaddingOrder = RootComplex->ID;
} else {
- StartIndex = 0;
- StartOffset = IsSocket0 ? NV_SI_RO_BOARD_S0_RCA0_CFG : NV_SI_RO_BOARD_S1_RCA0_CFG;
+ StartIndex = 0;
+ StartOffset = IsSocket0 ? NV_SI_RO_BOARD_S0_RCA0_CFG : NV_SI_RO_BOARD_S1_RCA0_CFG;
PaddingOrder = IsRootComplexTypeA ? RootComplex->ID : MaxRootComplexA;
}
@@ -298,45 +303,47 @@ GetNvParamOffsetLane ( EFI_STATUS
GetNvParamOffsetPreset (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN NVPARAM_PCIE_PRESET_TYPE PresetType,
- OUT NVPARAM *NvParamOffset
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN NVPARAM_PCIE_PRESET_TYPE PresetType,
+ OUT NVPARAM *NvParamOffset
)
{
- BOOLEAN IsAc01;
- BOOLEAN IsRootComplexTypeA;
- BOOLEAN IsSocket0;
- UINT8 StartIndex;
- UINT64 StartOffset;
- UINT8 PaddingOrder;
-
- IsSocket0 = RootComplex->Socket == 0 ? TRUE : FALSE;
- IsAc01 = IsAc01Processor ();
+ BOOLEAN IsAc01;
+ BOOLEAN IsRootComplexTypeA;
+ BOOLEAN IsSocket0;
+ UINT8 StartIndex;
+ UINT64 StartOffset;
+ UINT8 PaddingOrder;
+
+ IsSocket0 = RootComplex->Socket == 0 ? TRUE : FALSE;
+ IsAc01 = IsAc01Processor ();
IsRootComplexTypeA = RootComplex->Type == RootComplexTypeA ? TRUE : FALSE;
switch (PresetType) {
- case Gen3Preset:
- if (IsAc01) {
- StartOffset = IsSocket0 ? NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET :
- NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET;
- } else {
- StartOffset = IsSocket0 ? NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G3PRESET :
- NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G3PRESET;
- }
- break;
-
- case Gen4Preset:
- if (IsAc01) {
- StartOffset = IsSocket0 ? NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET :
- NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET;
- } else {
- StartOffset = IsSocket0 ? NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G4PRESET :
- NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G4PRESET;
- }
- break;
+ case Gen3Preset:
+ if (IsAc01) {
+ StartOffset = IsSocket0 ? NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET :
+ NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET;
+ } else {
+ StartOffset = IsSocket0 ? NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G3PRESET :
+ NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G3PRESET;
+ }
- default:
- return EFI_INVALID_PARAMETER;
+ break;
+
+ case Gen4Preset:
+ if (IsAc01) {
+ StartOffset = IsSocket0 ? NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET :
+ NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET;
+ } else {
+ StartOffset = IsSocket0 ? NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G4PRESET :
+ NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G4PRESET;
+ }
+
+ break;
+
+ default:
+ return EFI_INVALID_PARAMETER;
}
//
@@ -358,15 +365,15 @@ GetNvParamOffsetPreset ( VOID
GetLaneAllocation (
- IN OUT AC01_ROOT_COMPLEX *RootComplex
+ IN OUT AC01_ROOT_COMPLEX *RootComplex
)
{
- EFI_STATUS Status;
- INTN RPIndex;
- NVPARAM NvParamOffset;
- UINT32 Value;
- UINT32 Width;
- UINT32 MaxController;
+ EFI_STATUS Status;
+ INTN RPIndex;
+ NVPARAM NvParamOffset;
+ UINT32 Value;
+ UINT32 Width;
+ UINT32 MaxController;
Status = GetNvParamOffsetLane (RootComplex, &NvParamOffset);
if (!EFI_ERROR (Status)) {
@@ -382,35 +389,35 @@ GetLaneAllocation ( for (RPIndex = PcieController0; RPIndex < MaxController; RPIndex++) {
Width = (Value >> (RPIndex * BITS_PER_BYTE)) & BYTE_MASK;
switch (Width) {
- case 1:
- case 2:
- case 3:
- case 4:
- RootComplex->Pcie[RPIndex].MaxWidth = 1 << Width;
- RootComplex->Pcie[RPIndex].MaxGen = LINK_SPEED_GEN3;
- RootComplex->Pcie[RPIndex].Active = TRUE;
- break;
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ RootComplex->Pcie[RPIndex].MaxWidth = 1 << Width;
+ RootComplex->Pcie[RPIndex].MaxGen = LINK_SPEED_GEN3;
+ RootComplex->Pcie[RPIndex].Active = TRUE;
+ break;
- case 0:
- default:
- RootComplex->Pcie[RPIndex].MaxWidth = LINK_WIDTH_NONE;
- RootComplex->Pcie[RPIndex].MaxGen = LINK_SPEED_NONE;
- RootComplex->Pcie[RPIndex].Active = FALSE;
- break;
+ case 0:
+ default:
+ RootComplex->Pcie[RPIndex].MaxWidth = LINK_WIDTH_NONE;
+ RootComplex->Pcie[RPIndex].MaxGen = LINK_SPEED_NONE;
+ RootComplex->Pcie[RPIndex].Active = FALSE;
+ break;
}
}
// Update RootComplex data to handle auto bifurcation mode on RCA
if (Value == AUTO_BIFURCATION_SETTING_VALUE) {
RootComplex->Pcie[PcieController0].MaxWidth = LINK_WIDTH_X4;
- RootComplex->Pcie[PcieController0].MaxGen = LINK_SPEED_GEN3;
- RootComplex->Pcie[PcieController0].Active = TRUE;
- RootComplex->DefaultDevMapLow = DevMapModeAuto;
+ RootComplex->Pcie[PcieController0].MaxGen = LINK_SPEED_GEN3;
+ RootComplex->Pcie[PcieController0].Active = TRUE;
+ RootComplex->DefaultDevMapLow = DevMapModeAuto;
}
if (RootComplex->Type == RootComplexTypeB) {
NvParamOffset += NV_PARAM_ENTRYSIZE;
- Status = NVParamGet (NvParamOffset, NV_PERM_ALL, &Value);
+ Status = NVParamGet (NvParamOffset, NV_PERM_ALL, &Value);
if (EFI_ERROR (Status)) {
Value = 0;
}
@@ -418,21 +425,21 @@ GetLaneAllocation ( for (RPIndex = MaxPcieControllerOfRootComplexA; RPIndex < MaxPcieController; RPIndex++) {
Width = (Value >> ((RPIndex - MaxPcieControllerOfRootComplexA) * BITS_PER_BYTE)) & BYTE_MASK;
switch (Width) {
- case 1:
- case 2:
- case 3:
- case 4:
- RootComplex->Pcie[RPIndex].MaxWidth = 1 << Width;
- RootComplex->Pcie[RPIndex].MaxGen = LINK_SPEED_GEN3;
- RootComplex->Pcie[RPIndex].Active = TRUE;
- break;
-
- case 0:
- default:
- RootComplex->Pcie[RPIndex].MaxWidth = LINK_WIDTH_NONE;
- RootComplex->Pcie[RPIndex].MaxGen = LINK_SPEED_NONE;
- RootComplex->Pcie[RPIndex].Active = FALSE;
- break;
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ RootComplex->Pcie[RPIndex].MaxWidth = 1 << Width;
+ RootComplex->Pcie[RPIndex].MaxGen = LINK_SPEED_GEN3;
+ RootComplex->Pcie[RPIndex].Active = TRUE;
+ break;
+
+ case 0:
+ default:
+ RootComplex->Pcie[RPIndex].MaxWidth = LINK_WIDTH_NONE;
+ RootComplex->Pcie[RPIndex].MaxGen = LINK_SPEED_NONE;
+ RootComplex->Pcie[RPIndex].Active = FALSE;
+ break;
}
}
}
@@ -445,7 +452,7 @@ GetLaneAllocation ( VOID
GetPresetSetting (
- AC01_ROOT_COMPLEX *RootComplex
+ AC01_ROOT_COMPLEX *RootComplex
)
{
EFI_STATUS Status;
@@ -464,6 +471,7 @@ GetPresetSetting ( if (!EFI_ERROR (Status)) {
Status = NVParamGet (NvParamOffset, NV_PERM_ALL, &Value);
}
+
if (!EFI_ERROR (Status)) {
for (Index = 0; Index < MaxPcieControllerOfRootComplexA; Index++) {
RootComplex->PresetGen3[Index] = (Value >> (Index * BITS_PER_BYTE)) & BYTE_MASK;
@@ -472,7 +480,7 @@ GetPresetSetting ( if (RootComplex->Type == RootComplexTypeB) {
NvParamOffset += NV_PARAM_ENTRYSIZE;
- Status = NVParamGet (NvParamOffset, NV_PERM_ALL, &Value);
+ Status = NVParamGet (NvParamOffset, NV_PERM_ALL, &Value);
if (!EFI_ERROR (Status)) {
for (Index = MaxPcieControllerOfRootComplexA; Index < MaxPcieController; Index++) {
RootComplex->PresetGen3[Index] = (Value >> ((Index - MaxPcieControllerOfRootComplexA) * BITS_PER_BYTE)) & BYTE_MASK;
@@ -485,6 +493,7 @@ GetPresetSetting ( if (!EFI_ERROR (Status)) {
Status = NVParamGet (NvParamOffset, NV_PERM_ALL, &Value);
}
+
if (!EFI_ERROR (Status)) {
for (Index = 0; Index < MaxPcieControllerOfRootComplexA; Index++) {
RootComplex->PresetGen4[Index] = (Value >> (Index * BITS_PER_BYTE)) & BYTE_MASK;
@@ -493,7 +502,7 @@ GetPresetSetting ( if (RootComplex->Type == RootComplexTypeB) {
NvParamOffset += NV_PARAM_ENTRYSIZE;
- Status = NVParamGet (NvParamOffset, NV_PERM_ALL, &Value);
+ Status = NVParamGet (NvParamOffset, NV_PERM_ALL, &Value);
if (!EFI_ERROR (Status)) {
for (Index = MaxPcieControllerOfRootComplexA; Index < MaxPcieController; Index++) {
RootComplex->PresetGen4[Index] = (Value >> ((Index - MaxPcieControllerOfRootComplexA) * BITS_PER_BYTE)) & BYTE_MASK;
@@ -504,16 +513,16 @@ GetPresetSetting ( VOID
GetMaxSpeedGen (
- AC01_ROOT_COMPLEX *RootComplex
+ AC01_ROOT_COMPLEX *RootComplex
)
{
- UINT8 MaxSpeedGen[MaxPcieControllerOfRootComplexA] = { LINK_SPEED_GEN4, LINK_SPEED_GEN4, LINK_SPEED_GEN4, LINK_SPEED_GEN4 }; // Bifurcation 0: RootComplexTypeA x16 / RootComplexTypeB x8
- UINT8 ErrataSpeedDevMap3[MaxPcieControllerOfRootComplexA] = { LINK_SPEED_GEN4, LINK_SPEED_GEN4, LINK_SPEED_GEN1, LINK_SPEED_GEN1 }; // Bifurcation 2: x8 x4 x4 (PCIE_ERRATA_SPEED1)
- UINT8 ErrataSpeedDevMap4[MaxPcieControllerOfRootComplexA] = { LINK_SPEED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1 }; // Bifurcation 3: x4 x4 x4 x4 (PCIE_ERRATA_SPEED1)
- UINT8 ErrataSpeedRcb[MaxPcieControllerOfRootComplexA] = { LINK_SPEED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1 }; // RootComplexTypeB PCIE_ERRATA_SPEED1
- UINT8 Idx;
- UINT8 MaxController;
- UINT8 *MaxGen;
+ UINT8 MaxSpeedGen[MaxPcieControllerOfRootComplexA] = { LINK_SPEED_GEN4, LINK_SPEED_GEN4, LINK_SPEED_GEN4, LINK_SPEED_GEN4 }; // Bifurcation 0: RootComplexTypeA x16 / RootComplexTypeB x8
+ UINT8 ErrataSpeedDevMap3[MaxPcieControllerOfRootComplexA] = { LINK_SPEED_GEN4, LINK_SPEED_GEN4, LINK_SPEED_GEN1, LINK_SPEED_GEN1 }; // Bifurcation 2: x8 x4 x4 (PCIE_ERRATA_SPEED1)
+ UINT8 ErrataSpeedDevMap4[MaxPcieControllerOfRootComplexA] = { LINK_SPEED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1 }; // Bifurcation 3: x4 x4 x4 x4 (PCIE_ERRATA_SPEED1)
+ UINT8 ErrataSpeedRcb[MaxPcieControllerOfRootComplexA] = { LINK_SPEED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1, LINK_SPEED_GEN1 }; // RootComplexTypeB PCIE_ERRATA_SPEED1
+ UINT8 Idx;
+ UINT8 MaxController;
+ UINT8 *MaxGen;
ASSERT (MaxPcieControllerOfRootComplexA == 4);
ASSERT (MaxPcieController == 8);
@@ -531,23 +540,25 @@ GetMaxSpeedGen ( }
} else {
switch (RootComplex->DevMapLow) {
- case DevMapMode3: /* x8 x4 x4 */
- if (RootComplex->Flags & PCIE_ERRATA_SPEED1) {
- MaxGen = ErrataSpeedDevMap3;
- }
- break;
+ case DevMapMode3: /* x8 x4 x4 */
+ if (RootComplex->Flags & PCIE_ERRATA_SPEED1) {
+ MaxGen = ErrataSpeedDevMap3;
+ }
- case DevMapModeAuto:
- case DevMapMode4: /* x4 x4 x4 x4 */
- if (RootComplex->Flags & PCIE_ERRATA_SPEED1) {
- MaxGen = ErrataSpeedDevMap4;
- }
- break;
+ break;
- case DevMapMode2: /* x8 x8 */
- case DevMapMode1: /* x16 */
- default:
- break;
+ case DevMapModeAuto:
+ case DevMapMode4: /* x4 x4 x4 x4 */
+ if (RootComplex->Flags & PCIE_ERRATA_SPEED1) {
+ MaxGen = ErrataSpeedDevMap4;
+ }
+
+ break;
+
+ case DevMapMode2: /* x8 x8 */
+ case DevMapMode1: /* x16 */
+ default:
+ break;
}
}
@@ -566,7 +577,7 @@ GetMaxSpeedGen ( VOID
ParseRootComplexNVParamData (
- IN OUT AC01_ROOT_COMPLEX *RootComplex
+ IN OUT AC01_ROOT_COMPLEX *RootComplex
)
{
PLATFORM_INFO_HOB *PlatformHob;
@@ -575,10 +586,10 @@ ParseRootComplexNVParamData ( VOID *Hob;
EFuse = 0;
- Hob = GetFirstGuidHob (&gPlatformInfoHobGuid);
+ Hob = GetFirstGuidHob (&gPlatformInfoHobGuid);
if (Hob != NULL) {
PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
- EFuse = PlatformHob->RcDisableMask[0] | (PlatformHob->RcDisableMask[1] << AC01_PCIE_MAX_RCS_PER_SOCKET);
+ EFuse = PlatformHob->RcDisableMask[0] | (PlatformHob->RcDisableMask[1] << AC01_PCIE_MAX_RCS_PER_SOCKET);
DEBUG ((
DEBUG_INFO,
"RcDisableMask[0]: 0x%x [1]: 0x%x\n",
@@ -588,11 +599,11 @@ ParseRootComplexNVParamData ( // Update errata flags for Ampere Altra
if ((PlatformHob->ScuProductId[0] & 0xff) == 0x01) {
- if (PlatformHob->AHBCId[0] == 0x20100
- || PlatformHob->AHBCId[0] == 0x21100
- || (IsSlaveSocketActive ()
- && (PlatformHob->AHBCId[1] == 0x20100
- || PlatformHob->AHBCId[1] == 0x21100)))
+ if ( (PlatformHob->AHBCId[0] == 0x20100)
+ || (PlatformHob->AHBCId[0] == 0x21100)
+ || ( IsSlaveSocketActive ()
+ && ( (PlatformHob->AHBCId[1] == 0x20100)
+ || (PlatformHob->AHBCId[1] == 0x21100))))
{
RootComplex->Flags |= PCIE_ERRATA_SPEED1;
DEBUG ((DEBUG_INFO, "RootComplex[%d]: Flags 0x%x\n", RootComplex->ID, RootComplex->Flags));
@@ -600,11 +611,12 @@ ParseRootComplexNVParamData ( }
}
- RootComplexID = RootComplex->Socket * AC01_PCIE_MAX_RCS_PER_SOCKET + RootComplex->ID;
+ RootComplexID = RootComplex->Socket * AC01_PCIE_MAX_RCS_PER_SOCKET + RootComplex->ID;
RootComplex->DefaultActive = !(EFuse & BIT (RootComplexID)) ? TRUE : FALSE;
- if (!IsSlaveSocketActive () && RootComplex->Socket == 1) {
+ if (!IsSlaveSocketActive () && (RootComplex->Socket == 1)) {
RootComplex->DefaultActive = FALSE;
}
+
RootComplex->Active = RootComplex->Active && RootComplex->DefaultActive;
GetPresetSetting (RootComplex);
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.h index 8c07f086a5..2e0213b1de 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.h +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PcieInitPei/RootComplexNVParam.h @@ -9,14 +9,14 @@ #ifndef GET_ROOT_COMPLEX_INFO_
#define GET_ROOT_COMPLEX_INFO_
-#define BITS_PER_BYTE 8
-#define BYTE_MASK 0xFF
-#define PCIE_ERRATA_SPEED1 0x0001 // Limited speed errata
+#define BITS_PER_BYTE 8
+#define BYTE_MASK 0xFF
+#define PCIE_ERRATA_SPEED1 0x0001 // Limited speed errata
#define AUTO_BIFURCATION_SETTING_VALUE 0x0A
#ifndef BIT
-#define BIT(nr) (1 << (nr))
+#define BIT(nr) (1 << (nr))
#endif
#define PCIE_GET_MAX_WIDTH(Pcie, Max) \
@@ -24,7 +24,7 @@ VOID
ParseRootComplexNVParamData (
- AC01_ROOT_COMPLEX *RootComplex
+ AC01_ROOT_COMPLEX *RootComplex
);
#endif /* GET_ROOT_COMPLEX_INFO_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.c index a5008cd349..519fbb7105 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoDxe.c @@ -29,11 +29,11 @@ //
// uni string and Vfr Binary data.
//
-extern UINT8 PlatformInfoVfrBin[];
-extern UINT8 PlatformInfoDxeStrings[];
+extern UINT8 PlatformInfoVfrBin[];
+extern UINT8 PlatformInfoDxeStrings[];
-EFI_HANDLE mDriverHandle = NULL;
-EFI_HII_HANDLE mHiiHandle = NULL;
+EFI_HANDLE mDriverHandle = NULL;
+EFI_HII_HANDLE mHiiHandle = NULL;
#pragma pack(1)
@@ -41,16 +41,16 @@ EFI_HII_HANDLE mHiiHandle = NULL; // HII specific Vendor Device Path definition.
//
typedef struct {
- VENDOR_DEVICE_PATH VendorDevicePath;
- EFI_DEVICE_PATH_PROTOCOL End;
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
} HII_VENDOR_DEVICE_PATH;
#pragma pack()
// PLATFORM_INFO_FORMSET_GUID
-EFI_GUID gPlatformInfoFormSetGuid = PLATFORM_INFO_FORMSET_GUID;
+EFI_GUID gPlatformInfoFormSetGuid = PLATFORM_INFO_FORMSET_GUID;
-HII_VENDOR_DEVICE_PATH mPlatformInfoHiiVendorDevicePath = {
+HII_VENDOR_DEVICE_PATH mPlatformInfoHiiVendorDevicePath = {
{
{
HARDWARE_DEVICE_PATH,
@@ -72,34 +72,34 @@ HII_VENDOR_DEVICE_PATH mPlatformInfoHiiVendorDevicePath = { }
};
-#define MAX_STRING_SIZE 64
-#define MHZ_SCALE_FACTOR 1000000
+#define MAX_STRING_SIZE 64
+#define MHZ_SCALE_FACTOR 1000000
STATIC
CHAR8 *
GetCCIXLinkSpeed (
- IN UINTN Speed
+ IN UINTN Speed
)
{
switch (Speed) {
- case 1:
- return "2.5 GT/s";
+ case 1:
+ return "2.5 GT/s";
- case 2:
- return "5 GT/s";
+ case 2:
+ return "5 GT/s";
- case 3:
- return "8 GT/s";
+ case 3:
+ return "8 GT/s";
- case 4:
- case 6:
- return "16 GT/s";
+ case 4:
+ case 6:
+ return "16 GT/s";
- case 0xa:
- return "20 GT/s";
+ case 0xa:
+ return "20 GT/s";
- case 0xf:
- return "25 GT/s";
+ case 0xf:
+ return "25 GT/s";
}
return "Unknown";
@@ -108,23 +108,24 @@ GetCCIXLinkSpeed ( STATIC
EFI_STATUS
UpdatePlatformInfoScreen (
- IN EFI_HII_HANDLE *HiiHandle
+ IN EFI_HII_HANDLE *HiiHandle
)
{
VOID *Hob;
PLATFORM_INFO_HOB *PlatformHob;
CHAR16 Str[MAX_STRING_SIZE];
- VOID *StartOpCodeHandle;
- EFI_IFR_GUID_LABEL *StartLabel;
- VOID *EndOpCodeHandle;
- EFI_IFR_GUID_LABEL *EndLabel;
+ VOID *StartOpCodeHandle;
+ EFI_IFR_GUID_LABEL *StartLabel;
+ VOID *EndOpCodeHandle;
+ EFI_IFR_GUID_LABEL *EndLabel;
/* Get the Platform HOB */
Hob = GetFirstGuidHob (&gPlatformInfoHobGuid);
if (Hob == NULL) {
return EFI_DEVICE_ERROR;
}
+
PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
/* SCP Version */
@@ -354,11 +355,11 @@ PlatformInfoUnload ( EFI_STATUS
EFIAPI
PlatformInfoEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = gBS->InstallMultipleProtocolInterfaces (
&mDriverHandle,
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoHii.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoHii.h index 7f363160af..82541ffff0 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoHii.h +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/PlatformInfoDxe/PlatformInfoHii.h @@ -14,9 +14,9 @@ 0x8DF0F6FB, 0x65A5, 0x434B, { 0xB2, 0xA6, 0xCE, 0xDF, 0xD2, 0x0A, 0x96, 0x8A } \
}
-#define LABEL_UPDATE 0x2223
-#define LABEL_END 0x2224
+#define LABEL_UPDATE 0x2223
+#define LABEL_END 0x2224
-#define PLATFORM_INFO_FORM_ID 0x1
+#define PLATFORM_INFO_FORM_ID 0x1
#endif
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.c index dc11083355..921850210c 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.c @@ -29,12 +29,12 @@ #include "RasConfigDxe.h"
-CHAR16 RasConfigVarstoreDataName[] = L"RasConfigNVData";
+CHAR16 RasConfigVarstoreDataName[] = L"RasConfigNVData";
-EFI_HANDLE mDriverHandle = NULL;
-RAS_CONFIG_PRIVATE_DATA *mPrivateData = NULL;
+EFI_HANDLE mDriverHandle = NULL;
+RAS_CONFIG_PRIVATE_DATA *mPrivateData = NULL;
-EFI_GUID mRasConfigFormSetGuid = RAS_CONFIG_FORMSET_GUID;
+EFI_GUID mRasConfigFormSetGuid = RAS_CONFIG_FORMSET_GUID;
//
// Default RAS Settings
@@ -48,8 +48,7 @@ EFI_GUID mRasConfigFormSetGuid = RAS_CONFIG_FORMSET_GUID; #define RAS_DEFAULT_PROCESSOR_CE_THRESHOLD 1
#define RAS_DEFAULT_DDR_LINK_ERROR_THRESHOLD 1
-
-HII_VENDOR_DEVICE_PATH mRasConfigHiiVendorDevicePath = {
+HII_VENDOR_DEVICE_PATH mRasConfigHiiVendorDevicePath = {
{
{
HARDWARE_DEVICE_PATH,
@@ -103,11 +102,11 @@ IsDdrCeWindowEnabled ( EFI_STATUS
RasConfigNvParamGet (
- OUT RAS_CONFIG_VARSTORE_DATA *Configuration
+ OUT RAS_CONFIG_VARSTORE_DATA *Configuration
)
{
- EFI_STATUS Status;
- UINT32 Value;
+ EFI_STATUS Status;
+ UINT32 Value;
Status = NVParamGet (
NV_SI_HARDWARE_EINJ,
@@ -115,7 +114,7 @@ RasConfigNvParamGet ( &Value
);
if (EFI_ERROR (Status)) {
- Value = RAS_DEFAULT_HARDWARE_EINJ_SUPPORT;
+ Value = RAS_DEFAULT_HARDWARE_EINJ_SUPPORT;
Status = NVParamSet (
NV_SI_HARDWARE_EINJ,
NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
@@ -128,6 +127,7 @@ RasConfigNvParamGet ( Value = 0;
}
}
+
Configuration->RasHardwareEinj = Value;
Status = NVParamGet (
@@ -136,7 +136,7 @@ RasConfigNvParamGet ( &Value
);
if (EFI_ERROR (Status)) {
- Value = RAS_DEFAULT_PCIE_AER_FW_FIRST;
+ Value = RAS_DEFAULT_PCIE_AER_FW_FIRST;
Status = NVParamSet (
NV_SI_RAS_PCIE_AER_FW_FIRST,
NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
@@ -149,6 +149,7 @@ RasConfigNvParamGet ( Value = 0;
}
}
+
Configuration->RasPcieAerFwFirstEnabled = Value;
Status = NVParamGet (
@@ -157,7 +158,7 @@ RasConfigNvParamGet ( &Value
);
if (EFI_ERROR (Status)) {
- Value = RAS_DEFAULT_BERT_SUPPORT;
+ Value = RAS_DEFAULT_BERT_SUPPORT;
Status = NVParamSet (
NV_SI_RAS_BERT_ENABLED,
NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
@@ -170,6 +171,7 @@ RasConfigNvParamGet ( Value = 0;
}
}
+
Configuration->RasBertEnabled = Value;
Status = NVParamGet (
@@ -178,7 +180,7 @@ RasConfigNvParamGet ( &Value
);
if (EFI_ERROR (Status)) {
- Value = RAS_DEFAULT_SDEI_SUPPORT;
+ Value = RAS_DEFAULT_SDEI_SUPPORT;
Status = NVParamSet (
NV_SI_RAS_SDEI_ENABLED,
NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
@@ -191,6 +193,7 @@ RasConfigNvParamGet ( Value = 0;
}
}
+
Configuration->RasSdeiEnabled = Value;
Status = NVParamGet (
@@ -199,7 +202,7 @@ RasConfigNvParamGet ( &Value
);
if (EFI_ERROR (Status)) {
- Value = RAS_DEFAULT_DDR_CE_THRESHOLD;
+ Value = RAS_DEFAULT_DDR_CE_THRESHOLD;
Status = NVParamSet (
NV_SI_DDR_CE_RAS_THRESHOLD,
NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
@@ -212,6 +215,7 @@ RasConfigNvParamGet ( Value = 0;
}
}
+
Configuration->RasDdrCeThreshold = Value;
Status = NVParamGet (
@@ -220,7 +224,7 @@ RasConfigNvParamGet ( &Value
);
if (EFI_ERROR (Status)) {
- Value = RAS_DEFAULT_2P_CE_THRESHOLD;
+ Value = RAS_DEFAULT_2P_CE_THRESHOLD;
Status = NVParamSet (
NV_SI_2P_CE_RAS_THRESHOLD,
NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
@@ -233,6 +237,7 @@ RasConfigNvParamGet ( Value = 0;
}
}
+
Configuration->Ras2pCeThreshold = Value;
Status = NVParamGet (
@@ -241,7 +246,7 @@ RasConfigNvParamGet ( &Value
);
if (EFI_ERROR (Status)) {
- Value = RAS_DEFAULT_PROCESSOR_CE_THRESHOLD;
+ Value = RAS_DEFAULT_PROCESSOR_CE_THRESHOLD;
Status = NVParamSet (
NV_SI_CPM_CE_RAS_THRESHOLD,
NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
@@ -254,6 +259,7 @@ RasConfigNvParamGet ( Value = 0;
}
}
+
Configuration->RasCpmCeThreshold = Value;
Status = NVParamGet (
@@ -262,7 +268,7 @@ RasConfigNvParamGet ( &Value
);
if (EFI_ERROR (Status)) {
- Value = RAS_DEFAULT_DDR_LINK_ERROR_THRESHOLD;
+ Value = RAS_DEFAULT_DDR_LINK_ERROR_THRESHOLD;
Status = NVParamSet (
NV_SI_LINK_ERR_THRESHOLD,
NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
@@ -275,6 +281,7 @@ RasConfigNvParamGet ( Value = 0;
}
}
+
Configuration->RasLinkErrThreshold = Value;
return EFI_SUCCESS;
@@ -282,10 +289,10 @@ RasConfigNvParamGet ( EFI_STATUS
RasConfigNvParamSet (
- IN RAS_CONFIG_VARSTORE_DATA *Configuration
+ IN RAS_CONFIG_VARSTORE_DATA *Configuration
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = NVParamSet (
NV_SI_HARDWARE_EINJ,
@@ -383,38 +390,39 @@ RasConfigNvParamSet ( EFI_STATUS
EFIAPI
RasConfigExtractConfig (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN CONST EFI_STRING Request,
- OUT EFI_STRING *Progress,
- OUT EFI_STRING *Results
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Request,
+ OUT EFI_STRING *Progress,
+ OUT EFI_STRING *Results
)
{
- EFI_STATUS Status;
- UINTN BufferSize;
- RAS_CONFIG_PRIVATE_DATA *PrivateData;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- EFI_STRING ConfigRequest;
- EFI_STRING ConfigRequestHdr;
- UINTN Size;
- BOOLEAN AllocatedRequest;
-
- if (Progress == NULL || Results == NULL) {
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ RAS_CONFIG_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STRING ConfigRequest;
+ EFI_STRING ConfigRequestHdr;
+ UINTN Size;
+ BOOLEAN AllocatedRequest;
+
+ if ((Progress == NULL) || (Results == NULL)) {
return EFI_INVALID_PARAMETER;
}
+
//
// Initialize the local variables.
//
- ConfigRequestHdr = NULL;
- ConfigRequest = NULL;
- Size = 0;
- *Progress = Request;
- AllocatedRequest = FALSE;
+ ConfigRequestHdr = NULL;
+ ConfigRequest = NULL;
+ Size = 0;
+ *Progress = Request;
+ AllocatedRequest = FALSE;
if ((Request != NULL) && !HiiIsConfigHdrMatch (Request, &mRasConfigFormSetGuid, RasConfigVarstoreDataName)) {
return EFI_NOT_FOUND;
}
- PrivateData = RAS_CONFIG_PRIVATE_FROM_THIS (This);
+ PrivateData = RAS_CONFIG_PRIVATE_FROM_THIS (This);
HiiConfigRouting = PrivateData->HiiConfigRouting;
//
@@ -428,7 +436,7 @@ RasConfigExtractConfig ( //
// Convert buffer data to <ConfigResp> by helper function BlockToConfig()
//
- BufferSize = sizeof (RAS_CONFIG_VARSTORE_DATA);
+ BufferSize = sizeof (RAS_CONFIG_VARSTORE_DATA);
ConfigRequest = Request;
if ((Request == NULL) || (StrStr (Request, L"OFFSET") == NULL)) {
//
@@ -437,12 +445,13 @@ RasConfigExtractConfig ( // followed by "&OFFSET=0&WIDTH=WWWWWWWWWWWWWWWW" followed by a Null-terminator
//
ConfigRequestHdr = HiiConstructConfigHdr (&mRasConfigFormSetGuid, RasConfigVarstoreDataName, PrivateData->DriverHandle);
- Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);
- ConfigRequest = AllocateZeroPool (Size);
+ Size = (StrLen (ConfigRequestHdr) + 32 + 1) * sizeof (CHAR16);
+ ConfigRequest = AllocateZeroPool (Size);
ASSERT (ConfigRequest != NULL);
if (ConfigRequest == NULL) {
return EFI_OUT_OF_RESOURCES;
}
+
AllocatedRequest = TRUE;
UnicodeSPrint (ConfigRequest, Size, L"%s&OFFSET=0&WIDTH=%016LX", ConfigRequestHdr, (UINT64)BufferSize);
FreePool (ConfigRequestHdr);
@@ -501,23 +510,23 @@ RasConfigExtractConfig ( EFI_STATUS
EFIAPI
RasConfigRouteConfig (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN CONST EFI_STRING Configuration,
- OUT EFI_STRING *Progress
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Configuration,
+ OUT EFI_STRING *Progress
)
{
- EFI_STATUS Status;
- UINTN BufferSize;
- RAS_CONFIG_PRIVATE_DATA *PrivateData;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ RAS_CONFIG_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- if (Configuration == NULL || Progress == NULL) {
+ if ((Configuration == NULL) || (Progress == NULL)) {
return EFI_INVALID_PARAMETER;
}
- PrivateData = RAS_CONFIG_PRIVATE_FROM_THIS (This);
+ PrivateData = RAS_CONFIG_PRIVATE_FROM_THIS (This);
HiiConfigRouting = PrivateData->HiiConfigRouting;
- *Progress = Configuration;
+ *Progress = Configuration;
//
// Check routing data in <ConfigHdr>.
@@ -539,13 +548,13 @@ RasConfigRouteConfig ( // Convert <ConfigResp> to buffer data by helper function ConfigToBlock()
//
BufferSize = sizeof (RAS_CONFIG_VARSTORE_DATA);
- Status = HiiConfigRouting->ConfigToBlock (
- HiiConfigRouting,
- Configuration,
- (UINT8 *)&PrivateData->Configuration,
- &BufferSize,
- Progress
- );
+ Status = HiiConfigRouting->ConfigToBlock (
+ HiiConfigRouting,
+ Configuration,
+ (UINT8 *)&PrivateData->Configuration,
+ &BufferSize,
+ Progress
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -582,12 +591,12 @@ RasConfigRouteConfig ( EFI_STATUS
EFIAPI
RasConfigCallback (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN EFI_BROWSER_ACTION Action,
- IN EFI_QUESTION_ID QuestionId,
- IN UINT8 Type,
- IN EFI_IFR_TYPE_VALUE *Value,
- OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN EFI_BROWSER_ACTION Action,
+ IN EFI_QUESTION_ID QuestionId,
+ IN UINT8 Type,
+ IN EFI_IFR_TYPE_VALUE *Value,
+ OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
)
{
if (Action != EFI_BROWSER_ACTION_CHANGING) {
@@ -596,10 +605,11 @@ RasConfigCallback ( //
return EFI_UNSUPPORTED;
}
- if (((Value == NULL)
- && (Action != EFI_BROWSER_ACTION_FORM_OPEN)
- && (Action != EFI_BROWSER_ACTION_FORM_CLOSE))
- || (ActionRequest == NULL))
+
+ if ( ( (Value == NULL)
+ && (Action != EFI_BROWSER_ACTION_FORM_OPEN)
+ && (Action != EFI_BROWSER_ACTION_FORM_CLOSE))
+ || (ActionRequest == NULL))
{
return EFI_INVALID_PARAMETER;
}
@@ -609,14 +619,14 @@ RasConfigCallback ( EFI_STATUS
UpdateRasConfigScreen (
- IN RAS_CONFIG_PRIVATE_DATA *PrivateData
+ IN RAS_CONFIG_PRIVATE_DATA *PrivateData
)
{
- EFI_STATUS Status;
- VOID *StartOpCodeHandle;
- EFI_IFR_GUID_LABEL *StartLabel;
- VOID *EndOpCodeHandle;
- EFI_IFR_GUID_LABEL *EndLabel;
+ EFI_STATUS Status;
+ VOID *StartOpCodeHandle;
+ EFI_IFR_GUID_LABEL *StartLabel;
+ VOID *EndOpCodeHandle;
+ EFI_IFR_GUID_LABEL *EndLabel;
//
// Initialize the container for dynamic opcodes
@@ -640,6 +650,7 @@ UpdateRasConfigScreen ( Status = EFI_OUT_OF_RESOURCES;
goto FreeOpCodeBuffer;
}
+
StartLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
StartLabel->Number = LABEL_UPDATE;
@@ -656,6 +667,7 @@ UpdateRasConfigScreen ( Status = EFI_OUT_OF_RESOURCES;
goto FreeOpCodeBuffer;
}
+
EndLabel->ExtendOpCode = EFI_IFR_EXTEND_OP_LABEL;
EndLabel->Number = LABEL_END;
@@ -747,13 +759,13 @@ RasConfigUnload ( EFI_STATUS
EFIAPI
RasConfigEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- EFI_HII_HANDLE HiiHandle;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STATUS Status;
+ EFI_HII_HANDLE HiiHandle;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
//
// Initialize driver private data
@@ -766,8 +778,8 @@ RasConfigEntryPoint ( mPrivateData->Signature = RAS_CONFIG_PRIVATE_SIGNATURE;
mPrivateData->ConfigAccess.ExtractConfig = RasConfigExtractConfig;
- mPrivateData->ConfigAccess.RouteConfig = RasConfigRouteConfig;
- mPrivateData->ConfigAccess.Callback = RasConfigCallback;
+ mPrivateData->ConfigAccess.RouteConfig = RasConfigRouteConfig;
+ mPrivateData->ConfigAccess.Callback = RasConfigCallback;
//
// Locate ConfigRouting protocol
@@ -776,6 +788,7 @@ RasConfigEntryPoint ( if (EFI_ERROR (Status)) {
return Status;
}
+
mPrivateData->HiiConfigRouting = HiiConfigRouting;
Status = gBS->InstallMultipleProtocolInterfaces (
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.h index 1258fbeda6..6c149317ce 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.h +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigDxe.h @@ -14,34 +14,34 @@ //
// This is the generated IFR binary data for each formset defined in VFR.
//
-extern UINT8 RasConfigVfrBin[];
+extern UINT8 RasConfigVfrBin[];
//
// This is the generated String package data for all .UNI files.
//
-extern UINT8 RasConfigDxeStrings[];
+extern UINT8 RasConfigDxeStrings[];
-#define RAS_DDR_CE_THRESHOLD_OFST OFFSET_OF (RAS_CONFIG_VARSTORE_DATA, RasDdrCeThreshold)
-#define RAS_2P_CE_THRESHOLD_OFST OFFSET_OF (RAS_CONFIG_VARSTORE_DATA, Ras2pCeThreshold)
+#define RAS_DDR_CE_THRESHOLD_OFST OFFSET_OF (RAS_CONFIG_VARSTORE_DATA, RasDdrCeThreshold)
+#define RAS_2P_CE_THRESHOLD_OFST OFFSET_OF (RAS_CONFIG_VARSTORE_DATA, Ras2pCeThreshold)
-#define RAS_CONFIG_PRIVATE_SIGNATURE SIGNATURE_32 ('R', 'A', 'S', 'C')
+#define RAS_CONFIG_PRIVATE_SIGNATURE SIGNATURE_32 ('R', 'A', 'S', 'C')
typedef struct {
- UINTN Signature;
+ UINTN Signature;
- EFI_HANDLE DriverHandle;
- EFI_HII_HANDLE HiiHandle;
- RAS_CONFIG_VARSTORE_DATA Configuration;
+ EFI_HANDLE DriverHandle;
+ EFI_HII_HANDLE HiiHandle;
+ RAS_CONFIG_VARSTORE_DATA Configuration;
//
// Consumed protocol
//
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
//
// Produced protocol
//
- EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
+ EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
} RAS_CONFIG_PRIVATE_DATA;
#define RAS_CONFIG_PRIVATE_FROM_THIS(a) CR (a, RAS_CONFIG_PRIVATE_DATA, ConfigAccess, RAS_CONFIG_PRIVATE_SIGNATURE)
@@ -52,8 +52,8 @@ typedef struct { /// HII specific Vendor Device Path definition.
///
typedef struct {
- VENDOR_DEVICE_PATH VendorDevicePath;
- EFI_DEVICE_PATH_PROTOCOL End;
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
} HII_VENDOR_DEVICE_PATH;
#pragma pack()
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigNVDataStruct.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigNVDataStruct.h index 8c528f043c..3a6f62bac3 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigNVDataStruct.h +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RasConfigDxe/RasConfigNVDataStruct.h @@ -9,10 +9,10 @@ #ifndef RAS_CONFIG_NV_DATA_STRUCT_H_
#define RAS_CONFIG_NV_DATA_STRUCT_H_
-#define RAS_CONFIG_VARSTORE_ID 0x1234
-#define RAS_CONFIG_FORM_ID 0x1235
+#define RAS_CONFIG_VARSTORE_ID 0x1234
+#define RAS_CONFIG_FORM_ID 0x1235
-#define RAS_VARSTORE_NAME L"RasConfigNVData"
+#define RAS_VARSTORE_NAME L"RasConfigNVData"
#define RAS_CONFIG_FORMSET_GUID \
{ \
@@ -22,8 +22,8 @@ //
// Labels definition
//
-#define LABEL_UPDATE 0x3234
-#define LABEL_END 0xffff
+#define LABEL_UPDATE 0x3234
+#define LABEL_END 0xffff
#pragma pack(1)
@@ -31,14 +31,14 @@ // Ras Configuration NV data structure definition
//
typedef struct {
- UINT32 RasHardwareEinj;
- UINT32 RasPcieAerFwFirstEnabled;
- UINT32 RasBertEnabled;
- UINT32 RasSdeiEnabled;
- UINT32 RasDdrCeThreshold;
- UINT32 Ras2pCeThreshold;
- UINT32 RasCpmCeThreshold;
- UINT32 RasLinkErrThreshold;
+ UINT32 RasHardwareEinj;
+ UINT32 RasPcieAerFwFirstEnabled;
+ UINT32 RasBertEnabled;
+ UINT32 RasSdeiEnabled;
+ UINT32 RasDdrCeThreshold;
+ UINT32 Ras2pCeThreshold;
+ UINT32 RasCpmCeThreshold;
+ UINT32 RasLinkErrThreshold;
} RAS_CONFIG_VARSTORE_DATA;
#pragma pack()
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.c index 9f2ec5b7ea..3ae6a9129e 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RngDxe/RngDxe.c @@ -38,12 +38,12 @@ EFI_STATUS
EFIAPI
RngGetInfo (
- IN EFI_RNG_PROTOCOL *This,
- IN OUT UINTN *RNGAlgorithmListSize,
- OUT EFI_RNG_ALGORITHM *RNGAlgorithmList
+ IN EFI_RNG_PROTOCOL *This,
+ IN OUT UINTN *RNGAlgorithmListSize,
+ OUT EFI_RNG_ALGORITHM *RNGAlgorithmList
)
{
- if (This == NULL || RNGAlgorithmListSize == NULL) {
+ if ((This == NULL) || (RNGAlgorithmListSize == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -85,22 +85,22 @@ RngGetInfo ( EFI_STATUS
EFIAPI
RngGetRNG (
- IN EFI_RNG_PROTOCOL *This,
+ IN EFI_RNG_PROTOCOL *This,
IN EFI_RNG_ALGORITHM *RNGAlgorithm, OPTIONAL
IN UINTN RNGValueLength,
OUT UINT8 *RNGValue
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
- if (This == NULL || RNGValueLength == 0 || RNGValue == NULL) {
+ if ((This == NULL) || (RNGValueLength == 0) || (RNGValue == NULL)) {
return EFI_INVALID_PARAMETER;
}
//
// We only support the raw algorithm, so reject requests for anything else
//
- if (RNGAlgorithm != NULL &&
+ if ((RNGAlgorithm != NULL) &&
!CompareGuid (RNGAlgorithm, &gEfiRngAlgorithmRaw))
{
return EFI_UNSUPPORTED;
@@ -123,7 +123,7 @@ RngGetRNG ( /*
* The Random Number Generator (RNG) protocol
*/
-EFI_RNG_PROTOCOL mRng = {
+EFI_RNG_PROTOCOL mRng = {
RngGetInfo,
RngGetRNG
};
@@ -142,12 +142,12 @@ EFI_RNG_PROTOCOL mRng = { EFI_STATUS
EFIAPI
RngDriverEntry (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- EFI_HANDLE Handle;
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
//
// Install UEFI RNG (Random Number Generator) Protocol
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.c b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.c index bc4812207f..a0892a7aab 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.c +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.c @@ -32,14 +32,14 @@ #include "RootComplexConfigDxe.h"
-BOOLEAN mReadOnlyStrongOrdering;
-CHAR16 mPcieNvparamVarstoreName[] = NVPARAM_VARSTORE_NAME;
-CHAR16 gPcieVarstoreName[] = ROOT_COMPLEX_CONFIG_VARSTORE_NAME;
-EFI_GUID gPcieFormSetGuid = ROOT_COMPLEX_CONFIG_FORMSET_GUID;
+BOOLEAN mReadOnlyStrongOrdering;
+CHAR16 mPcieNvparamVarstoreName[] = NVPARAM_VARSTORE_NAME;
+CHAR16 gPcieVarstoreName[] = ROOT_COMPLEX_CONFIG_VARSTORE_NAME;
+EFI_GUID gPcieFormSetGuid = ROOT_COMPLEX_CONFIG_FORMSET_GUID;
-SCREEN_PRIVATE_DATA *mPrivateData = NULL;
+SCREEN_PRIVATE_DATA *mPrivateData = NULL;
-HII_VENDOR_DEVICE_PATH mHiiVendorDevicePath = {
+HII_VENDOR_DEVICE_PATH mHiiVendorDevicePath = {
{
{
HARDWARE_DEVICE_PATH,
@@ -63,10 +63,10 @@ HII_VENDOR_DEVICE_PATH mHiiVendorDevicePath = { BOOLEAN
IsEmptyRC (
- IN AC01_ROOT_COMPLEX *RootComplex
+ IN AC01_ROOT_COMPLEX *RootComplex
)
{
- UINT8 Idx;
+ UINT8 Idx;
for (Idx = PcieController0; Idx < MaxPcieController; Idx++) {
if (RootComplex->Pcie[Idx].Active) {
@@ -79,11 +79,11 @@ IsEmptyRC ( AC01_ROOT_COMPLEX *
GetRootComplex (
- UINT8 Index
+ UINT8 Index
)
{
- AC01_ROOT_COMPLEX *RootComplexList;
- VOID *Hob;
+ AC01_ROOT_COMPLEX *RootComplexList;
+ VOID *Hob;
Hob = GetFirstGuidHob (&gRootComplexInfoHobGuid);
if (Hob == NULL) {
@@ -121,24 +121,24 @@ GetRootComplex ( EFI_STATUS
EFIAPI
ExtractConfig (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN CONST EFI_STRING Request,
- OUT EFI_STRING *Progress,
- OUT EFI_STRING *Results
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Request,
+ OUT EFI_STRING *Progress,
+ OUT EFI_STRING *Results
)
{
- EFI_STATUS Status;
- UINTN BufferSize;
- SCREEN_PRIVATE_DATA *PrivateData;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- EFI_STRING ConfigRequest;
- UINTN Size;
- CHAR16 *StrPointer;
- BOOLEAN AllocatedRequest;
- UINT8 *VarStoreConfig;
- UINT32 Value;
-
- if (Progress == NULL || Results == NULL) {
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ SCREEN_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_STRING ConfigRequest;
+ UINTN Size;
+ CHAR16 *StrPointer;
+ BOOLEAN AllocatedRequest;
+ UINT8 *VarStoreConfig;
+ UINT32 Value;
+
+ if ((Progress == NULL) || (Results == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -149,12 +149,12 @@ ExtractConfig ( //
// Initialize the local variables.
//
- ConfigRequest = NULL;
- Size = 0;
- *Progress = Request;
- AllocatedRequest = FALSE;
+ ConfigRequest = NULL;
+ Size = 0;
+ *Progress = Request;
+ AllocatedRequest = FALSE;
- PrivateData = SCREEN_PRIVATE_FROM_THIS (This);
+ PrivateData = SCREEN_PRIVATE_FROM_THIS (This);
HiiConfigRouting = PrivateData->HiiConfigRouting;
//
@@ -186,7 +186,6 @@ ExtractConfig ( }
BufferSize = sizeof (NVPARAM_ROOT_COMPLEX_CONFIG_VARSTORE_DATA);
-
} else if (HiiIsConfigHdrMatch (Request, &gPcieFormSetGuid, gPcieVarstoreName)) {
VarStoreConfig = (UINT8 *)&PrivateData->VarStoreConfig;
ASSERT (VarStoreConfig != NULL);
@@ -196,17 +195,16 @@ ExtractConfig ( // Try to get the current setting from variable.
//
BufferSize = sizeof (ROOT_COMPLEX_CONFIG_VARSTORE_DATA);
- Status = gRT->GetVariable (
- gPcieVarstoreName,
- &gPcieFormSetGuid,
- NULL,
- &BufferSize,
- VarStoreConfig
- );
+ Status = gRT->GetVariable (
+ gPcieVarstoreName,
+ &gPcieFormSetGuid,
+ NULL,
+ &BufferSize,
+ VarStoreConfig
+ );
if (EFI_ERROR (Status)) {
return EFI_NOT_FOUND;
}
-
} else {
return EFI_NOT_FOUND;
}
@@ -227,12 +225,13 @@ ExtractConfig ( if (StrPointer == NULL) {
return EFI_INVALID_PARAMETER;
}
+
if (StrStr (StrPointer, L"&") == NULL) {
//
// Allocate and fill a buffer large enough to hold the <ConfigHdr> template
// followed by "&OFFSET=0&WIDTH=WWWWWWWWWWWWWWWW" followed by a Null-terminator
//
- Size = (StrLen (Request) + 32 + 1) * sizeof (CHAR16);
+ Size = (StrLen (Request) + 32 + 1) * sizeof (CHAR16);
ConfigRequest = AllocateZeroPool (Size);
ASSERT (ConfigRequest != NULL);
AllocatedRequest = TRUE;
@@ -296,33 +295,34 @@ ExtractConfig ( EFI_STATUS
EFIAPI
RouteConfig (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN CONST EFI_STRING Configuration,
- OUT EFI_STRING *Progress
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN CONST EFI_STRING Configuration,
+ OUT EFI_STRING *Progress
)
{
- EFI_STATUS Status;
- UINTN BufferSize;
- SCREEN_PRIVATE_DATA *PrivateData;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- UINT8 *VarStoreConfig;
- UINT32 Value;
-
- if (Configuration == NULL || Progress == NULL) {
+ EFI_STATUS Status;
+ UINTN BufferSize;
+ SCREEN_PRIVATE_DATA *PrivateData;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ UINT8 *VarStoreConfig;
+ UINT32 Value;
+
+ if ((Configuration == NULL) || (Progress == NULL)) {
return EFI_INVALID_PARAMETER;
}
- PrivateData = SCREEN_PRIVATE_FROM_THIS (This);
+ PrivateData = SCREEN_PRIVATE_FROM_THIS (This);
HiiConfigRouting = PrivateData->HiiConfigRouting;
- *Progress = Configuration;
+ *Progress = Configuration;
if (HiiIsConfigHdrMatch (Configuration, &gPcieFormSetGuid, mPcieNvparamVarstoreName)) {
VarStoreConfig = (UINT8 *)&PrivateData->NVParamVarStoreConfig;
- BufferSize = sizeof (NVPARAM_ROOT_COMPLEX_CONFIG_VARSTORE_DATA);
+ BufferSize = sizeof (NVPARAM_ROOT_COMPLEX_CONFIG_VARSTORE_DATA);
} else if (HiiIsConfigHdrMatch (Configuration, &gPcieFormSetGuid, gPcieVarstoreName)) {
- BufferSize = sizeof (ROOT_COMPLEX_CONFIG_VARSTORE_DATA);
+ BufferSize = sizeof (ROOT_COMPLEX_CONFIG_VARSTORE_DATA);
VarStoreConfig = (UINT8 *)&PrivateData->VarStoreConfig;
}
+
ASSERT (VarStoreConfig != NULL);
//
@@ -420,16 +420,16 @@ RouteConfig ( EFI_STATUS
EFIAPI
DriverCallback (
- IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
- IN EFI_BROWSER_ACTION Action,
- IN EFI_QUESTION_ID QuestionId,
- IN UINT8 Type,
- IN EFI_IFR_TYPE_VALUE *Value,
- OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
+ IN CONST EFI_HII_CONFIG_ACCESS_PROTOCOL *This,
+ IN EFI_BROWSER_ACTION Action,
+ IN EFI_QUESTION_ID QuestionId,
+ IN UINT8 Type,
+ IN EFI_IFR_TYPE_VALUE *Value,
+ OUT EFI_BROWSER_ACTION_REQUEST *ActionRequest
)
{
- SCREEN_PRIVATE_DATA *PrivateData;
- EFI_STATUS Status;
+ SCREEN_PRIVATE_DATA *PrivateData;
+ EFI_STATUS Status;
if (((Value == NULL) &&
(Action != EFI_BROWSER_ACTION_FORM_OPEN) &&
@@ -444,53 +444,54 @@ DriverCallback ( Status = EFI_SUCCESS;
switch (Action) {
- case EFI_BROWSER_ACTION_FORM_OPEN:
- break;
-
- case EFI_BROWSER_ACTION_FORM_CLOSE:
- break;
-
- case EFI_BROWSER_ACTION_DEFAULT_STANDARD:
- case EFI_BROWSER_ACTION_DEFAULT_MANUFACTURING:
- if (QuestionId == SMMU_PMU_ID) {
- //
- // SMMU PMU
- //
- Value->u32 = 0;
+ case EFI_BROWSER_ACTION_FORM_OPEN:
break;
- }
- if (QuestionId == STRONG_ORDERING_ID) {
- //
- // Strong Ordering
- //
- Value->u8 = STRONG_ORDERING_DEFAULT_OPTION_VALUE;
+ case EFI_BROWSER_ACTION_FORM_CLOSE:
break;
- }
- switch ((QuestionId - 0x8002) % MAX_EDITABLE_ELEMENTS) {
- case 0:
- Value->u8 = PcieRCActiveDefaultSetting ((QuestionId - 0x8002) / MAX_EDITABLE_ELEMENTS, PrivateData);
- break;
+ case EFI_BROWSER_ACTION_DEFAULT_STANDARD:
+ case EFI_BROWSER_ACTION_DEFAULT_MANUFACTURING:
+ if (QuestionId == SMMU_PMU_ID) {
+ //
+ // SMMU PMU
+ //
+ Value->u32 = 0;
+ break;
+ }
- case 1:
- Value->u8 = PcieRCDevMapLowDefaultSetting ((QuestionId - 0x8002) / MAX_EDITABLE_ELEMENTS, PrivateData);
- break;
+ if (QuestionId == STRONG_ORDERING_ID) {
+ //
+ // Strong Ordering
+ //
+ Value->u8 = STRONG_ORDERING_DEFAULT_OPTION_VALUE;
+ break;
+ }
+
+ switch ((QuestionId - 0x8002) % MAX_EDITABLE_ELEMENTS) {
+ case 0:
+ Value->u8 = PcieRCActiveDefaultSetting ((QuestionId - 0x8002) / MAX_EDITABLE_ELEMENTS, PrivateData);
+ break;
+
+ case 1:
+ Value->u8 = PcieRCDevMapLowDefaultSetting ((QuestionId - 0x8002) / MAX_EDITABLE_ELEMENTS, PrivateData);
+ break;
+
+ case 2:
+ Value->u8 = PcieRCDevMapHighDefaultSetting ((QuestionId - 0x8002) / MAX_EDITABLE_ELEMENTS, PrivateData);
+ break;
+ }
- case 2:
- Value->u8 = PcieRCDevMapHighDefaultSetting ((QuestionId - 0x8002) / MAX_EDITABLE_ELEMENTS, PrivateData);
break;
- }
- break;
- case EFI_BROWSER_ACTION_RETRIEVE:
- case EFI_BROWSER_ACTION_CHANGING:
- case EFI_BROWSER_ACTION_SUBMITTED:
- break;
+ case EFI_BROWSER_ACTION_RETRIEVE:
+ case EFI_BROWSER_ACTION_CHANGING:
+ case EFI_BROWSER_ACTION_SUBMITTED:
+ break;
- default:
- Status = EFI_UNSUPPORTED;
- break;
+ default:
+ Status = EFI_UNSUPPORTED;
+ break;
}
return Status;
@@ -506,11 +507,11 @@ DriverCallback ( **/
UINT8
PcieRCDevMapLowDefaultSetting (
- IN UINTN RCIndex,
- IN SCREEN_PRIVATE_DATA *PrivateData
+ IN UINTN RCIndex,
+ IN SCREEN_PRIVATE_DATA *PrivateData
)
{
- AC01_ROOT_COMPLEX *RootComplex = GetRootComplex (RCIndex);
+ AC01_ROOT_COMPLEX *RootComplex = GetRootComplex (RCIndex);
return RootComplex->DefaultDevMapLow;
}
@@ -525,29 +526,29 @@ PcieRCDevMapLowDefaultSetting ( **/
UINT8
PcieRCDevMapHighDefaultSetting (
- IN UINTN RCIndex,
- IN SCREEN_PRIVATE_DATA *PrivateData
+ IN UINTN RCIndex,
+ IN SCREEN_PRIVATE_DATA *PrivateData
)
{
- AC01_ROOT_COMPLEX *RootComplex = GetRootComplex (RCIndex);
+ AC01_ROOT_COMPLEX *RootComplex = GetRootComplex (RCIndex);
return RootComplex->DefaultDevMapHigh;
}
BOOLEAN
PcieRCActiveDefaultSetting (
- IN UINTN RCIndex,
- IN SCREEN_PRIVATE_DATA *PrivateData
+ IN UINTN RCIndex,
+ IN SCREEN_PRIVATE_DATA *PrivateData
)
{
- AC01_ROOT_COMPLEX *RootComplex = GetRootComplex (RCIndex);
+ AC01_ROOT_COMPLEX *RootComplex = GetRootComplex (RCIndex);
return RootComplex->DefaultActive;
}
VOID *
CreateDevMapOptions (
- AC01_ROOT_COMPLEX *RootComplex
+ AC01_ROOT_COMPLEX *RootComplex
)
{
EFI_STRING_ID StringId;
@@ -557,8 +558,8 @@ CreateDevMapOptions ( ASSERT (OptionsOpCodeHandle != NULL);
StringId = RootComplex->Type == RootComplexTypeA ?
- STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE0) :
- STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE4);
+ STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE0) :
+ STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE4);
HiiCreateOneOfOptionOpCode (
OptionsOpCodeHandle,
StringId,
@@ -568,8 +569,8 @@ CreateDevMapOptions ( );
StringId = RootComplex->Type == RootComplexTypeA ?
- STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE1) :
- STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE5);
+ STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE1) :
+ STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE5);
HiiCreateOneOfOptionOpCode (
OptionsOpCodeHandle,
StringId,
@@ -579,8 +580,8 @@ CreateDevMapOptions ( );
StringId = RootComplex->Type == RootComplexTypeA ?
- STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE2) :
- STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE6);
+ STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE2) :
+ STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE6);
HiiCreateOneOfOptionOpCode (
OptionsOpCodeHandle,
StringId,
@@ -590,8 +591,8 @@ CreateDevMapOptions ( );
StringId = RootComplex->Type == RootComplexTypeA ?
- STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE3) :
- STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE7);
+ STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE3) :
+ STRING_TOKEN (STR_PCIE_BIFUR_SELECT_VALUE7);
HiiCreateOneOfOptionOpCode (
OptionsOpCodeHandle,
StringId,
@@ -622,21 +623,21 @@ CreateDevMapOptions ( **/
EFI_STATUS
PcieRCScreenSetup (
- IN UINTN RCIndex,
- IN SCREEN_PRIVATE_DATA *PrivateData
+ IN UINTN RCIndex,
+ IN SCREEN_PRIVATE_DATA *PrivateData
)
{
- AC01_ROOT_COMPLEX *RootComplex;
- CHAR16 Str[MAX_STRING_SIZE];
- EFI_IFR_GUID_LABEL *EndLabel;
- EFI_IFR_GUID_LABEL *StartLabel;
- UINT16 BifurHiVarOffset;
- UINT16 BifurLoVarOffset;
- UINT16 DisabledStatusVarOffset;
- UINT8 QuestionFlags, QuestionFlagsSubItem;
- VOID *EndOpCodeHandle;
- VOID *OptionsOpCodeHandle;
- VOID *StartOpCodeHandle;
+ AC01_ROOT_COMPLEX *RootComplex;
+ CHAR16 Str[MAX_STRING_SIZE];
+ EFI_IFR_GUID_LABEL *EndLabel;
+ EFI_IFR_GUID_LABEL *StartLabel;
+ UINT16 BifurHiVarOffset;
+ UINT16 BifurLoVarOffset;
+ UINT16 DisabledStatusVarOffset;
+ UINT8 QuestionFlags, QuestionFlagsSubItem;
+ VOID *EndOpCodeHandle;
+ VOID *OptionsOpCodeHandle;
+ VOID *StartOpCodeHandle;
RootComplex = GetRootComplex (RCIndex);
@@ -695,12 +696,12 @@ PcieRCScreenSetup ( UnicodeSPrint (Str, sizeof (Str), L"Root Complex #%2d", RCIndex);
DisabledStatusVarOffset = (UINT16)RC0_STATUS_OFFSET + sizeof (BOOLEAN) * RCIndex;
- BifurLoVarOffset = (UINT16)RC0_BIFUR_LO_OFFSET + sizeof (UINT8) * RCIndex;
- BifurHiVarOffset = (UINT16)RC0_BIFUR_HI_OFFSET + sizeof (UINT8) * RCIndex;
+ BifurLoVarOffset = (UINT16)RC0_BIFUR_LO_OFFSET + sizeof (UINT8) * RCIndex;
+ BifurHiVarOffset = (UINT16)RC0_BIFUR_HI_OFFSET + sizeof (UINT8) * RCIndex;
QuestionFlags = EFI_IFR_FLAG_RESET_REQUIRED | EFI_IFR_FLAG_CALLBACK;
- if (IsEmptyRC (RootComplex)
- || (GetNumberOfActiveSockets () == 1 && RootComplex->Socket == 1))
+ if ( IsEmptyRC (RootComplex)
+ || ((GetNumberOfActiveSockets () == 1) && (RootComplex->Socket == 1)))
{
//
// Do not allow changing if none of Root Port underneath enabled
@@ -733,8 +734,9 @@ PcieRCScreenSetup ( //
OptionsOpCodeHandle = CreateDevMapOptions (RootComplex);
- if ((RootComplex->DefaultDevMapLow != 0)
- && (RootComplex->DefaultDevMapLow != DevMapModeAuto)) {
+ if ( (RootComplex->DefaultDevMapLow != 0)
+ && (RootComplex->DefaultDevMapLow != DevMapModeAuto))
+ {
QuestionFlags |= EFI_IFR_FLAG_READ_ONLY;
}
@@ -793,7 +795,7 @@ PcieRCScreenSetup ( STRING_TOKEN (STR_PCIE_RCB_HI_BIFUR_HELP), // Question help text
QuestionFlagsSubItem, // Question flag
EFI_IFR_NUMERIC_SIZE_1, // Data type of Question Value
- OptionsOpCodeHandle, // Option Opcode list
+ OptionsOpCodeHandle, // Option Opcode list
NULL // Default Opcode is NULl
);
}
@@ -821,18 +823,18 @@ PcieRCScreenSetup ( **/
EFI_STATUS
PcieMainScreenSetup (
- IN SCREEN_PRIVATE_DATA *PrivateData
+ IN SCREEN_PRIVATE_DATA *PrivateData
)
{
- VOID *StartOpCodeHandle;
- EFI_IFR_GUID_LABEL *StartLabel;
- VOID *EndOpCodeHandle;
- EFI_IFR_GUID_LABEL *EndLabel;
- CHAR16 Str[MAX_STRING_SIZE];
- UINTN RootComplex;
- SETUP_GOTO_DATA *GotoItem = NULL;
- EFI_QUESTION_ID GotoId;
- UINT8 QuestionFlags;
+ VOID *StartOpCodeHandle;
+ EFI_IFR_GUID_LABEL *StartLabel;
+ VOID *EndOpCodeHandle;
+ EFI_IFR_GUID_LABEL *EndLabel;
+ CHAR16 Str[MAX_STRING_SIZE];
+ UINTN RootComplex;
+ SETUP_GOTO_DATA *GotoItem = NULL;
+ EFI_QUESTION_ID GotoId;
+ UINT8 QuestionFlags;
// Initialize the container for dynamic opcodes
StartOpCodeHandle = HiiAllocateOpCodeHandle ();
@@ -902,11 +904,11 @@ PcieMainScreenSetup ( // Create Goto form for each RootComplex
for (RootComplex = 0; RootComplex < AC01_PCIE_MAX_ROOT_COMPLEX; RootComplex++) {
-
GotoItem = AllocateZeroPool (sizeof (SETUP_GOTO_DATA));
if (GotoItem == NULL) {
return EFI_OUT_OF_RESOURCES;
}
+
GotoItem->PciDevIdx = RootComplex;
GotoId = GOTO_ID_BASE + (UINT16)RootComplex;
@@ -920,7 +922,7 @@ PcieMainScreenSetup ( NULL
);
GotoItem->GotoHelpStringId = STRING_TOKEN (STR_PCIE_GOTO_HELP);
- GotoItem->ShowItem = TRUE;
+ GotoItem->ShowItem = TRUE;
// Add goto control
HiiCreateGotoOpCode (
@@ -952,22 +954,22 @@ NVParamVarstoreInit ( VOID
)
{
- BOOLEAN BoardSettingValid;
- BOOLEAN UserSettingValid;
- BOOLEAN Update;
- EFI_STATUS Status;
- UINT32 UserValue;
- UINT32 InitValue;
+ BOOLEAN BoardSettingValid;
+ BOOLEAN UserSettingValid;
+ BOOLEAN Update;
+ EFI_STATUS Status;
+ UINT32 UserValue;
+ UINT32 InitValue;
mReadOnlyStrongOrdering = FALSE;
// S0
UserSettingValid = FALSE;
- Status = NVParamGet (
- NV_SI_MESH_S0_CXG_RC_STRONG_ORDERING_EN,
- NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
- &UserValue
- );
+ Status = NVParamGet (
+ NV_SI_MESH_S0_CXG_RC_STRONG_ORDERING_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &UserValue
+ );
if (!EFI_ERROR (Status)) {
UserSettingValid = TRUE;
}
@@ -976,21 +978,22 @@ NVParamVarstoreInit ( // InitValue will be default value or board setting value.
//
BoardSettingValid = FALSE;
- Status = NVParamGet (
- NV_SI_RO_BOARD_MESH_S0_CXG_RC_STRONG_ORDERING_EN,
- NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
- &InitValue
- );
- if (!EFI_ERROR (Status) && InitValue > 0) {
- BoardSettingValid = TRUE;
+ Status = NVParamGet (
+ NV_SI_RO_BOARD_MESH_S0_CXG_RC_STRONG_ORDERING_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &InitValue
+ );
+ if (!EFI_ERROR (Status) && (InitValue > 0)) {
+ BoardSettingValid = TRUE;
mReadOnlyStrongOrdering = TRUE;
} else {
InitValue = STRONG_ORDERING_DEFAULT_NVPARAM_VALUE;
}
Update = TRUE;
- if ((UserSettingValid && (UserValue == InitValue))
- || (!BoardSettingValid && UserSettingValid && (UserValue == 0))) {
+ if ( (UserSettingValid && (UserValue == InitValue))
+ || (!BoardSettingValid && UserSettingValid && (UserValue == 0)))
+ {
Update = FALSE;
}
@@ -1008,11 +1011,11 @@ NVParamVarstoreInit ( // No need to check slave present.
//
UserSettingValid = FALSE;
- Status = NVParamGet (
- NV_SI_MESH_S1_CXG_RC_STRONG_ORDERING_EN,
- NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
- &UserValue
- );
+ Status = NVParamGet (
+ NV_SI_MESH_S1_CXG_RC_STRONG_ORDERING_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &UserValue
+ );
if (!EFI_ERROR (Status)) {
UserSettingValid = TRUE;
}
@@ -1021,21 +1024,22 @@ NVParamVarstoreInit ( // InitValue will be default value or board setting value.
//
BoardSettingValid = FALSE;
- Status = NVParamGet (
- NV_SI_RO_BOARD_MESH_S1_CXG_RC_STRONG_ORDERING_EN,
- NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
- &InitValue
- );
- if (!EFI_ERROR (Status) && InitValue > 0) {
- BoardSettingValid = TRUE;
+ Status = NVParamGet (
+ NV_SI_RO_BOARD_MESH_S1_CXG_RC_STRONG_ORDERING_EN,
+ NV_PERM_ATF | NV_PERM_BIOS | NV_PERM_MANU | NV_PERM_BMC,
+ &InitValue
+ );
+ if (!EFI_ERROR (Status) && (InitValue > 0)) {
+ BoardSettingValid = TRUE;
mReadOnlyStrongOrdering = TRUE;
} else {
InitValue = STRONG_ORDERING_DEFAULT_NVPARAM_VALUE;
}
Update = TRUE;
- if ((UserSettingValid && (UserValue == InitValue))
- || (!BoardSettingValid && UserSettingValid && (UserValue == 0))) {
+ if ( (UserSettingValid && (UserValue == InitValue))
+ || (!BoardSettingValid && UserSettingValid && (UserValue == 0)))
+ {
Update = FALSE;
}
@@ -1064,18 +1068,18 @@ RootComplexDriverEntry ( IN EFI_SYSTEM_TABLE *SystemTable
)
{
- AC01_ROOT_COMPLEX *RootComplex;
- BOOLEAN IsUpdated;
- EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *HiiKeywordHandler;
- EFI_HANDLE DriverHandle;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- EFI_HII_DATABASE_PROTOCOL *HiiDatabase;
- EFI_HII_HANDLE HiiHandle;
- EFI_HII_STRING_PROTOCOL *HiiString;
- EFI_STATUS Status;
- ROOT_COMPLEX_CONFIG_VARSTORE_DATA *VarStoreConfig;
- UINT8 RCIndex;
- UINTN BufferSize;
+ AC01_ROOT_COMPLEX *RootComplex;
+ BOOLEAN IsUpdated;
+ EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *HiiKeywordHandler;
+ EFI_HANDLE DriverHandle;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_HII_DATABASE_PROTOCOL *HiiDatabase;
+ EFI_HII_HANDLE HiiHandle;
+ EFI_HII_STRING_PROTOCOL *HiiString;
+ EFI_STATUS Status;
+ ROOT_COMPLEX_CONFIG_VARSTORE_DATA *VarStoreConfig;
+ UINT8 RCIndex;
+ UINTN BufferSize;
//
// Initialize driver private data
@@ -1085,10 +1089,10 @@ RootComplexDriverEntry ( return EFI_OUT_OF_RESOURCES;
}
- mPrivateData->Signature = SCREEN_PRIVATE_DATA_SIGNATURE;
+ mPrivateData->Signature = SCREEN_PRIVATE_DATA_SIGNATURE;
mPrivateData->ConfigAccess.ExtractConfig = ExtractConfig;
- mPrivateData->ConfigAccess.RouteConfig = RouteConfig;
- mPrivateData->ConfigAccess.Callback = DriverCallback;
+ mPrivateData->ConfigAccess.RouteConfig = RouteConfig;
+ mPrivateData->ConfigAccess.Callback = DriverCallback;
//
// Locate Hii Database protocol
@@ -1101,6 +1105,7 @@ RootComplexDriverEntry ( if (EFI_ERROR (Status)) {
return Status;
}
+
mPrivateData->HiiDatabase = HiiDatabase;
//
@@ -1114,6 +1119,7 @@ RootComplexDriverEntry ( if (EFI_ERROR (Status)) {
return Status;
}
+
mPrivateData->HiiString = HiiString;
//
@@ -1127,6 +1133,7 @@ RootComplexDriverEntry ( if (EFI_ERROR (Status)) {
return Status;
}
+
mPrivateData->HiiConfigRouting = HiiConfigRouting;
//
@@ -1140,17 +1147,18 @@ RootComplexDriverEntry ( if (EFI_ERROR (Status)) {
return Status;
}
+
mPrivateData->HiiKeywordHandler = HiiKeywordHandler;
DriverHandle = NULL;
- Status = gBS->InstallMultipleProtocolInterfaces (
- &DriverHandle,
- &gEfiDevicePathProtocolGuid,
- &mHiiVendorDevicePath,
- &gEfiHiiConfigAccessProtocolGuid,
- &mPrivateData->ConfigAccess,
- NULL
- );
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &DriverHandle,
+ &gEfiDevicePathProtocolGuid,
+ &mHiiVendorDevicePath,
+ &gEfiHiiConfigAccessProtocolGuid,
+ &mPrivateData->ConfigAccess,
+ NULL
+ );
ASSERT_EFI_ERROR (Status);
mPrivateData->DriverHandle = DriverHandle;
@@ -1184,29 +1192,30 @@ RootComplexDriverEntry ( // Get Buffer Storage data from EFI variable
BufferSize = sizeof (ROOT_COMPLEX_CONFIG_VARSTORE_DATA);
- Status = gRT->GetVariable (
- gPcieVarstoreName,
- &gPcieFormSetGuid,
- NULL,
- &BufferSize,
- VarStoreConfig
- );
+ Status = gRT->GetVariable (
+ gPcieVarstoreName,
+ &gPcieFormSetGuid,
+ NULL,
+ &BufferSize,
+ VarStoreConfig
+ );
IsUpdated = FALSE;
if (EFI_ERROR (Status)) {
VarStoreConfig->SmmuPmu = 0; /* Disable by default */
- IsUpdated = TRUE;
+ IsUpdated = TRUE;
}
+
// Update board settings to menu
for (RCIndex = 0; RCIndex < AC01_PCIE_MAX_ROOT_COMPLEX; RCIndex++) {
RootComplex = GetRootComplex (RCIndex);
if (EFI_ERROR (Status)) {
- VarStoreConfig->RCBifurcationLow[RCIndex] = RootComplex->DefaultDevMapLow;
+ VarStoreConfig->RCBifurcationLow[RCIndex] = RootComplex->DefaultDevMapLow;
VarStoreConfig->RCBifurcationHigh[RCIndex] = RootComplex->DefaultDevMapHigh;
- VarStoreConfig->RCStatus[RCIndex] = RootComplex->Active;
- IsUpdated = TRUE;
+ VarStoreConfig->RCStatus[RCIndex] = RootComplex->Active;
+ IsUpdated = TRUE;
}
}
@@ -1225,6 +1234,7 @@ RootComplexDriverEntry ( return Status;
}
}
+
Status = PcieMainScreenSetup (mPrivateData);
ASSERT_EFI_ERROR (Status);
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.h index c02ee765a1..cf731c2266 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.h +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigDxe.h @@ -16,16 +16,16 @@ // This data array is ready to be used as input of HiiAddPackages() to
// create a packagelist (which contains Form packages, String packages, etc).
//
-extern UINT8 RootComplexConfigVfrBin[];
+extern UINT8 RootComplexConfigVfrBin[];
//
// This is the generated String package data for all .UNI files.
// This data array is ready to be used as input of HiiAddPackages() to
// create a packagelist (which contains Form packages, String packages, etc).
//
-extern UINT8 RootComplexConfigDxeStrings[];
+extern UINT8 RootComplexConfigDxeStrings[];
-#define MAX_EDITABLE_ELEMENTS 3
+#define MAX_EDITABLE_ELEMENTS 3
#define RC0_STATUS_OFFSET \
OFFSET_OF (ROOT_COMPLEX_CONFIG_VARSTORE_DATA, RCStatus[0])
#define RC0_BIFUR_LO_OFFSET \
@@ -41,41 +41,41 @@ extern UINT8 RootComplexConfigDxeStrings[]; //
// Signature: Ampere Computing PCIe Screen
//
-#define SCREEN_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('A', 'C', 'P', 'S')
+#define SCREEN_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('A', 'C', 'P', 'S')
-#define MAX_STRING_SIZE 32
+#define MAX_STRING_SIZE 32
-#define STRONG_ORDERING_DEFAULT_OPTION_VALUE 1
-#define STRONG_ORDERING_DEFAULT_NVPARAM_VALUE 0xFFFFFFFF
+#define STRONG_ORDERING_DEFAULT_OPTION_VALUE 1
+#define STRONG_ORDERING_DEFAULT_NVPARAM_VALUE 0xFFFFFFFF
typedef struct {
- UINTN Signature;
+ UINTN Signature;
- EFI_HANDLE DriverHandle;
- EFI_HII_HANDLE HiiHandle;
- ROOT_COMPLEX_CONFIG_VARSTORE_DATA VarStoreConfig;
- NVPARAM_ROOT_COMPLEX_CONFIG_VARSTORE_DATA NVParamVarStoreConfig;
+ EFI_HANDLE DriverHandle;
+ EFI_HII_HANDLE HiiHandle;
+ ROOT_COMPLEX_CONFIG_VARSTORE_DATA VarStoreConfig;
+ NVPARAM_ROOT_COMPLEX_CONFIG_VARSTORE_DATA NVParamVarStoreConfig;
//
// Consumed protocol
//
- EFI_HII_DATABASE_PROTOCOL *HiiDatabase;
- EFI_HII_STRING_PROTOCOL *HiiString;
- EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
- EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *HiiKeywordHandler;
+ EFI_HII_DATABASE_PROTOCOL *HiiDatabase;
+ EFI_HII_STRING_PROTOCOL *HiiString;
+ EFI_HII_CONFIG_ROUTING_PROTOCOL *HiiConfigRouting;
+ EFI_CONFIG_KEYWORD_HANDLER_PROTOCOL *HiiKeywordHandler;
//
// Produced protocol
//
- EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
+ EFI_HII_CONFIG_ACCESS_PROTOCOL ConfigAccess;
} SCREEN_PRIVATE_DATA;
typedef struct {
- UINTN PciDevIdx;
- EFI_STRING_ID GotoStringId;
- EFI_STRING_ID GotoHelpStringId;
- UINT16 GotoKey;
- BOOLEAN ShowItem;
+ UINTN PciDevIdx;
+ EFI_STRING_ID GotoStringId;
+ EFI_STRING_ID GotoHelpStringId;
+ UINT16 GotoKey;
+ BOOLEAN ShowItem;
} SETUP_GOTO_DATA;
#define SCREEN_PRIVATE_FROM_THIS(a) \
@@ -87,28 +87,28 @@ typedef struct { /// HII specific Vendor Device Path definition.
///
typedef struct {
- VENDOR_DEVICE_PATH VendorDevicePath;
- EFI_DEVICE_PATH_PROTOCOL End;
+ VENDOR_DEVICE_PATH VendorDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL End;
} HII_VENDOR_DEVICE_PATH;
#pragma pack()
UINT8
PcieRCDevMapLowDefaultSetting (
- IN UINTN RCIndex,
- IN SCREEN_PRIVATE_DATA *PrivateData
+ IN UINTN RCIndex,
+ IN SCREEN_PRIVATE_DATA *PrivateData
);
UINT8
PcieRCDevMapHighDefaultSetting (
- IN UINTN RCIndex,
- IN SCREEN_PRIVATE_DATA *PrivateData
+ IN UINTN RCIndex,
+ IN SCREEN_PRIVATE_DATA *PrivateData
);
BOOLEAN
PcieRCActiveDefaultSetting (
- IN UINTN RCIndex,
- IN SCREEN_PRIVATE_DATA *PrivateData
+ IN UINTN RCIndex,
+ IN SCREEN_PRIVATE_DATA *PrivateData
);
#endif /* BOARD_PCIE_SCREEN_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigNVDataStruct.h b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigNVDataStruct.h index 3350f6eb7f..805c431c0e 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigNVDataStruct.h +++ b/Silicon/Ampere/AmpereAltraPkg/Drivers/RootComplexConfigDxe/RootComplexConfigNVDataStruct.h @@ -11,30 +11,30 @@ #include <Platform/Ac01.h>
-#define VARSTORE_ID 0x1234
-#define FORM_ID 0x1235
-#define RC0_FORM_ID 0x1236
-#define RC1_FORM_ID 0x1237
-#define RC2_FORM_ID 0x1238
-#define RC3_FORM_ID 0x1239
-#define RC4_FORM_ID 0x123A
-#define RC5_FORM_ID 0x123B
-#define RC6_FORM_ID 0x123C
-#define RC7_FORM_ID 0x123D
-#define RC8_FORM_ID 0x123E
-#define RC9_FORM_ID 0x123F
-#define RC10_FORM_ID 0x1240
-#define RC11_FORM_ID 0x1241
-#define RC12_FORM_ID 0x1242
-#define RC13_FORM_ID 0x1243
-#define RC14_FORM_ID 0x1244
-#define RC15_FORM_ID 0x1245
+#define VARSTORE_ID 0x1234
+#define FORM_ID 0x1235
+#define RC0_FORM_ID 0x1236
+#define RC1_FORM_ID 0x1237
+#define RC2_FORM_ID 0x1238
+#define RC3_FORM_ID 0x1239
+#define RC4_FORM_ID 0x123A
+#define RC5_FORM_ID 0x123B
+#define RC6_FORM_ID 0x123C
+#define RC7_FORM_ID 0x123D
+#define RC8_FORM_ID 0x123E
+#define RC9_FORM_ID 0x123F
+#define RC10_FORM_ID 0x1240
+#define RC11_FORM_ID 0x1241
+#define RC12_FORM_ID 0x1242
+#define RC13_FORM_ID 0x1243
+#define RC14_FORM_ID 0x1244
+#define RC15_FORM_ID 0x1245
-#define QUESTION_ID_BASE 0x8002
-#define GOTO_ID_BASE 0x8040
+#define QUESTION_ID_BASE 0x8002
+#define GOTO_ID_BASE 0x8040
-#define SMMU_PMU_ID 0x9000
-#define STRONG_ORDERING_ID 0x9001
+#define SMMU_PMU_ID 0x9000
+#define STRONG_ORDERING_ID 0x9001
#define NVPARAM_VARSTORE_NAME L"PcieIfrNVParamData"
#define NVPARAM_VARSTORE_ID 0x1233
@@ -45,7 +45,7 @@ // NVParam data structure definition
//
typedef struct {
- BOOLEAN PcieStrongOrdering;
+ BOOLEAN PcieStrongOrdering;
} NVPARAM_ROOT_COMPLEX_CONFIG_VARSTORE_DATA;
#pragma pack()
@@ -53,39 +53,39 @@ typedef struct { //
// Labels definition
//
-#define LABEL_UPDATE 0x2223
-#define LABEL_END 0x2224
-#define LABEL_RC0_UPDATE 0x2225
-#define LABEL_RC0_END 0x2226
-#define LABEL_RC1_UPDATE 0x2227
-#define LABEL_RC1_END 0x2228
-#define LABEL_RC2_UPDATE 0x2229
-#define LABEL_RC2_END 0x222A
-#define LABEL_RC3_UPDATE 0x222B
-#define LABEL_RC3_END 0x222C
-#define LABEL_RC4_UPDATE 0x222D
-#define LABEL_RC4_END 0x222E
-#define LABEL_RC5_UPDATE 0x222F
-#define LABEL_RC5_END 0x2230
-#define LABEL_RC6_UPDATE 0x2231
-#define LABEL_RC6_END 0x2232
-#define LABEL_RC7_UPDATE 0x2233
-#define LABEL_RC7_END 0x2234
-#define LABEL_RC8_UPDATE 0x2235
-#define LABEL_RC8_END 0x2236
-#define LABEL_RC9_UPDATE 0x2237
-#define LABEL_RC9_END 0x2238
-#define LABEL_RC10_UPDATE 0x2239
-#define LABEL_RC10_END 0x223A
-#define LABEL_RC11_UPDATE 0x223B
-#define LABEL_RC11_END 0x223C
-#define LABEL_RC12_UPDATE 0x223D
-#define LABEL_RC12_END 0x223E
-#define LABEL_RC13_UPDATE 0x223F
-#define LABEL_RC13_END 0x2240
-#define LABEL_RC14_UPDATE 0x2241
-#define LABEL_RC14_END 0x2242
-#define LABEL_RC15_UPDATE 0x2243
-#define LABEL_RC15_END 0x2244
+#define LABEL_UPDATE 0x2223
+#define LABEL_END 0x2224
+#define LABEL_RC0_UPDATE 0x2225
+#define LABEL_RC0_END 0x2226
+#define LABEL_RC1_UPDATE 0x2227
+#define LABEL_RC1_END 0x2228
+#define LABEL_RC2_UPDATE 0x2229
+#define LABEL_RC2_END 0x222A
+#define LABEL_RC3_UPDATE 0x222B
+#define LABEL_RC3_END 0x222C
+#define LABEL_RC4_UPDATE 0x222D
+#define LABEL_RC4_END 0x222E
+#define LABEL_RC5_UPDATE 0x222F
+#define LABEL_RC5_END 0x2230
+#define LABEL_RC6_UPDATE 0x2231
+#define LABEL_RC6_END 0x2232
+#define LABEL_RC7_UPDATE 0x2233
+#define LABEL_RC7_END 0x2234
+#define LABEL_RC8_UPDATE 0x2235
+#define LABEL_RC8_END 0x2236
+#define LABEL_RC9_UPDATE 0x2237
+#define LABEL_RC9_END 0x2238
+#define LABEL_RC10_UPDATE 0x2239
+#define LABEL_RC10_END 0x223A
+#define LABEL_RC11_UPDATE 0x223B
+#define LABEL_RC11_END 0x223C
+#define LABEL_RC12_UPDATE 0x223D
+#define LABEL_RC12_END 0x223E
+#define LABEL_RC13_UPDATE 0x223F
+#define LABEL_RC13_END 0x2240
+#define LABEL_RC14_UPDATE 0x2241
+#define LABEL_RC14_END 0x2242
+#define LABEL_RC15_UPDATE 0x2243
+#define LABEL_RC15_END 0x2244
#endif /* BOARD_PCIE_VFR_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/AcpiConfigNVDataStruct.h b/Silicon/Ampere/AmpereAltraPkg/Include/AcpiConfigNVDataStruct.h index 58574015c6..5acca29100 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/AcpiConfigNVDataStruct.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/AcpiConfigNVDataStruct.h @@ -15,10 +15,10 @@ // ACPI Configuration NV data structure definition
//
typedef struct {
- UINT32 EnableApeiSupport;
- UINT32 AcpiCppcEnable;
- UINT32 AcpiLpiEnable;
- UINT32 Reserved[6];
+ UINT32 EnableApeiSupport;
+ UINT32 AcpiCppcEnable;
+ UINT32 AcpiLpiEnable;
+ UINT32 Reserved[6];
} ACPI_CONFIG_VARSTORE_DATA;
#pragma pack()
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/AcpiHeader.h b/Silicon/Ampere/AmpereAltraPkg/Include/AcpiHeader.h index d604b712d8..6ec7b5c811 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/AcpiHeader.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/AcpiHeader.h @@ -14,15 +14,15 @@ //
// ACPI table information used to initialize tables.
//
-#define EFI_ACPI_OEM_ID {'A','m','p','e','r','e'}
-#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('A','l','t','r','a',' ',' ',' ')
-#define EFI_ACPI_OEM_REVISION FixedPcdGet32 (PcdAcpiDefaultOemRevision)
-#define EFI_ACPI_CREATOR_ID SIGNATURE_32('A','M','P','.')
-#define EFI_ACPI_CREATOR_REVISION FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)
+#define EFI_ACPI_OEM_ID {'A','m','p','e','r','e'}
+#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('A','l','t','r','a',' ',' ',' ')
+#define EFI_ACPI_OEM_REVISION FixedPcdGet32 (PcdAcpiDefaultOemRevision)
+#define EFI_ACPI_CREATOR_ID SIGNATURE_32('A','M','P','.')
+#define EFI_ACPI_CREATOR_REVISION FixedPcdGet32 (PcdAcpiDefaultCreatorRevision)
// A macro to initialise the common header part of EFI ACPI tables as defined by
// EFI_ACPI_DESCRIPTION_HEADER structure.
-#define __ACPI_HEADER(Signature, Type, Revision) { \
+#define __ACPI_HEADER(Signature, Type, Revision) { \
Signature, /* UINT32 Signature */ \
sizeof (Type), /* UINT32 Length */ \
Revision, /* UINT8 Revision */ \
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/CpuConfigNVDataStruc.h b/Silicon/Ampere/AmpereAltraPkg/Include/CpuConfigNVDataStruc.h index 2341d0aad7..6115cfd81b 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/CpuConfigNVDataStruc.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/CpuConfigNVDataStruc.h @@ -9,21 +9,21 @@ #ifndef CPU_CONFIG_NV_DATA_STRUC_H_
#define CPU_CONFIG_NV_DATA_STRUC_H_
-#define CPU_SUBNUMA_MODE_MONO 0x00
-#define CPU_SUBNUMA_MODE_HEMI 0x01
-#define CPU_SUBNUMA_MODE_QUAD 0x02
+#define CPU_SUBNUMA_MODE_MONO 0x00
+#define CPU_SUBNUMA_MODE_HEMI 0x01
+#define CPU_SUBNUMA_MODE_QUAD 0x02
-#define CPU_SLC_AS_L3_ENABLE 0x00
-#define CPU_SLC_AS_L3_DISABLE 0x01
+#define CPU_SLC_AS_L3_ENABLE 0x00
+#define CPU_SLC_AS_L3_DISABLE 0x01
-#define CPU_SLC_AS_L3_PERMITTED_YES 0x00
-#define CPU_SLC_AS_L3_PERMITTED_NO 0x01
+#define CPU_SLC_AS_L3_PERMITTED_YES 0x00
+#define CPU_SLC_AS_L3_PERMITTED_NO 0x01
#pragma pack(1)
typedef struct {
- UINT32 CpuSubNumaMode;
- UINT32 CpuSlcAsL3Permitted;
- UINT32 CpuSlcAsL3;
+ UINT32 CpuSubNumaMode;
+ UINT32 CpuSlcAsL3Permitted;
+ UINT32 CpuSlcAsL3;
} CPU_VARSTORE_DATA;
#pragma pack()
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/AcpiConfigHii.h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/AcpiConfigHii.h index 1779a45437..583a69c9cf 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/AcpiConfigHii.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/AcpiConfigHii.h @@ -14,6 +14,6 @@ 0x0ceb6764, 0xd415, 0x4b01, { 0xa8, 0x43, 0xd1, 0x01, 0xbc, 0xb0, 0xd8, 0x29 } \
}
-extern EFI_GUID gAcpiConfigFormSetGuid;
+extern EFI_GUID gAcpiConfigFormSetGuid;
#endif /* ACPI_CONFIG_FORMSET_GUID_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/CpuConfigHii.h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/CpuConfigHii.h index 71c8492f76..a84dd61065 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/CpuConfigHii.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/CpuConfigHii.h @@ -14,6 +14,6 @@ 0x43FAA144, 0xA2DF, 0x4050, { 0xA7, 0xFD, 0xEE, 0x17, 0xC9, 0xB8, 0x88, 0x8E } \
}
-extern EFI_GUID gCpuConfigFormSetGuid;
+extern EFI_GUID gCpuConfigFormSetGuid;
#endif /* CPU_CONFIG_HII_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/PlatformInfoHob.h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/PlatformInfoHob.h index 9c088c01fc..42cfeec33d 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/PlatformInfoHob.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/PlatformInfoHob.h @@ -15,7 +15,7 @@ #define PLATFORM_INFO_HOB_GUID \
{ 0x7f73e372, 0x7183, 0x4022, { 0xb3, 0x76, 0x78, 0x30, 0x32, 0x6d, 0x79, 0xb4 } }
-extern EFI_GUID gPlatformInfoHobGuid;
+extern EFI_GUID gPlatformInfoHobGuid;
//
// DIMM type
@@ -30,52 +30,52 @@ extern EFI_GUID gPlatformInfoHobGuid; //
// DIMM status
//
-#define DIMM_NOT_INSTALLED 0x00
-#define DIMM_INSTALLED_OPERATIONAL 0x01 // installed and operational
-#define DIMM_INSTALLED_NONOPERATIONAL 0x02 // installed and non-operational
-#define DIMM_INSTALLED_FAILED 0x03 // installed and failed
+#define DIMM_NOT_INSTALLED 0x00
+#define DIMM_INSTALLED_OPERATIONAL 0x01 // installed and operational
+#define DIMM_INSTALLED_NONOPERATIONAL 0x02 // installed and non-operational
+#define DIMM_INSTALLED_FAILED 0x03 // installed and failed
typedef struct {
- UINT32 NumRegion;
- UINT64 TotalSize;
- UINT64 Base[PLATFORM_DRAM_INFO_MAX_REGION];
- UINT64 Size[PLATFORM_DRAM_INFO_MAX_REGION];
- UINT64 Node[PLATFORM_DRAM_INFO_MAX_REGION];
- UINT64 Socket[PLATFORM_DRAM_INFO_MAX_REGION];
- UINT32 MaxSpeed;
- UINT32 McuMask[PLATFORM_CPU_MAX_SOCKET];
- UINT32 NvdRegion[PLATFORM_DRAM_INFO_MAX_REGION];
- UINT32 NvdimmMode[PLATFORM_CPU_MAX_SOCKET];
+ UINT32 NumRegion;
+ UINT64 TotalSize;
+ UINT64 Base[PLATFORM_DRAM_INFO_MAX_REGION];
+ UINT64 Size[PLATFORM_DRAM_INFO_MAX_REGION];
+ UINT64 Node[PLATFORM_DRAM_INFO_MAX_REGION];
+ UINT64 Socket[PLATFORM_DRAM_INFO_MAX_REGION];
+ UINT32 MaxSpeed;
+ UINT32 McuMask[PLATFORM_CPU_MAX_SOCKET];
+ UINT32 NvdRegion[PLATFORM_DRAM_INFO_MAX_REGION];
+ UINT32 NvdimmMode[PLATFORM_CPU_MAX_SOCKET];
} PLATFORM_DRAM_INFO;
typedef struct {
- CHAR8 PartNumber[32];
- UINT64 DimmSize;
- UINT16 DimmMfcId;
- UINT16 Reserved;
- UINT8 DimmNrRank;
- UINT8 DimmType;
- UINT8 DimmStatus;
- UINT8 DimmDevType;
+ CHAR8 PartNumber[32];
+ UINT64 DimmSize;
+ UINT16 DimmMfcId;
+ UINT16 Reserved;
+ UINT8 DimmNrRank;
+ UINT8 DimmType;
+ UINT8 DimmStatus;
+ UINT8 DimmDevType;
} PLATFORM_DIMM_INFO;
typedef struct {
- UINT8 Data[512];
+ UINT8 Data[512];
} PLATFORM_DIMM_SPD_DATA;
typedef struct {
- PLATFORM_DIMM_INFO Info;
- PLATFORM_DIMM_SPD_DATA SpdData;
- UINT32 NodeId;
+ PLATFORM_DIMM_INFO Info;
+ PLATFORM_DIMM_SPD_DATA SpdData;
+ UINT32 NodeId;
} PLATFORM_DIMM;
typedef struct {
- UINT32 BoardDimmSlots;
- PLATFORM_DIMM Dimm[PLATFORM_DIMM_INFO_MAX_SLOT];
+ UINT32 BoardDimmSlots;
+ PLATFORM_DIMM Dimm[PLATFORM_DIMM_INFO_MAX_SLOT];
} PLATFORM_DIMM_LIST;
typedef struct {
- UINT32 EnableMask[4];
+ UINT32 EnableMask[4];
} PLATFORM_CLUSTER_EN;
//
@@ -91,101 +91,101 @@ typedef enum { // Platform digest data definition
//
typedef union {
- unsigned char Sha1[SHA1_DIGEST_SIZE];
- unsigned char Sha256[SHA256_DIGEST_SIZE];
+ unsigned char Sha1[SHA1_DIGEST_SIZE];
+ unsigned char Sha256[SHA256_DIGEST_SIZE];
} PLATFORM_TPM_DIGEST;
-#define MAX_VIRTUAL_PCR_INDEX 0x0002
+#define MAX_VIRTUAL_PCR_INDEX 0x0002
#pragma pack(1)
typedef struct {
- PLATFORM_ALGORITHM_ID AlgorithmId;
+ PLATFORM_ALGORITHM_ID AlgorithmId;
struct {
- PLATFORM_TPM_DIGEST Hash;
+ PLATFORM_TPM_DIGEST Hash;
} VPcr[MAX_VIRTUAL_PCR_INDEX]; // vPCR 0 or 1
} PLATFORM_VPCR_HASH_INFO;
typedef struct {
- UINT8 InterfaceType; // If I/F is CRB then CRB parameters are expected
- UINT64 InterfaceParametersAddress; // Physical address of interface, by Value */
- UINT64 InterfaceParametersLength;
- UINT32 SupportedAlgorithmsBitMask;
- UINT64 EventLogAddress;
- UINT64 EventLogLength;
- UINT8 Reserved[3];
+ UINT8 InterfaceType; // If I/F is CRB then CRB parameters are expected
+ UINT64 InterfaceParametersAddress; // Physical address of interface, by Value */
+ UINT64 InterfaceParametersLength;
+ UINT32 SupportedAlgorithmsBitMask;
+ UINT64 EventLogAddress;
+ UINT64 EventLogLength;
+ UINT8 Reserved[3];
} PLATFORM_TPM2_CONFIG_DATA;
typedef struct {
- UINT32 CurrentRequest;
- UINT32 LastRequest;
- UINT32 LastRequestStatus;
+ UINT32 CurrentRequest;
+ UINT32 LastRequest;
+ UINT32 LastRequestStatus;
} PLATFORM_TPM2_PPI_REQUEST;
typedef struct {
- UINT64 AddressOfControlArea;
- UINT64 ControlAreaLength;
- UINT8 InterruptMode;
- UINT8 Reserved[3];
- UINT32 InterruptNumber; // Should have a value of zero polling
- UINT32 SmcFunctionId; // SMC Function ID
- UINT64 PpiRequestNotifyAddress; // Doorbell/Interrupt Address
- PLATFORM_TPM2_PPI_REQUEST *PpiRequest; // PPI Request
+ UINT64 AddressOfControlArea;
+ UINT64 ControlAreaLength;
+ UINT8 InterruptMode;
+ UINT8 Reserved[3];
+ UINT32 InterruptNumber; // Should have a value of zero polling
+ UINT32 SmcFunctionId; // SMC Function ID
+ UINT64 PpiRequestNotifyAddress; // Doorbell/Interrupt Address
+ PLATFORM_TPM2_PPI_REQUEST *PpiRequest; // PPI Request
} PLATFORM_TPM2_CRB_INTERFACE_PARAMETERS;
typedef struct {
- PLATFORM_TPM2_CONFIG_DATA Tpm2ConfigData;
- PLATFORM_TPM2_CRB_INTERFACE_PARAMETERS Tpm2CrbInterfaceParams;
- PLATFORM_VPCR_HASH_INFO Tpm2VPcrHashInfo;
+ PLATFORM_TPM2_CONFIG_DATA Tpm2ConfigData;
+ PLATFORM_TPM2_CRB_INTERFACE_PARAMETERS Tpm2CrbInterfaceParams;
+ PLATFORM_VPCR_HASH_INFO Tpm2VPcrHashInfo;
} PLATFORM_TPM2_INFO;
#pragma pack()
typedef struct {
- UINT8 MajorNumber;
- UINT8 MinorNumber;
- UINT64 PcpClk;
- UINT64 CpuClk;
- UINT64 SocClk;
- UINT64 AhbClk;
- UINT64 SysClk;
- UINT8 CpuInfo[128];
- UINT8 CpuVer[32];
- UINT8 SmPmProVer[32];
- UINT8 SmPmProBuild[32];
- PLATFORM_DRAM_INFO DramInfo;
- PLATFORM_DIMM_LIST DimmList;
- PLATFORM_CLUSTER_EN ClusterEn[2];
- UINT32 FailSafeStatus;
- UINT32 RcDisableMask[2];
- UINT8 ResetStatus;
- UINT16 CoreVoltage[2];
- UINT16 SocVoltage[2];
- UINT16 Dimm1Voltage[2];
- UINT16 Dimm2Voltage[2];
+ UINT8 MajorNumber;
+ UINT8 MinorNumber;
+ UINT64 PcpClk;
+ UINT64 CpuClk;
+ UINT64 SocClk;
+ UINT64 AhbClk;
+ UINT64 SysClk;
+ UINT8 CpuInfo[128];
+ UINT8 CpuVer[32];
+ UINT8 SmPmProVer[32];
+ UINT8 SmPmProBuild[32];
+ PLATFORM_DRAM_INFO DramInfo;
+ PLATFORM_DIMM_LIST DimmList;
+ PLATFORM_CLUSTER_EN ClusterEn[2];
+ UINT32 FailSafeStatus;
+ UINT32 RcDisableMask[2];
+ UINT8 ResetStatus;
+ UINT16 CoreVoltage[2];
+ UINT16 SocVoltage[2];
+ UINT16 Dimm1Voltage[2];
+ UINT16 Dimm2Voltage[2];
/* Chip information */
- UINT32 ScuProductId[2];
- UINT8 MaxNumOfCore[2];
- UINT8 Warranty[2];
- UINT8 SubNumaMode[2];
- UINT8 AvsEnable[2];
- UINT32 AvsVoltageMV[2];
- UINT8 TurboCapability[2];
- UINT32 TurboFrequency[2];
-
- UINT8 SkuMaxTurbo[2];
- UINT8 SkuMaxCore[2];
- UINT32 AHBCId[2];
+ UINT32 ScuProductId[2];
+ UINT8 MaxNumOfCore[2];
+ UINT8 Warranty[2];
+ UINT8 SubNumaMode[2];
+ UINT8 AvsEnable[2];
+ UINT32 AvsVoltageMV[2];
+ UINT8 TurboCapability[2];
+ UINT32 TurboFrequency[2];
+
+ UINT8 SkuMaxTurbo[2];
+ UINT8 SkuMaxCore[2];
+ UINT32 AHBCId[2];
/* TPM2 Info */
- PLATFORM_TPM2_INFO Tpm2Info;
+ PLATFORM_TPM2_INFO Tpm2Info;
/* 2P link info for RCA0/RCA1 */
- UINT8 Link2PSpeed[2];
- UINT8 Link2PWidth[2];
+ UINT8 Link2PSpeed[2];
+ UINT8 Link2PWidth[2];
- UINT32 Ecid[2][4];
- UINT8 SkuMaxLink2pSpeed;
- UINT8 VdmCapability[2];
+ UINT32 Ecid[2][4];
+ UINT8 SkuMaxLink2pSpeed;
+ UINT8 VdmCapability[2];
} PLATFORM_INFO_HOB;
#endif /* PLATFORM_INFO_HOB_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexConfigHii.h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexConfigHii.h index d82604cdf8..e2a4b45476 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexConfigHii.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexConfigHii.h @@ -16,18 +16,18 @@ 0xE84E70D6, 0xE4B2, 0x4C6E, { 0x98, 0x51, 0xCB, 0x2B, 0xAC, 0x77, 0x7D, 0xBB } \
}
-extern EFI_GUID gRootComplexConfigFormSetGuid;
+extern EFI_GUID gRootComplexConfigFormSetGuid;
//
// NV data structure definition
//
typedef struct {
- BOOLEAN RCStatus[AC01_PCIE_MAX_ROOT_COMPLEX];
- UINT8 RCBifurcationLow[AC01_PCIE_MAX_ROOT_COMPLEX];
- UINT8 RCBifurcationHigh[AC01_PCIE_MAX_ROOT_COMPLEX];
- UINT32 SmmuPmu;
+ BOOLEAN RCStatus[AC01_PCIE_MAX_ROOT_COMPLEX];
+ UINT8 RCBifurcationLow[AC01_PCIE_MAX_ROOT_COMPLEX];
+ UINT8 RCBifurcationHigh[AC01_PCIE_MAX_ROOT_COMPLEX];
+ UINT32 SmmuPmu;
} ROOT_COMPLEX_CONFIG_VARSTORE_DATA;
-#define ROOT_COMPLEX_CONFIG_VARSTORE_NAME L"PcieIfrNVData"
+#define ROOT_COMPLEX_CONFIG_VARSTORE_NAME L"PcieIfrNVData"
#endif /* ROOT_COMPLEX_CONFIG_HII_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h index 0b252de37d..daa914dbfb 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Guid/RootComplexInfoHob.h @@ -12,28 +12,28 @@ #define ROOT_COMPLEX_INFO_HOB_GUID \
{ 0x568a258a, 0xcaa1, 0x47e9, { 0xbb, 0x89, 0x65, 0xa3, 0x73, 0x9b, 0x58, 0x75 } }
-extern GUID gRootComplexInfoHobGuid;
+extern GUID gRootComplexInfoHobGuid;
-#define PRESET_INVALID 0xFF
+#define PRESET_INVALID 0xFF
//
// PCIe link width
//
-#define LINK_WIDTH_NONE 0x00
-#define LINK_WIDTH_X1 0x01
-#define LINK_WIDTH_X2 0x02
-#define LINK_WIDTH_X4 0x04
-#define LINK_WIDTH_X8 0x08
-#define LINK_WIDTH_X16 0x10
+#define LINK_WIDTH_NONE 0x00
+#define LINK_WIDTH_X1 0x01
+#define LINK_WIDTH_X2 0x02
+#define LINK_WIDTH_X4 0x04
+#define LINK_WIDTH_X8 0x08
+#define LINK_WIDTH_X16 0x10
//
// PCIe link speed
//
-#define LINK_SPEED_NONE 0x00
-#define LINK_SPEED_GEN1 0x01
-#define LINK_SPEED_GEN2 0x02
-#define LINK_SPEED_GEN3 0x04
-#define LINK_SPEED_GEN4 0x08
+#define LINK_SPEED_NONE 0x00
+#define LINK_SPEED_GEN1 0x01
+#define LINK_SPEED_GEN2 0x02
+#define LINK_SPEED_GEN3 0x04
+#define LINK_SPEED_GEN4 0x08
typedef enum {
DevMapMode1 = 0,
@@ -93,47 +93,47 @@ typedef enum { // Data structure to store the PCIe controller information
//
typedef struct {
- PHYSICAL_ADDRESS CsrBase; // Base address of CSR block
- PHYSICAL_ADDRESS SnpsRamBase; // Base address of Synopsys SRAM
- UINT8 MaxGen; // Max speed Gen-1/-2/-3/-4
- UINT8 CurrentGen; // Current speed Gen-1/-2/-3/-4
- UINT8 MaxWidth; // Max lanes x2/x4/x8/x16
- UINT8 CurWidth; // Current lanes x2/x4/x8/x16
- UINT8 ID; // ID of the controller within Root Complex
- UINT8 DevNum; // Device number as part of Bus:Dev:Func
- BOOLEAN Active; // Active? Used in bi-furcation mode
- BOOLEAN LinkUp; // PHY and PCIE linkup
- BOOLEAN HotPlug; // Hotplug support
+ PHYSICAL_ADDRESS CsrBase; // Base address of CSR block
+ PHYSICAL_ADDRESS SnpsRamBase; // Base address of Synopsys SRAM
+ UINT8 MaxGen; // Max speed Gen-1/-2/-3/-4
+ UINT8 CurrentGen; // Current speed Gen-1/-2/-3/-4
+ UINT8 MaxWidth; // Max lanes x2/x4/x8/x16
+ UINT8 CurWidth; // Current lanes x2/x4/x8/x16
+ UINT8 ID; // ID of the controller within Root Complex
+ UINT8 DevNum; // Device number as part of Bus:Dev:Func
+ BOOLEAN Active; // Active? Used in bi-furcation mode
+ BOOLEAN LinkUp; // PHY and PCIE linkup
+ BOOLEAN HotPlug; // Hotplug support
} AC01_PCIE_CONTROLLER;
//
// Data structure to store the Root Complex information
//
typedef struct {
- PHYSICAL_ADDRESS CsrBase;
- PHYSICAL_ADDRESS TcuBase;
- PHYSICAL_ADDRESS HostBridgeBase;
- PHYSICAL_ADDRESS SerdesBase;
- PHYSICAL_ADDRESS MmcfgBase;
- PHYSICAL_ADDRESS MmioBase;
- PHYSICAL_ADDRESS MmioSize;
- PHYSICAL_ADDRESS Mmio32Base;
- PHYSICAL_ADDRESS Mmio32Size;
- AC01_PCIE_CONTROLLER Pcie[MaxPcieController];
- UINT8 MaxPcieController;
- AC01_ROOT_COMPLEX_TYPE Type;
- UINT8 ID;
- DEV_MAP_MODE DevMapHigh:3; // Copy of High Devmap programmed to Host bridge
- DEV_MAP_MODE DevMapLow:3; // Copy of Low Devmap programmed to Host bridge
- DEV_MAP_MODE DefaultDevMapHigh:3; // Default of High devmap based on board settings
- DEV_MAP_MODE DefaultDevMapLow:3; // Default of Low devmap based on board settings
- UINT8 Socket;
- BOOLEAN Active;
- BOOLEAN DefaultActive;
- UINT16 Logical;
- UINT32 Flags;
- UINT8 PresetGen3[MaxPcieController];
- UINT8 PresetGen4[MaxPcieController];
+ PHYSICAL_ADDRESS CsrBase;
+ PHYSICAL_ADDRESS TcuBase;
+ PHYSICAL_ADDRESS HostBridgeBase;
+ PHYSICAL_ADDRESS SerdesBase;
+ PHYSICAL_ADDRESS MmcfgBase;
+ PHYSICAL_ADDRESS MmioBase;
+ PHYSICAL_ADDRESS MmioSize;
+ PHYSICAL_ADDRESS Mmio32Base;
+ PHYSICAL_ADDRESS Mmio32Size;
+ AC01_PCIE_CONTROLLER Pcie[MaxPcieController];
+ UINT8 MaxPcieController;
+ AC01_ROOT_COMPLEX_TYPE Type;
+ UINT8 ID;
+ DEV_MAP_MODE DevMapHigh : 3; // Copy of High Devmap programmed to Host bridge
+ DEV_MAP_MODE DevMapLow : 3; // Copy of Low Devmap programmed to Host bridge
+ DEV_MAP_MODE DefaultDevMapHigh : 3; // Default of High devmap based on board settings
+ DEV_MAP_MODE DefaultDevMapLow : 3; // Default of Low devmap based on board settings
+ UINT8 Socket;
+ BOOLEAN Active;
+ BOOLEAN DefaultActive;
+ UINT16 Logical;
+ UINT32 Flags;
+ UINT8 PresetGen3[MaxPcieController];
+ UINT8 PresetGen4[MaxPcieController];
} AC01_ROOT_COMPLEX;
#pragma pack()
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/Ac01PcieLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/Ac01PcieLib.h index 692bc26699..9eef4acdaf 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Library/Ac01PcieLib.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/Ac01PcieLib.h @@ -21,9 +21,9 @@ **/
RETURN_STATUS
Ac01PcieCoreSetupRC (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN BOOLEAN ReInit,
- IN UINT8 ReInitPcieIndex
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN BOOLEAN ReInit,
+ IN UINT8 ReInitPcieIndex
);
/**
@@ -33,7 +33,7 @@ Ac01PcieCoreSetupRC ( **/
VOID
Ac01PcieCorePostSetupRC (
- IN AC01_ROOT_COMPLEX *RootComplexList
+ IN AC01_ROOT_COMPLEX *RootComplexList
);
/**
@@ -43,7 +43,7 @@ Ac01PcieCorePostSetupRC ( **/
VOID
Ac01PcieCoreEndEnumeration (
- IN AC01_ROOT_COMPLEX *RootComplex
+ IN AC01_ROOT_COMPLEX *RootComplex
);
#endif /* AC01_PCIE_LIB_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h index 2f186d2466..087dcb8f78 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/AmpereCpuLib.h @@ -11,19 +11,19 @@ #ifndef AMPERE_CPU_LIB_H_
#define AMPERE_CPU_LIB_H_
-#define SUBNUMA_MODE_MONOLITHIC 0
-#define SUBNUMA_MODE_HEMISPHERE 1
-#define SUBNUMA_MODE_QUADRANT 2
+#define SUBNUMA_MODE_MONOLITHIC 0
+#define SUBNUMA_MODE_HEMISPHERE 1
+#define SUBNUMA_MODE_QUADRANT 2
-#define MONOLITIC_NUM_OF_REGION 1
-#define HEMISPHERE_NUM_OF_REGION 2
-#define QUADRANT_NUM_OF_REGION 4
+#define MONOLITIC_NUM_OF_REGION 1
+#define HEMISPHERE_NUM_OF_REGION 2
+#define QUADRANT_NUM_OF_REGION 4
-#define SOCKET_ID(CpuId) ((CpuId) / (PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM))
-#define CLUSTER_ID(CpuId) (((CpuId) / PLATFORM_CPU_NUM_CORES_PER_CPM) % PLATFORM_CPU_MAX_CPM)
+#define SOCKET_ID(CpuId) ((CpuId) / (PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM))
+#define CLUSTER_ID(CpuId) (((CpuId) / PLATFORM_CPU_NUM_CORES_PER_CPM) % PLATFORM_CPU_MAX_CPM)
-#define MASTER_SOCKET 0
-#define SLAVE_SOCKET 1
+#define MASTER_SOCKET 0
+#define SLAVE_SOCKET 1
/**
Get current CPU frequency.
@@ -35,7 +35,7 @@ UINTN
EFIAPI
CpuGetCurrentFreq (
- UINT8 Socket
+ UINT8 Socket
);
/**
@@ -48,7 +48,7 @@ CpuGetCurrentFreq ( UINTN
EFIAPI
CpuGetMaxFreq (
- UINT8 Socket
+ UINT8 Socket
);
/**
@@ -61,7 +61,7 @@ CpuGetMaxFreq ( UINT8
EFIAPI
CpuGetVoltage (
- UINT8 Socket
+ UINT8 Socket
);
/**
@@ -74,8 +74,8 @@ CpuGetVoltage ( VOID
EFIAPI
CpuGetEcid (
- UINT8 SocketId,
- UINT32 **Ecid
+ UINT8 SocketId,
+ UINT32 **Ecid
);
/**
@@ -88,7 +88,7 @@ CpuGetEcid ( UINT8
EFIAPI
GetSkuMaxCore (
- UINT8 SocketId
+ UINT8 SocketId
);
/**
@@ -101,7 +101,7 @@ GetSkuMaxCore ( UINT8
EFIAPI
GetSkuMaxTurbo (
- UINT8 SocketId
+ UINT8 SocketId
);
/**
@@ -150,8 +150,8 @@ CpuGetNumberOfSubNumaRegion ( UINT8
EFIAPI
CpuGetSubNumNode (
- UINT8 Socket,
- UINT16 Cpm
+ UINT8 Socket,
+ UINT16 Cpm
);
/**
@@ -188,7 +188,7 @@ GetNumberOfActiveSockets ( UINT16
EFIAPI
GetNumberOfActiveCPMsPerSocket (
- UINT8 SocketId
+ UINT8 SocketId
);
/**
@@ -201,7 +201,7 @@ GetNumberOfActiveCPMsPerSocket ( UINT16
EFIAPI
GetNumberOfConfiguredCPMs (
- UINT8 SocketId
+ UINT8 SocketId
);
/**
@@ -212,7 +212,7 @@ GetNumberOfConfiguredCPMs ( VOID
EFIAPI
GetScpVersion (
- UINT8 **ScpVer
+ UINT8 **ScpVer
);
/**
@@ -223,7 +223,7 @@ GetScpVersion ( VOID
EFIAPI
GetScpBuild (
- UINT8 **ScpBuild
+ UINT8 **ScpBuild
);
/**
@@ -234,7 +234,7 @@ GetScpBuild ( VOID
EFIAPI
GetDimmList (
- PLATFORM_DIMM_LIST **DimmList
+ PLATFORM_DIMM_LIST **DimmList
);
/**
@@ -245,7 +245,7 @@ GetDimmList ( VOID
EFIAPI
GetDramInfo (
- PLATFORM_DRAM_INFO **DramInfo
+ PLATFORM_DRAM_INFO **DramInfo
);
/**
@@ -260,8 +260,8 @@ GetDramInfo ( EFI_STATUS
EFIAPI
SetNumberOfConfiguredCPMs (
- UINT8 SocketId,
- UINT16 NumberOfCPMs
+ UINT8 SocketId,
+ UINT16 NumberOfCPMs
);
/**
@@ -286,7 +286,7 @@ GetMaximumNumberOfCores ( UINT16
EFIAPI
GetNumberOfActiveCoresPerSocket (
- UINT8 SocketId
+ UINT8 SocketId
);
/**
@@ -312,10 +312,9 @@ GetNumberOfActiveCores ( BOOLEAN
EFIAPI
IsCpuEnabled (
- UINT16 CpuId
+ UINT16 CpuId
);
-
/**
Check if the slave socket is present
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/BoardPcieLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/BoardPcieLib.h index 34e7dee702..9b8843ad84 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Library/BoardPcieLib.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/BoardPcieLib.h @@ -24,9 +24,9 @@ RETURN_STATUS
EFIAPI
BoardPcieAssertPerst (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN UINT8 PcieIndex,
- IN BOOLEAN IsPullToHigh
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN UINT8 PcieIndex,
+ IN BOOLEAN IsPullToHigh
);
/**
@@ -39,7 +39,7 @@ BoardPcieAssertPerst ( **/
UINT16
BoardPcieGetSegmentNumber (
- IN AC01_ROOT_COMPLEX *RootComplex
+ IN AC01_ROOT_COMPLEX *RootComplex
);
#endif /* BOARD_PCIE_LIB_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/FlashLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/FlashLib.h index ce50602f99..340dd05131 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Library/FlashLib.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/FlashLib.h @@ -22,8 +22,8 @@ EFI_STATUS
EFIAPI
FlashGetFailSafeInfo (
- OUT UINTN *FailSafeBase,
- OUT UINT32 *FailSafeSize
+ OUT UINTN *FailSafeBase,
+ OUT UINT32 *FailSafeSize
);
/**
@@ -39,8 +39,8 @@ FlashGetFailSafeInfo ( EFI_STATUS
EFIAPI
FlashGetNvRamInfo (
- OUT UINTN *NvRamBase,
- OUT UINT32 *NvRamSize
+ OUT UINTN *NvRamBase,
+ OUT UINT32 *NvRamSize
);
/**
@@ -56,8 +56,8 @@ FlashGetNvRamInfo ( EFI_STATUS
EFIAPI
FlashGetNvRam2Info (
- OUT UINTN *NvRam2Base,
- OUT UINT32 *NvRam2Size
+ OUT UINTN *NvRam2Base,
+ OUT UINT32 *NvRam2Size
);
/**
@@ -73,8 +73,8 @@ FlashGetNvRam2Info ( EFI_STATUS
EFIAPI
FlashEraseCommand (
- IN UINTN ByteAddress,
- IN UINT32 Length
+ IN UINTN ByteAddress,
+ IN UINT32 Length
);
/**
@@ -91,9 +91,9 @@ FlashEraseCommand ( EFI_STATUS
EFIAPI
FlashWriteCommand (
- IN UINTN ByteAddress,
- IN VOID *Buffer,
- IN UINT32 Length
+ IN UINTN ByteAddress,
+ IN VOID *Buffer,
+ IN UINT32 Length
);
/**
@@ -110,9 +110,9 @@ FlashWriteCommand ( EFI_STATUS
EFIAPI
FlashReadCommand (
- IN UINTN ByteAddress,
- OUT VOID *Buffer,
- IN UINT32 Length
+ IN UINTN ByteAddress,
+ OUT VOID *Buffer,
+ IN UINT32 Length
);
#endif /* FLASH_LIB_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/GpioLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/GpioLib.h index 3c72ce3d48..e75773b94d 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Library/GpioLib.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/GpioLib.h @@ -28,8 +28,8 @@ typedef enum { VOID
EFIAPI
GpioWriteBit (
- IN UINT32 Pin,
- IN UINT32 Val
+ IN UINT32 Pin,
+ IN UINT32 Val
);
/*
@@ -43,7 +43,7 @@ GpioWriteBit ( UINTN
EFIAPI
GpioReadBit (
- IN UINT32 Pin
+ IN UINT32 Pin
);
/*
@@ -56,8 +56,8 @@ GpioReadBit ( EFI_STATUS
EFIAPI
GpioModeConfig (
- UINT8 Pin,
- GPIO_CONFIG_MODE Mode
+ UINT8 Pin,
+ GPIO_CONFIG_MODE Mode
);
/*
@@ -70,7 +70,7 @@ GpioModeConfig ( EFI_STATUS
EFIAPI
GpioSetupRuntime (
- IN UINT32 Pin
+ IN UINT32 Pin
);
#endif /* GPIO_LIB_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/I2cLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/I2cLib.h index 3a312f7b6a..d0bb70d0cc 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Library/I2cLib.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/I2cLib.h @@ -30,10 +30,10 @@ EFI_STATUS
EFIAPI
I2cWrite (
- IN UINT32 Bus,
- IN UINT32 SlaveAddr,
- IN OUT UINT8 *Buf,
- IN OUT UINT32 *WriteLength
+ IN UINT32 Bus,
+ IN UINT32 SlaveAddr,
+ IN OUT UINT8 *Buf,
+ IN OUT UINT32 *WriteLength
);
/**
@@ -57,12 +57,12 @@ I2cWrite ( EFI_STATUS
EFIAPI
I2cRead (
- IN UINT32 Bus,
- IN UINT32 SlaveAddr,
- IN UINT8 *BufCmd,
- IN UINT32 CmdLength,
- IN OUT UINT8 *Buf,
- IN OUT UINT32 *ReadLength
+ IN UINT32 Bus,
+ IN UINT32 SlaveAddr,
+ IN UINT8 *BufCmd,
+ IN UINT32 CmdLength,
+ IN OUT UINT8 *Buf,
+ IN OUT UINT32 *ReadLength
);
/**
@@ -99,7 +99,7 @@ I2cProbe ( EFI_STATUS
EFIAPI
I2cSetupRuntime (
- IN UINT32 Bus
+ IN UINT32 Bus
);
#endif /* I2C_LIB_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/MailboxInterfaceLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/MailboxInterfaceLib.h index 425dc5c083..daab0f1739 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Library/MailboxInterfaceLib.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/MailboxInterfaceLib.h @@ -15,21 +15,21 @@ #ifndef MAILBOX_INTERFACE_LIB_H_
#define MAILBOX_INTERFACE_LIB_H_
-#define SMPRO_DB_MAX 8
-#define PMPRO_DB_MAX 8
-#define NUMBER_OF_DOORBELLS_PER_SOCKET (SMPRO_DB_MAX + PMPRO_DB_MAX)
+#define SMPRO_DB_MAX 8
+#define PMPRO_DB_MAX 8
+#define NUMBER_OF_DOORBELLS_PER_SOCKET (SMPRO_DB_MAX + PMPRO_DB_MAX)
//
// General address offset of Doorbell registers
//
-#define DB_IN_REG_OFST 0x00000000 // Doorbell In
-#define DB_DIN0_REG_OFST 0x00000004 // Doorbell In Data
-#define DB_DIN1_REG_OFST 0x00000008 // Doorbell In Data
-#define DB_OUT_REG_OFST 0x00000010 // Doorbell Out
-#define DB_DOUT0_REG_OFST 0x00000014 // Doorbell Out Data
-#define DB_DOUT1_REG_OFST 0x00000018 // Doorbell Out Data
-#define DB_STATUS_REG_OFST 0x00000020 // Doorbell Interrupt Status
-#define DB_STATUS_MASK_REG_OFST 0x00000024 // Doorbell Interrupt Status Mask
+#define DB_IN_REG_OFST 0x00000000 // Doorbell In
+#define DB_DIN0_REG_OFST 0x00000004 // Doorbell In Data
+#define DB_DIN1_REG_OFST 0x00000008 // Doorbell In Data
+#define DB_OUT_REG_OFST 0x00000010 // Doorbell Out
+#define DB_DOUT0_REG_OFST 0x00000014 // Doorbell Out Data
+#define DB_DOUT1_REG_OFST 0x00000018 // Doorbell Out Data
+#define DB_STATUS_REG_OFST 0x00000020 // Doorbell Interrupt Status
+#define DB_STATUS_MASK_REG_OFST 0x00000024 // Doorbell Interrupt Status Mask
//
// List of supported doorbells
@@ -67,8 +67,8 @@ typedef enum { // including 4 bytes for message and two 4 bytes for extended data.
//
typedef struct {
- UINT32 Data;
- UINT32 ExtendedData[2];
+ UINT32 Data;
+ UINT32 ExtendedData[2];
} MAILBOX_MESSAGE_DATA;
#pragma pack()
@@ -76,9 +76,9 @@ typedef struct { //
// Timeout configuration when waiting for an doorbell interrupt status
//
-#define MAILBOX_POLL_TIMEOUT_US 10000000
-#define MAILBOX_POLL_INTERVAL_US 1000
-#define MAILBOX_POLL_COUNT (MAILBOX_POLL_TIMEOUT_US / MAILBOX_POLL_INTERVAL_US)
+#define MAILBOX_POLL_TIMEOUT_US 10000000
+#define MAILBOX_POLL_INTERVAL_US 1000
+#define MAILBOX_POLL_COUNT (MAILBOX_POLL_TIMEOUT_US / MAILBOX_POLL_INTERVAL_US)
/**
Get the base address of a doorbell.
@@ -93,8 +93,8 @@ typedef struct { UINTN
EFIAPI
MailboxGetDoorbellAddress (
- IN UINT8 Socket,
- IN DOORBELL_CHANNELS Doorbell
+ IN UINT8 Socket,
+ IN DOORBELL_CHANNELS Doorbell
);
/**
@@ -110,8 +110,8 @@ MailboxGetDoorbellAddress ( UINT32
EFIAPI
MailboxGetDoorbellInterruptNumber (
- IN UINT8 Socket,
- IN DOORBELL_CHANNELS Doorbell
+ IN UINT8 Socket,
+ IN DOORBELL_CHANNELS Doorbell
);
/**
@@ -128,9 +128,9 @@ MailboxGetDoorbellInterruptNumber ( EFI_STATUS
EFIAPI
MailboxRead (
- IN UINT8 Socket,
- IN DOORBELL_CHANNELS Doorbell,
- OUT MAILBOX_MESSAGE_DATA *Message
+ IN UINT8 Socket,
+ IN DOORBELL_CHANNELS Doorbell,
+ OUT MAILBOX_MESSAGE_DATA *Message
);
/**
@@ -147,9 +147,9 @@ MailboxRead ( EFI_STATUS
EFIAPI
MailboxWrite (
- IN UINT8 Socket,
- IN DOORBELL_CHANNELS Doorbell,
- IN MAILBOX_MESSAGE_DATA *Message
+ IN UINT8 Socket,
+ IN DOORBELL_CHANNELS Doorbell,
+ IN MAILBOX_MESSAGE_DATA *Message
);
/**
@@ -165,8 +165,8 @@ MailboxWrite ( EFI_STATUS
EFIAPI
MailboxUnmaskInterrupt (
- IN UINT8 Socket,
- IN UINT16 Doorbell
+ IN UINT8 Socket,
+ IN UINT16 Doorbell
);
/**
@@ -182,8 +182,8 @@ MailboxUnmaskInterrupt ( EFI_STATUS
EFIAPI
MailboxRuntimeSetup (
- IN UINT8 Socket,
- IN DOORBELL_CHANNELS Doorbell
+ IN UINT8 Socket,
+ IN DOORBELL_CHANNELS Doorbell
);
#endif /* MAILBOX_INTERFACE_LIB_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h index fbbf66e518..d518946837 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/MmCommunicationLib.h @@ -37,8 +37,8 @@ EFI_STATUS
EFIAPI
MmCommunicationCommunicate (
- IN OUT VOID *CommBuffer,
- IN OUT UINTN *CommSize OPTIONAL
+ IN OUT VOID *CommBuffer,
+ IN OUT UINTN *CommSize OPTIONAL
);
#endif /* MM_COMMUNICATION_LIB_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h index e8521ce336..c149199848 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/NVParamLib.h @@ -41,14 +41,14 @@ #define NV_PARAM_MAX_SIZE (64 * 1024)
#define NV_PARAM_ENTRYSIZE 8
-#define NV_PERM_ALL 0xFFFF /* Allowed for all */
-#define NV_PERM_ATF 0x0001 /* Allowed for EL3 code */
-#define NV_PERM_OPTEE 0x0004 /* Allowed for secure El1 */
-#define NV_PERM_BIOS 0x0008 /* Allowed for EL2 non-secure */
-#define NV_PERM_MANU 0x0010 /* Allowed for manufactory interface */
-#define NV_PERM_BMC 0x0020 /* Allowed for BMC interface */
+#define NV_PERM_ALL 0xFFFF /* Allowed for all */
+#define NV_PERM_ATF 0x0001 /* Allowed for EL3 code */
+#define NV_PERM_OPTEE 0x0004 /* Allowed for secure El1 */
+#define NV_PERM_BIOS 0x0008 /* Allowed for EL2 non-secure */
+#define NV_PERM_MANU 0x0010 /* Allowed for manufactory interface */
+#define NV_PERM_BMC 0x0020 /* Allowed for BMC interface */
-#define NVPARAM_SIZE 0x8
+#define NVPARAM_SIZE 0x8
/**
Retrieve a non-volatile parameter.
@@ -68,9 +68,9 @@ **/
EFI_STATUS
NVParamGet (
- IN UINT32 Param,
- IN UINT16 ACLRd,
- OUT UINT32 *Val
+ IN UINT32 Param,
+ IN UINT16 ACLRd,
+ OUT UINT32 *Val
);
/**
@@ -93,10 +93,10 @@ NVParamGet ( **/
EFI_STATUS
NVParamSet (
- IN UINT32 Param,
- IN UINT16 ACLRd,
- IN UINT16 ACLWr,
- IN UINT32 Val
+ IN UINT32 Param,
+ IN UINT16 ACLRd,
+ IN UINT16 ACLWr,
+ IN UINT32 Val
);
/**
@@ -115,8 +115,8 @@ NVParamSet ( **/
EFI_STATUS
NVParamClr (
- IN UINT32 Param,
- IN UINT16 ACLWr
+ IN UINT32 Param,
+ IN UINT16 ACLWr
);
/**
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/PcieHotPlugLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/PcieHotPlugLib.h index e2f17d366a..45e76c266b 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Library/PcieHotPlugLib.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/PcieHotPlugLib.h @@ -9,17 +9,17 @@ #ifndef PCIE_HOT_PLUG_H_
#define PCIE_HOT_PLUG_H_
-#define PCIE_HOT_PLUG_SPCI_CMD_ALERT_IRQ 1 // Alert IRQ
-#define PCIE_HOT_PLUG_SPCI_CMD_START 2 // Stat monitor event
-#define PCIE_HOT_PLUG_SPCI_CMD_CHG 3 // Indicate PCIE port change state explicitly
-#define PCIE_HOT_PLUG_SPCI_CMD_LED 4 // Control LED state
-#define PCIE_HOT_PLUG_SPCI_CMD_PORT_MAP_CLR 5 // Clear all port map
-#define PCIE_HOT_PLUG_SPCI_CMD_PORT_MAP_SET 6 // Set port map
-#define PCIE_HOT_PLUG_SPCI_CMD_PORT_MAP_LOCK 7 // Lock port map
-#define PCIE_HOT_PLUG_SPCI_CMD_GPIO_MAP 8 // Set GPIO reset map
-
-#define LED_FAULT 1 // LED_CMD: LED type - Fault
-#define LED_ATT 2 // LED_CMD: LED type - Attention
+#define PCIE_HOT_PLUG_SPCI_CMD_ALERT_IRQ 1 // Alert IRQ
+#define PCIE_HOT_PLUG_SPCI_CMD_START 2 // Stat monitor event
+#define PCIE_HOT_PLUG_SPCI_CMD_CHG 3 // Indicate PCIE port change state explicitly
+#define PCIE_HOT_PLUG_SPCI_CMD_LED 4 // Control LED state
+#define PCIE_HOT_PLUG_SPCI_CMD_PORT_MAP_CLR 5 // Clear all port map
+#define PCIE_HOT_PLUG_SPCI_CMD_PORT_MAP_SET 6 // Set port map
+#define PCIE_HOT_PLUG_SPCI_CMD_PORT_MAP_LOCK 7 // Lock port map
+#define PCIE_HOT_PLUG_SPCI_CMD_GPIO_MAP 8 // Set GPIO reset map
+
+#define LED_FAULT 1 // LED_CMD: LED type - Fault
+#define LED_ATT 2 // LED_CMD: LED type - Attention
#define LED_SET_ON 1
#define LED_SET_OFF 2
@@ -41,11 +41,11 @@ #define SPCI_NOT_PRESENT -7
// Bit definitions inside the function id as per the SMC calling convention
-#define FUNCID_CC_SHIFT 30
-#define FUNCID_OEN_SHIFT 24
+#define FUNCID_CC_SHIFT 30
+#define FUNCID_OEN_SHIFT 24
-#define SMC_64 1
-#define SMC_32 0
+#define SMC_64 1
+#define SMC_32 0
// Definitions to build the complete SMC ID
#define SPCI_FID_MISC_FLAG (0 << 27)
@@ -69,10 +69,10 @@ SPCI_SMC ((tun_fid) << SPCI_FID_TUN_SHIFT))
// SPCI miscellaneous functions
-#define SPCI_FID_SERVICE_HANDLE_OPEN 0x2
-#define SPCI_FID_SERVICE_HANDLE_CLOSE 0x3
-#define SPCI_FID_SERVICE_REQUEST_BLOCKING 0x7
-#define SPCI_FID_SERVICE_REQUEST_START 0x8
+#define SPCI_FID_SERVICE_HANDLE_OPEN 0x2
+#define SPCI_FID_SERVICE_HANDLE_CLOSE 0x3
+#define SPCI_FID_SERVICE_REQUEST_BLOCKING 0x7
+#define SPCI_FID_SERVICE_REQUEST_START 0x8
// SPCI tunneling functions
#define SPCI_FID_SERVICE_TUN_REQUEST_BLOCKING 0x2
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/SystemFirmwareInterfaceLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/SystemFirmwareInterfaceLib.h index 40ad14a3f9..fec5667cc1 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Library/SystemFirmwareInterfaceLib.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/SystemFirmwareInterfaceLib.h @@ -18,39 +18,39 @@ // Bit 23:16 - Message control byte
// Bit 15:0 - Message data specific
//
-#define MAILBOX_MESSAGE_TYPE_SHIFT 28
-#define MAILBOX_MESSAGE_SUBTYPE_SHIFT 24
-#define MAILBOX_MESSAGE_CONTROL_BYTE_SHIFT 16
+#define MAILBOX_MESSAGE_TYPE_SHIFT 28
+#define MAILBOX_MESSAGE_SUBTYPE_SHIFT 24
+#define MAILBOX_MESSAGE_CONTROL_BYTE_SHIFT 16
-#define COMMON_MESSAGE_ENCODE(Type,Subtype,Control) \
+#define COMMON_MESSAGE_ENCODE(Type, Subtype, Control) \
( \
((Type) << MAILBOX_MESSAGE_TYPE_SHIFT) | \
((Subtype) << MAILBOX_MESSAGE_SUBTYPE_SHIFT) | \
((Control) << MAILBOX_MESSAGE_CONTROL_BYTE_SHIFT) \
)
-#define MAILBOX_MESSAGE_CONTROL_URGENT BIT7
-#define MAILBOX_MESSAGE_CONTROL_TYPICAL 0
+#define MAILBOX_MESSAGE_CONTROL_URGENT BIT7
+#define MAILBOX_MESSAGE_CONTROL_TYPICAL 0
//
// Mailbox Message Types
//
-#define MAILBOX_MESSAGE_TYPE_DEBUG 0x00
-#define MAILBOX_MESSAGE_TYPE_ADDRESS 0x05
-#define MAILBOX_MESSAGE_TYPE_USER 0x06
+#define MAILBOX_MESSAGE_TYPE_DEBUG 0x00
+#define MAILBOX_MESSAGE_TYPE_ADDRESS 0x05
+#define MAILBOX_MESSAGE_TYPE_USER 0x06
//
// Mailbox Message Type 0x00 - Debug message
//
-#define MAILBOX_DEBUG_MESSAGE_SUBTYPE_REGISTER_READ 0x01
-#define MAILBOX_DEBUG_MESSAGE_SUBTYPE_REGISTER_WRITE 0x02
+#define MAILBOX_DEBUG_MESSAGE_SUBTYPE_REGISTER_READ 0x01
+#define MAILBOX_DEBUG_MESSAGE_SUBTYPE_REGISTER_WRITE 0x02
//
// Debug message data format
// Bit 31:16 - Refer to definition of COMMON_MESSAGE_ENCODE
// Bit 15:0 - Store lower 16-bit of the upper 64-bit address
//
-#define MAILBOX_DEBUG_MESSAGE_ENCODE(Subtype,Address) \
+#define MAILBOX_DEBUG_MESSAGE_ENCODE(Subtype, Address) \
( \
(COMMON_MESSAGE_ENCODE ( \
MAILBOX_MESSAGE_TYPE_DEBUG, \
@@ -62,7 +62,7 @@ //
// Mailbox Message Type 0x05 - Address message
//
-#define MAILBOX_ADDRESS_MESSAGE_SUBTYPE_PCC 0x03
+#define MAILBOX_ADDRESS_MESSAGE_SUBTYPE_PCC 0x03
//
// Address message data format
@@ -73,7 +73,7 @@ // 0x0: No alignment
// Bit 3:0 - Unused
//
-#define MAILBOX_ADDRESS_MESSAGE_ENCODE(Subtype,Param,Align) \
+#define MAILBOX_ADDRESS_MESSAGE_ENCODE(Subtype, Param, Align) \
( \
(COMMON_MESSAGE_ENCODE ( \
MAILBOX_MESSAGE_TYPE_ADDRESS, \
@@ -83,7 +83,7 @@ ((Align) << 4) \
)
-#define MAILBOX_ADDRESS_URGENT_MESSAGE_ENCODE(Subtype,Param,Align) \
+#define MAILBOX_ADDRESS_URGENT_MESSAGE_ENCODE(Subtype, Param, Align) \
( \
(COMMON_MESSAGE_ENCODE ( \
MAILBOX_MESSAGE_TYPE_ADDRESS, \
@@ -93,10 +93,10 @@ ((Align) << 4) \
)
-#define MAILBOX_ADDRESS_256_ALIGNMENT 0x4
-#define MAILBOX_ADDRESS_NO_ALIGNMENT 0x0
+#define MAILBOX_ADDRESS_256_ALIGNMENT 0x4
+#define MAILBOX_ADDRESS_NO_ALIGNMENT 0x0
-#define MAILBOX_ADDRESS_MESSAGE_PARAM_CPPC 0x01
+#define MAILBOX_ADDRESS_MESSAGE_PARAM_CPPC 0x01
#define MAILBOX_URGENT_CPPC_MESSAGE \
( \
@@ -117,9 +117,9 @@ //
// Mailbox Message Type 0x06 - User message
//
-#define MAILBOX_USER_MESSAGE_SUBTYPE_SET_CONFIGURATION 0x02
-#define MAILBOX_USER_MESSAGE_SUBTYPE_BOOT_PROGRESS 0x06
-#define MAILBOX_USER_MESSAGE_SUBTYPE_TRNG_PROXY 0x07
+#define MAILBOX_USER_MESSAGE_SUBTYPE_SET_CONFIGURATION 0x02
+#define MAILBOX_USER_MESSAGE_SUBTYPE_BOOT_PROGRESS 0x06
+#define MAILBOX_USER_MESSAGE_SUBTYPE_TRNG_PROXY 0x07
//
// User message data format
@@ -127,7 +127,7 @@ // Bit 15:8 - Message Parameter 0
// Bit 7:0 - Message Parameter 1
//
-#define MAILBOX_USER_MESSAGE_ENCODE(Subtype,Param0,Param1) \
+#define MAILBOX_USER_MESSAGE_ENCODE(Subtype, Param0, Param1) \
( \
(COMMON_MESSAGE_ENCODE ( \
MAILBOX_MESSAGE_TYPE_USER, \
@@ -142,7 +142,7 @@ // Param0: 1 - Get a random number
// Param1: Unused
//
-#define MAILBOX_TRNG_PROXY_GET_RANDOM_NUMBER 1
+#define MAILBOX_TRNG_PROXY_GET_RANDOM_NUMBER 1
//
// Parameters for Boot Progress
@@ -151,9 +151,9 @@ // 0x08: BL33/UEFI Stage
// 0x09: OS Stage
//
-#define MAILBOX_BOOT_PROGRESS_COMMAND_SET 1
-#define MAILBOX_BOOT_PROGRESS_STAGE_UEFI 8
-#define MAILBOX_BOOT_PROGRESS_STAGE_OS 9
+#define MAILBOX_BOOT_PROGRESS_COMMAND_SET 1
+#define MAILBOX_BOOT_PROGRESS_STAGE_UEFI 8
+#define MAILBOX_BOOT_PROGRESS_STAGE_OS 9
//
// Parameters for Set Configuration
@@ -180,9 +180,9 @@ EFI_STATUS
EFIAPI
MailboxMsgRegisterRead (
- IN UINT8 Socket,
- IN UINTN Address,
- OUT UINT32 *Value
+ IN UINT8 Socket,
+ IN UINTN Address,
+ OUT UINT32 *Value
);
/**
@@ -202,9 +202,9 @@ MailboxMsgRegisterRead ( EFI_STATUS
EFIAPI
MailboxMsgRegisterWrite (
- IN UINT8 Socket,
- IN UINTN Address,
- IN UINT32 Value
+ IN UINT8 Socket,
+ IN UINTN Address,
+ IN UINT32 Value
);
/**
@@ -223,10 +223,10 @@ MailboxMsgRegisterWrite ( EFI_STATUS
EFIAPI
MailboxMsgSetPccSharedMem (
- IN UINT8 Socket,
- IN UINT8 Doorbell,
- IN BOOLEAN AddressAlign256,
- IN UINTN Address
+ IN UINT8 Socket,
+ IN UINT8 Doorbell,
+ IN BOOLEAN AddressAlign256,
+ IN UINTN Address
);
/**
@@ -242,7 +242,7 @@ MailboxMsgSetPccSharedMem ( EFI_STATUS
EFIAPI
MailboxMsgGetRandomNumber64 (
- OUT UINT8 *Buffer
+ OUT UINT8 *Buffer
);
/**
@@ -279,7 +279,7 @@ MailboxMsgSetBootProgress ( EFI_STATUS
EFIAPI
MailboxMsgDateConfig (
- IN EFI_TIME *Time
+ IN EFI_TIME *Time
);
/**
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h b/Silicon/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h index b478986cb0..bdfa67e9f4 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Library/TrngLib.h @@ -24,8 +24,8 @@ EFI_STATUS
EFIAPI
GenerateRandomNumbers (
- OUT UINT8 *Buffer,
- IN UINTN BufferSize
+ OUT UINT8 *Buffer,
+ IN UINTN BufferSize
);
#endif /* TRNG_LIB_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h b/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h index 2815ea252c..22449e6cfe 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/NVParamDef.h @@ -136,206 +136,206 @@ //
// NOTE: Add before NV_PREBOOT_PARAM_MAX and increase its value
//
-#define NV_PREBOOT_PARAM_MAX ((86 * 8) + NV_PREBOOT_PARAM_START)
+#define NV_PREBOOT_PARAM_MAX ((86 * 8) + NV_PREBOOT_PARAM_START)
//
// Manufactory non-volatile memory
//
// These parameters will reset to default value on failsafe.
//
-#define NV_MANU_PARAM_START (0x004000)
-#define NV_SI_DDR_VMARGIN ((0 * 8) + NV_MANU_PARAM_START)
-#define NV_PMPRO_REGION2_LOAD_START (NV_SI_DDR_VMARGIN)
-#define NV_SI_SOC_VMARGIN ((1 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_AVS_VMARGIN ((2 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_TPC_TM1_MARGIN ((3 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_TPC_TM2_MARGIN ((4 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_TPC_FREQ_THROTTLE ((5 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_T_LTLM_EN ((6 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_T_LTLM_THRSHLD ((7 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_T_GTLM_THRSHLD ((8 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_P_LM_EN ((9 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_P_LM_THRSHLD ((10 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_TPC_OVERTEMP_ISR_DISABLE ((11 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_VPP_VMARGIN ((12 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PMPRO_FAILURE_FAILSAFE ((13 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_FAILSAFE_DISABLE ((14 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLIMIT_APM_DS_PERCENTAGE ((15 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLIMIT_APM_EP_MS ((16 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLIMIT_APM_PM1_PERCENTAGE_TDP ((17 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_CPU_LPI_RESERVED0 ((18 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_CPU_LPI_RESERVED1 ((19 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_CCIX_OPT_CONFIG ((20 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_MESH_FREQ_MARGIN ((21 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_MESH_TURBO_EN ((22 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PWR_HEADROOM_WATT ((23 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_EXTRA_PCP_VOLT_MV ((24 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_CPU_LPI_HYST_CNT ((25 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_DVFS_VOLT_INC_STEP_MV ((26 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_DVFS_VOLT_DEC_STEP_MV ((27 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLIMIT_APM_TEMP_THLD ((28 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLIMIT_APM_EN ((29 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_VDM_EN ((30 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_VDM_VMARGIN_MV ((31 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_EN ((32 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_SOCKET ((33 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_MCU_MASK ((34 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_RANK_MASK ((35 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_SLICE_MASK ((36 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_BIT_MASK ((37 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_X_PARAM ((38 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_Y_PARAM ((39 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_X_LEFT ((40 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_X_RIGHT ((41 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_X_STEP ((42 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_Y_BOTTOM ((43 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_Y_TOP ((44 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_Y_STEP ((45 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_START_ADDR_LO ((46 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_START_ADDR_UP ((47 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_SIZE ((48 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_THREAD_CNT ((49 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_SCREEN ((50 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_PLT_RSVD ((51 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_DVFS_VOLT_CHANGE_BY_STEP_EN ((52 * 8) + NV_MANU_PARAM_START)
-#define NS_SI_DVFS_TCAL_F_LIMIT ((53 * 8) + NV_MANU_PARAM_START)
-#define NS_SI_DVFS_TCAL_T_LIMIT ((54 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_CCIX_DIAG_CTRL1 ((55 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_CCIX_DIAG_CTRL2 ((56 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_DDR_TCAL_EN ((57 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_DDR_TCAL_DIMM_LOW_TEMP_THRESHOLD ((58 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_DDR_TCAL_DIMM_HIGH_TEMP_THRESHOLD ((59 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_DDR_TCAL_MCU_LOW_TEMP_THRESHOLD ((60 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_DDR_TCAL_MCU_HIGH_TEMP_THRESHOLD ((61 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_DDR_TCAL_LOW_TEMP_VOLT_OFF_MV ((62 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_DDR_TCAL_PERIOD_SEC ((63 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_DDR_TCAL_SOC_VOLT_CAP_MV ((64 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_ALTRAMAX_ICCMAX_EN ((65 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_MESH_TURBO_ACTIVITY_THRESHOLD ((66 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_ALTRAMAX_ICCMAX_OC_LIMIT_MARGIN ((67 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_SLT_VREF_EXT_PROG_EN ((68 * 8) + NV_MANU_PARAM_START)
-#define NV_SI_SLT_FLAGS ((69 * 8) + NV_MANU_PARAM_START)
-#define NV_PMPRO_REGION2_LOAD_END (NV_SI_SLT_FLAGS)
+#define NV_MANU_PARAM_START (0x004000)
+#define NV_SI_DDR_VMARGIN ((0 * 8) + NV_MANU_PARAM_START)
+#define NV_PMPRO_REGION2_LOAD_START (NV_SI_DDR_VMARGIN)
+#define NV_SI_SOC_VMARGIN ((1 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_AVS_VMARGIN ((2 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_TPC_TM1_MARGIN ((3 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_TPC_TM2_MARGIN ((4 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_TPC_FREQ_THROTTLE ((5 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_T_LTLM_EN ((6 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_T_LTLM_THRSHLD ((7 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_T_GTLM_THRSHLD ((8 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_P_LM_EN ((9 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_P_LM_THRSHLD ((10 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_TPC_OVERTEMP_ISR_DISABLE ((11 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_VPP_VMARGIN ((12 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PMPRO_FAILURE_FAILSAFE ((13 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_FAILSAFE_DISABLE ((14 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLIMIT_APM_DS_PERCENTAGE ((15 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLIMIT_APM_EP_MS ((16 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLIMIT_APM_PM1_PERCENTAGE_TDP ((17 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_CPU_LPI_RESERVED0 ((18 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_CPU_LPI_RESERVED1 ((19 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_CCIX_OPT_CONFIG ((20 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_MESH_FREQ_MARGIN ((21 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_MESH_TURBO_EN ((22 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PWR_HEADROOM_WATT ((23 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_EXTRA_PCP_VOLT_MV ((24 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_CPU_LPI_HYST_CNT ((25 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_DVFS_VOLT_INC_STEP_MV ((26 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_DVFS_VOLT_DEC_STEP_MV ((27 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLIMIT_APM_TEMP_THLD ((28 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLIMIT_APM_EN ((29 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_VDM_EN ((30 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_VDM_VMARGIN_MV ((31 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_EN ((32 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_SOCKET ((33 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_MCU_MASK ((34 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_RANK_MASK ((35 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_SLICE_MASK ((36 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_BIT_MASK ((37 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_X_PARAM ((38 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_Y_PARAM ((39 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_X_LEFT ((40 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_X_RIGHT ((41 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_X_STEP ((42 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_Y_BOTTOM ((43 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_Y_TOP ((44 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_Y_STEP ((45 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_START_ADDR_LO ((46 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_START_ADDR_UP ((47 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_SIZE ((48 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_THREAD_CNT ((49 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_SCREEN ((50 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_PLT_RSVD ((51 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_DVFS_VOLT_CHANGE_BY_STEP_EN ((52 * 8) + NV_MANU_PARAM_START)
+#define NS_SI_DVFS_TCAL_F_LIMIT ((53 * 8) + NV_MANU_PARAM_START)
+#define NS_SI_DVFS_TCAL_T_LIMIT ((54 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_CCIX_DIAG_CTRL1 ((55 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_CCIX_DIAG_CTRL2 ((56 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_DDR_TCAL_EN ((57 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_DDR_TCAL_DIMM_LOW_TEMP_THRESHOLD ((58 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_DDR_TCAL_DIMM_HIGH_TEMP_THRESHOLD ((59 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_DDR_TCAL_MCU_LOW_TEMP_THRESHOLD ((60 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_DDR_TCAL_MCU_HIGH_TEMP_THRESHOLD ((61 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_DDR_TCAL_LOW_TEMP_VOLT_OFF_MV ((62 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_DDR_TCAL_PERIOD_SEC ((63 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_DDR_TCAL_SOC_VOLT_CAP_MV ((64 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_ALTRAMAX_ICCMAX_EN ((65 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_MESH_TURBO_ACTIVITY_THRESHOLD ((66 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_ALTRAMAX_ICCMAX_OC_LIMIT_MARGIN ((67 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_SLT_VREF_EXT_PROG_EN ((68 * 8) + NV_MANU_PARAM_START)
+#define NV_SI_SLT_FLAGS ((69 * 8) + NV_MANU_PARAM_START)
+#define NV_PMPRO_REGION2_LOAD_END (NV_SI_SLT_FLAGS)
//
// NOTE: Add before NV_MANU_PARAM_MAX and increase its value
//
-#define NV_MANU_PARAM_MAX ((66 * 8) + NV_MANU_PARAM_START)
+#define NV_MANU_PARAM_MAX ((66 * 8) + NV_MANU_PARAM_START)
//
// User non-volatile memory
//
// These parameters will reset to default value on failsafe.
//
-#define NV_USER_PARAM_START (0x008000)
-#define NV_SI_S0_PCP_ACTIVECPM_0_31 ((0 * 8) + NV_USER_PARAM_START)
-#define NV_SI_S0_PCP_ACTIVECPM_32_63 ((1 * 8) + NV_USER_PARAM_START)
-#define NV_SI_S1_PCP_ACTIVECPM_0_31 ((2 * 8) + NV_USER_PARAM_START)
-#define NV_SI_S1_PCP_ACTIVECPM_32_63 ((3 * 8) + NV_USER_PARAM_START)
-#define NV_SI_WDT_BIOS_EXP_MINS ((4 * 8) + NV_USER_PARAM_START)
-#define NV_SI_DDR_CE_RAS_THRESHOLD ((5 * 8) + NV_USER_PARAM_START)
-#define NV_SI_DDR_CE_RAS_INTERVAL ((6 * 8) + NV_USER_PARAM_START)
-#define NV_SI_DDR_SPEED ((7 * 8) + NV_USER_PARAM_START)
-#define NV_SI_DDR_SCRUB_EN ((8 * 8) + NV_USER_PARAM_START)
-#define NV_SI_DDR_ECC_MODE ((9 * 8) + NV_USER_PARAM_START)
-#define NV_SI_S0_RCA_PCI_DEVMAP ((10 * 8) + NV_USER_PARAM_START)
-#define NV_SI_S0_RCB_PCI_DEVMAP ((11 * 8) + NV_USER_PARAM_START)
-#define NV_SI_S1_RCA_PCI_DEVMAP ((12 * 8) + NV_USER_PARAM_START)
-#define NV_SI_S1_RCB_PCI_DEVMAP ((13 * 8) + NV_USER_PARAM_START)
-#define NV_SI_DDR_ERRCTRL ((14 * 8) + NV_USER_PARAM_START)
-#define NV_SI_DDR_REFRESH_GRANULARITY ((15 * 8) + NV_USER_PARAM_START)
-#define NV_SI_SUBNUMA_MODE ((16 * 8) + NV_USER_PARAM_START)
-#define NV_SI_ERRATUM_1542419_WA ((17 * 8) + NV_USER_PARAM_START)
-#define NV_SI_NEAR_ATOMIC_DISABLE ((18 * 8) + NV_USER_PARAM_START)
-#define NV_SI_DDR_SLAVE_32BIT_MEM_EN ((19 * 8) + NV_USER_PARAM_START)
-#define NV_SI_CPUECTLR_EL1_0_31 ((20 * 8) + NV_USER_PARAM_START)
-#define NV_SI_CPUECTLR_EL1_32_63 ((21 * 8) + NV_USER_PARAM_START)
-#define NV_SI_HARDWARE_EINJ ((22 * 8) + NV_USER_PARAM_START)
-#define NV_SI_2P_CE_RAS_THRESHOLD ((23 * 8) + NV_USER_PARAM_START)
-#define NV_SI_2P_CE_RAS_INTERVAL ((24 * 8) + NV_USER_PARAM_START)
-#define NV_SI_RAS_BERT_ENABLED ((25 * 8) + NV_USER_PARAM_START)
-#define NV_SI_HNF_AUX_CTL_0_31 ((26 * 8) + NV_USER_PARAM_START)
-#define NV_SI_HNF_AUX_CTL_32_63 ((27 * 8) + NV_USER_PARAM_START)
-#define NV_SI_CPM_CE_RAS_THRESHOLD ((28 * 8) + NV_USER_PARAM_START)
-#define NV_SI_CPM_CE_RAS_INTERVAL ((29 * 8) + NV_USER_PARAM_START)
-#define NV_SI_HNF_AUX_CTL_0_31_WR_EN_MASK ((30 * 8) + NV_USER_PARAM_START)
-#define NV_SI_HNF_AUX_CTL_32_63_WR_EN_MASK ((31 * 8) + NV_USER_PARAM_START)
-#define NV_SI_DDR_WR_BACK_EN ((32 * 8) + NV_USER_PARAM_START)
-#define NV_SI_CPUECTLR_EL1_0_31_WR_EN_MASK ((33 * 8) + NV_USER_PARAM_START)
-#define NV_SI_CPUECTLR_EL1_32_63_WR_EN_MASK ((34 * 8) + NV_USER_PARAM_START)
-#define NV_SI_LINK_ERR_THRESHOLD ((35 * 8) + NV_USER_PARAM_START)
-#define NV_SI_SEC_WDT_BIOS_EXP_MINS ((36 * 8) + NV_USER_PARAM_START)
-#define NV_SI_NVDIMM_MODE ((37 * 8) + NV_USER_PARAM_START)
-#define NV_SI_RAS_SDEI_ENABLED ((38 * 8) + NV_USER_PARAM_START)
-#define NV_SI_NVDIMM_PROV_MASK_S0 ((39 * 8) + NV_USER_PARAM_START)
-#define NV_SI_NVDIMM_PROV_MASK_S1 ((40 * 8) + NV_USER_PARAM_START)
-#define NV_SI_DDR_ZQCS_EN ((41 * 8) + NV_USER_PARAM_START)
-#define NV_SI_DDR_CRC_MODE ((42 * 8) + NV_USER_PARAM_START)
-#define NV_SI_CXG_RA_AUX_CTL_0_31 ((43 * 8) + NV_USER_PARAM_START)
-#define NV_SI_CXG_RA_AUX_CTL_32_63 ((44 * 8) + NV_USER_PARAM_START)
-#define NV_SI_CXG_RA_AUX_CTL_0_31_WR_EN_MASK ((45 * 8) + NV_USER_PARAM_START)
-#define NV_SI_CXG_RA_AUX_CTL_32_63_WR_EN_MASK ((46 * 8) + NV_USER_PARAM_START)
-#define NV_SI_CXLA_AUX_CTL_0_31 ((47 * 8) + NV_USER_PARAM_START)
-#define NV_SI_CXLA_AUX_CTL_32_63 ((48 * 8) + NV_USER_PARAM_START)
-#define NV_SI_CXLA_AUX_CTL_0_31_WR_EN_MASK ((49 * 8) + NV_USER_PARAM_START)
-#define NV_SI_CXLA_AUX_CTL_32_63_WR_EN_MASK ((50 * 8) + NV_USER_PARAM_START)
-#define NV_SI_DDR_LOW_POWER_CFG ((51 * 8) + NV_USER_PARAM_START)
-#define NV_SI_ALERT_DIMM_SHUTDOWN_EN ((52 * 8) + NV_USER_PARAM_START)
-#define NV_SI_DFS_EN ((53 * 8) + NV_USER_PARAM_START)
-#define NV_SI_RAS_PCIE_AER_FW_FIRST ((54 * 8) + NV_USER_PARAM_START)
-#define NV_SI_RAS_DRAM_EINJ_NOTRIGGER ((55 * 8) + NV_USER_PARAM_START)
-#define NV_SI_RAS_AEST_PROC_EN ((56 * 8) + NV_USER_PARAM_START)
-#define NV_SI_MESH_S0_CXG_RC_STRONG_ORDERING_EN ((57 * 8) + NV_USER_PARAM_START)
-#define NV_SI_MESH_S1_CXG_RC_STRONG_ORDERING_EN ((58 * 8) + NV_USER_PARAM_START)
-#define NV_SI_2P_RESERVED0 ((59 * 8) + NV_USER_PARAM_START)
-#define NV_SI_2P_RESERVED1 ((60 * 8) + NV_USER_PARAM_START)
-#define NV_SI_2P_RESERVED2 ((61 * 8) + NV_USER_PARAM_START)
-#define NV_SI_HCR_EL2_CTL_LOW ((62 * 8) + NV_USER_PARAM_START)
-#define NV_SI_HCR_EL2_CTL_HIGH ((63 * 8) + NV_USER_PARAM_START)
-#define NV_SI_ESM_SPEED ((64 * 8) + NV_USER_PARAM_START)
-#define NV_SI_RAS_DDR_CE_TH1 ((65 * 8) + NV_USER_PARAM_START)
-#define NV_SI_RAS_DDR_CE_TH2 ((66 * 8) + NV_USER_PARAM_START)
-#define NV_SI_RAS_DDR_CE_WINDOW1 ((67 * 8) + NV_USER_PARAM_START)
-#define NV_SI_RAS_DDR_CE_WINDOW2 ((68 * 8) + NV_USER_PARAM_START)
-#define NV_SI_RAS_2P_CE_FILTER_THRESHOLD ((69 * 8) + NV_USER_PARAM_START)
-#define NV_SI_RAS_2P_CE_FILTER_WINDOW ((70 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC0_AER_CE_THRESHOLD ((71 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC0_AER_CE_INTERVAL ((72 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC1_AER_CE_THRESHOLD ((73 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC1_AER_CE_INTERVAL ((74 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC2_AER_CE_THRESHOLD ((75 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC2_AER_CE_INTERVAL ((76 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC3_AER_CE_THRESHOLD ((77 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC3_AER_CE_INTERVAL ((78 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC4_AER_CE_THRESHOLD ((79 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC4_AER_CE_INTERVAL ((80 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC5_AER_CE_THRESHOLD ((81 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC5_AER_CE_INTERVAL ((82 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC6_AER_CE_THRESHOLD ((83 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC6_AER_CE_INTERVAL ((84 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC7_AER_CE_THRESHOLD ((85 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S0_RC7_AER_CE_INTERVAL ((86 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC0_AER_CE_THRESHOLD ((87 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC0_AER_CE_INTERVAL ((88 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC1_AER_CE_THRESHOLD ((89 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC1_AER_CE_INTERVAL ((90 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC2_AER_CE_THRESHOLD ((91 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC2_AER_CE_INTERVAL ((92 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC3_AER_CE_THRESHOLD ((93 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC3_AER_CE_INTERVAL ((94 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC4_AER_CE_THRESHOLD ((95 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC4_AER_CE_INTERVAL ((96 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC5_AER_CE_THRESHOLD ((97 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC5_AER_CE_INTERVAL ((98 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC6_AER_CE_THRESHOLD ((99 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC6_AER_CE_INTERVAL ((100 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC7_AER_CE_THRESHOLD ((101 * 8) + NV_USER_PARAM_START)
-#define NV_SI_PCIE_S1_RC7_AER_CE_INTERVAL ((102 * 8) + NV_USER_PARAM_START)
+#define NV_USER_PARAM_START (0x008000)
+#define NV_SI_S0_PCP_ACTIVECPM_0_31 ((0 * 8) + NV_USER_PARAM_START)
+#define NV_SI_S0_PCP_ACTIVECPM_32_63 ((1 * 8) + NV_USER_PARAM_START)
+#define NV_SI_S1_PCP_ACTIVECPM_0_31 ((2 * 8) + NV_USER_PARAM_START)
+#define NV_SI_S1_PCP_ACTIVECPM_32_63 ((3 * 8) + NV_USER_PARAM_START)
+#define NV_SI_WDT_BIOS_EXP_MINS ((4 * 8) + NV_USER_PARAM_START)
+#define NV_SI_DDR_CE_RAS_THRESHOLD ((5 * 8) + NV_USER_PARAM_START)
+#define NV_SI_DDR_CE_RAS_INTERVAL ((6 * 8) + NV_USER_PARAM_START)
+#define NV_SI_DDR_SPEED ((7 * 8) + NV_USER_PARAM_START)
+#define NV_SI_DDR_SCRUB_EN ((8 * 8) + NV_USER_PARAM_START)
+#define NV_SI_DDR_ECC_MODE ((9 * 8) + NV_USER_PARAM_START)
+#define NV_SI_S0_RCA_PCI_DEVMAP ((10 * 8) + NV_USER_PARAM_START)
+#define NV_SI_S0_RCB_PCI_DEVMAP ((11 * 8) + NV_USER_PARAM_START)
+#define NV_SI_S1_RCA_PCI_DEVMAP ((12 * 8) + NV_USER_PARAM_START)
+#define NV_SI_S1_RCB_PCI_DEVMAP ((13 * 8) + NV_USER_PARAM_START)
+#define NV_SI_DDR_ERRCTRL ((14 * 8) + NV_USER_PARAM_START)
+#define NV_SI_DDR_REFRESH_GRANULARITY ((15 * 8) + NV_USER_PARAM_START)
+#define NV_SI_SUBNUMA_MODE ((16 * 8) + NV_USER_PARAM_START)
+#define NV_SI_ERRATUM_1542419_WA ((17 * 8) + NV_USER_PARAM_START)
+#define NV_SI_NEAR_ATOMIC_DISABLE ((18 * 8) + NV_USER_PARAM_START)
+#define NV_SI_DDR_SLAVE_32BIT_MEM_EN ((19 * 8) + NV_USER_PARAM_START)
+#define NV_SI_CPUECTLR_EL1_0_31 ((20 * 8) + NV_USER_PARAM_START)
+#define NV_SI_CPUECTLR_EL1_32_63 ((21 * 8) + NV_USER_PARAM_START)
+#define NV_SI_HARDWARE_EINJ ((22 * 8) + NV_USER_PARAM_START)
+#define NV_SI_2P_CE_RAS_THRESHOLD ((23 * 8) + NV_USER_PARAM_START)
+#define NV_SI_2P_CE_RAS_INTERVAL ((24 * 8) + NV_USER_PARAM_START)
+#define NV_SI_RAS_BERT_ENABLED ((25 * 8) + NV_USER_PARAM_START)
+#define NV_SI_HNF_AUX_CTL_0_31 ((26 * 8) + NV_USER_PARAM_START)
+#define NV_SI_HNF_AUX_CTL_32_63 ((27 * 8) + NV_USER_PARAM_START)
+#define NV_SI_CPM_CE_RAS_THRESHOLD ((28 * 8) + NV_USER_PARAM_START)
+#define NV_SI_CPM_CE_RAS_INTERVAL ((29 * 8) + NV_USER_PARAM_START)
+#define NV_SI_HNF_AUX_CTL_0_31_WR_EN_MASK ((30 * 8) + NV_USER_PARAM_START)
+#define NV_SI_HNF_AUX_CTL_32_63_WR_EN_MASK ((31 * 8) + NV_USER_PARAM_START)
+#define NV_SI_DDR_WR_BACK_EN ((32 * 8) + NV_USER_PARAM_START)
+#define NV_SI_CPUECTLR_EL1_0_31_WR_EN_MASK ((33 * 8) + NV_USER_PARAM_START)
+#define NV_SI_CPUECTLR_EL1_32_63_WR_EN_MASK ((34 * 8) + NV_USER_PARAM_START)
+#define NV_SI_LINK_ERR_THRESHOLD ((35 * 8) + NV_USER_PARAM_START)
+#define NV_SI_SEC_WDT_BIOS_EXP_MINS ((36 * 8) + NV_USER_PARAM_START)
+#define NV_SI_NVDIMM_MODE ((37 * 8) + NV_USER_PARAM_START)
+#define NV_SI_RAS_SDEI_ENABLED ((38 * 8) + NV_USER_PARAM_START)
+#define NV_SI_NVDIMM_PROV_MASK_S0 ((39 * 8) + NV_USER_PARAM_START)
+#define NV_SI_NVDIMM_PROV_MASK_S1 ((40 * 8) + NV_USER_PARAM_START)
+#define NV_SI_DDR_ZQCS_EN ((41 * 8) + NV_USER_PARAM_START)
+#define NV_SI_DDR_CRC_MODE ((42 * 8) + NV_USER_PARAM_START)
+#define NV_SI_CXG_RA_AUX_CTL_0_31 ((43 * 8) + NV_USER_PARAM_START)
+#define NV_SI_CXG_RA_AUX_CTL_32_63 ((44 * 8) + NV_USER_PARAM_START)
+#define NV_SI_CXG_RA_AUX_CTL_0_31_WR_EN_MASK ((45 * 8) + NV_USER_PARAM_START)
+#define NV_SI_CXG_RA_AUX_CTL_32_63_WR_EN_MASK ((46 * 8) + NV_USER_PARAM_START)
+#define NV_SI_CXLA_AUX_CTL_0_31 ((47 * 8) + NV_USER_PARAM_START)
+#define NV_SI_CXLA_AUX_CTL_32_63 ((48 * 8) + NV_USER_PARAM_START)
+#define NV_SI_CXLA_AUX_CTL_0_31_WR_EN_MASK ((49 * 8) + NV_USER_PARAM_START)
+#define NV_SI_CXLA_AUX_CTL_32_63_WR_EN_MASK ((50 * 8) + NV_USER_PARAM_START)
+#define NV_SI_DDR_LOW_POWER_CFG ((51 * 8) + NV_USER_PARAM_START)
+#define NV_SI_ALERT_DIMM_SHUTDOWN_EN ((52 * 8) + NV_USER_PARAM_START)
+#define NV_SI_DFS_EN ((53 * 8) + NV_USER_PARAM_START)
+#define NV_SI_RAS_PCIE_AER_FW_FIRST ((54 * 8) + NV_USER_PARAM_START)
+#define NV_SI_RAS_DRAM_EINJ_NOTRIGGER ((55 * 8) + NV_USER_PARAM_START)
+#define NV_SI_RAS_AEST_PROC_EN ((56 * 8) + NV_USER_PARAM_START)
+#define NV_SI_MESH_S0_CXG_RC_STRONG_ORDERING_EN ((57 * 8) + NV_USER_PARAM_START)
+#define NV_SI_MESH_S1_CXG_RC_STRONG_ORDERING_EN ((58 * 8) + NV_USER_PARAM_START)
+#define NV_SI_2P_RESERVED0 ((59 * 8) + NV_USER_PARAM_START)
+#define NV_SI_2P_RESERVED1 ((60 * 8) + NV_USER_PARAM_START)
+#define NV_SI_2P_RESERVED2 ((61 * 8) + NV_USER_PARAM_START)
+#define NV_SI_HCR_EL2_CTL_LOW ((62 * 8) + NV_USER_PARAM_START)
+#define NV_SI_HCR_EL2_CTL_HIGH ((63 * 8) + NV_USER_PARAM_START)
+#define NV_SI_ESM_SPEED ((64 * 8) + NV_USER_PARAM_START)
+#define NV_SI_RAS_DDR_CE_TH1 ((65 * 8) + NV_USER_PARAM_START)
+#define NV_SI_RAS_DDR_CE_TH2 ((66 * 8) + NV_USER_PARAM_START)
+#define NV_SI_RAS_DDR_CE_WINDOW1 ((67 * 8) + NV_USER_PARAM_START)
+#define NV_SI_RAS_DDR_CE_WINDOW2 ((68 * 8) + NV_USER_PARAM_START)
+#define NV_SI_RAS_2P_CE_FILTER_THRESHOLD ((69 * 8) + NV_USER_PARAM_START)
+#define NV_SI_RAS_2P_CE_FILTER_WINDOW ((70 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC0_AER_CE_THRESHOLD ((71 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC0_AER_CE_INTERVAL ((72 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC1_AER_CE_THRESHOLD ((73 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC1_AER_CE_INTERVAL ((74 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC2_AER_CE_THRESHOLD ((75 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC2_AER_CE_INTERVAL ((76 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC3_AER_CE_THRESHOLD ((77 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC3_AER_CE_INTERVAL ((78 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC4_AER_CE_THRESHOLD ((79 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC4_AER_CE_INTERVAL ((80 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC5_AER_CE_THRESHOLD ((81 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC5_AER_CE_INTERVAL ((82 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC6_AER_CE_THRESHOLD ((83 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC6_AER_CE_INTERVAL ((84 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC7_AER_CE_THRESHOLD ((85 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S0_RC7_AER_CE_INTERVAL ((86 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC0_AER_CE_THRESHOLD ((87 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC0_AER_CE_INTERVAL ((88 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC1_AER_CE_THRESHOLD ((89 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC1_AER_CE_INTERVAL ((90 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC2_AER_CE_THRESHOLD ((91 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC2_AER_CE_INTERVAL ((92 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC3_AER_CE_THRESHOLD ((93 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC3_AER_CE_INTERVAL ((94 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC4_AER_CE_THRESHOLD ((95 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC4_AER_CE_INTERVAL ((96 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC5_AER_CE_THRESHOLD ((97 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC5_AER_CE_INTERVAL ((98 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC6_AER_CE_THRESHOLD ((99 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC6_AER_CE_INTERVAL ((100 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC7_AER_CE_THRESHOLD ((101 * 8) + NV_USER_PARAM_START)
+#define NV_SI_PCIE_S1_RC7_AER_CE_INTERVAL ((102 * 8) + NV_USER_PARAM_START)
//
// NOTE: Add before NV_USER_PARAM_MAX and increase its value
//
-#define NV_USER_PARAM_MAX (NV_SI_PCIE_S1_RC7_AER_CE_INTERVAL)
-#define NV_PMPRO_REGION3_LOAD_START (NV_USER_PARAM_START)
-#define NV_PMPRO_REGION3_LOAD_END (NV_USER_PARAM_MAX)
+#define NV_USER_PARAM_MAX (NV_SI_PCIE_S1_RC7_AER_CE_INTERVAL)
+#define NV_PMPRO_REGION3_LOAD_START (NV_USER_PARAM_START)
+#define NV_PMPRO_REGION3_LOAD_END (NV_USER_PARAM_MAX)
//
// Non-volatile board read-only setting
@@ -350,62 +350,62 @@ // board setting. The keyword "Default: " is used to provide
// the default value.
//
-#define NV_BOARD_PARAM_START (0x00C000)
-#define NV_SI_RO_BOARD_VENDOR ((0 * 8) + NV_BOARD_PARAM_START) /* Default: 0x0000CD3A - Follow BMC FRU format */
-#define NV_PMPRO_REGION4_LOAD_START (NV_SI_RO_BOARD_VENDOR)
-#define NV_SI_RO_BOARD_TYPE ((1 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 - Follow BMC FRU format */
-#define NV_SI_RO_BOARD_REV ((2 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 Follow BMC FRU format */
-#define NV_SI_RO_BOARD_CFG ((3 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 Follow BMC FRU format */
-#define NV_SI_RO_BOARD_S0_DIMM_AVAIL ((4 * 8) + NV_BOARD_PARAM_START) /* Default: 0x0000FFFF */
-#define NV_SI_RO_BOARD_S1_DIMM_AVAIL ((5 * 8) + NV_BOARD_PARAM_START) /* Default: 0x0000FFFF */
-#define NV_SI_RO_BOARD_SPI0CS0_FREQ_KHZ ((6 * 8) + NV_BOARD_PARAM_START) /* Default: 33000 */
-#define NV_SI_RO_BOARD_SPI0CS1_FREQ_KHZ ((7 * 8) + NV_BOARD_PARAM_START) /* Default: 33000 */
-#define NV_SI_RO_BOARD_SPI1CS0_FREQ_KHZ ((8 * 8) + NV_BOARD_PARAM_START) /* Default: 10000 */
-#define NV_SI_RO_BOARD_SPI1CS1_FREQ_KHZ ((9 * 8) + NV_BOARD_PARAM_START) /* Default: 10000 */
-#define NV_SI_RO_BOARD_TPM_LOC ((10 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
-#define NV_SI_RO_BOARD_I2C0_FREQ_KHZ ((11 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
-#define NV_SI_RO_BOARD_I2C1_FREQ_KHZ ((12 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
-#define NV_SI_RO_BOARD_I2C2_10_FREQ_KHZ ((13 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
-#define NV_SI_RO_BOARD_I2C3_FREQ_KHZ ((14 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
-#define NV_SI_RO_BOARD_I2C9_FREQ_KHZ ((15 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
-#define NV_SI_RO_BOARD_2P_CFG ((16 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFF01 */
-#define NV_SI_RO_BOARD_S0_RCA0_CFG ((17 * 8) + NV_BOARD_PARAM_START)
-#define NV_SI_RO_BOARD_S0_RCA1_CFG ((18 * 8) + NV_BOARD_PARAM_START)
-#define NV_SI_RO_BOARD_S0_RCA2_CFG ((19 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000004 */
-#define NV_SI_RO_BOARD_S0_RCA3_CFG ((20 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000004 */
-#define NV_SI_RO_BOARD_S0_RCB0_LO_CFG ((21 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
-#define NV_SI_RO_BOARD_S0_RCB0_HI_CFG ((22 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
-#define NV_SI_RO_BOARD_S0_RCB1_LO_CFG ((23 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
-#define NV_SI_RO_BOARD_S0_RCB1_HI_CFG ((24 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
-#define NV_SI_RO_BOARD_S0_RCB2_LO_CFG ((25 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
-#define NV_SI_RO_BOARD_S0_RCB2_HI_CFG ((26 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
-#define NV_SI_RO_BOARD_S0_RCB3_LO_CFG ((27 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
-#define NV_SI_RO_BOARD_S0_RCB3_HI_CFG ((28 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
-#define NV_SI_RO_BOARD_S1_RCA0_CFG ((29 * 8) + NV_BOARD_PARAM_START)
-#define NV_SI_RO_BOARD_S1_RCA1_CFG ((30 * 8) + NV_BOARD_PARAM_START)
-#define NV_SI_RO_BOARD_S1_RCA2_CFG ((31 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */
-#define NV_SI_RO_BOARD_S1_RCA3_CFG ((32 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00030003 */
-#define NV_SI_RO_BOARD_S1_RCB0_LO_CFG ((33 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
-#define NV_SI_RO_BOARD_S1_RCB0_HI_CFG ((34 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
-#define NV_SI_RO_BOARD_S1_RCB1_LO_CFG ((35 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
-#define NV_SI_RO_BOARD_S1_RCB1_HI_CFG ((36 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
-#define NV_SI_RO_BOARD_S1_RCB2_LO_CFG ((37 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
-#define NV_SI_RO_BOARD_S1_RCB2_HI_CFG ((38 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
-#define NV_SI_RO_BOARD_S1_RCB3_LO_CFG ((39 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
-#define NV_SI_RO_BOARD_S1_RCB3_HI_CFG ((40 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
-#define NV_SI_RO_BOARD_T_LTLM_DELTA_P0 ((41 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000001 */
-#define NV_SI_RO_BOARD_T_LTLM_DELTA_P1 ((42 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000002 */
-#define NV_SI_RO_BOARD_T_LTLM_DELTA_P2 ((43 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
-#define NV_SI_RO_BOARD_T_LTLM_DELTA_P3 ((44 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000004 */
-#define NV_SI_RO_BOARD_T_LTLM_DELTA_M1 ((45 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
-#define NV_SI_RO_BOARD_T_LTLM_DELTA_M2 ((46 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFE */
-#define NV_SI_RO_BOARD_T_LTLM_DELTA_M3 ((47 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFD */
-#define NV_SI_RO_BOARD_P_LM_PID_P ((48 * 8) + NV_BOARD_PARAM_START)
-#define NV_SI_RO_BOARD_P_LM_PID_I ((49 * 8) + NV_BOARD_PARAM_START)
-#define NV_SI_RO_BOARD_P_LM_PID_I_L_THOLD ((50 * 8) + NV_BOARD_PARAM_START)
-#define NV_SI_RO_BOARD_P_LM_PID_I_H_THOLD ((51 * 8) + NV_BOARD_PARAM_START)
-#define NV_SI_RO_BOARD_P_LM_PID_D ((52 * 8) + NV_BOARD_PARAM_START)
-#define NV_SI_RO_BOARD_P_LM_EXP_SMOOTH_CONST ((53 * 8) + NV_BOARD_PARAM_START)
+#define NV_BOARD_PARAM_START (0x00C000)
+#define NV_SI_RO_BOARD_VENDOR ((0 * 8) + NV_BOARD_PARAM_START) /* Default: 0x0000CD3A - Follow BMC FRU format */
+#define NV_PMPRO_REGION4_LOAD_START (NV_SI_RO_BOARD_VENDOR)
+#define NV_SI_RO_BOARD_TYPE ((1 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 - Follow BMC FRU format */
+#define NV_SI_RO_BOARD_REV ((2 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 Follow BMC FRU format */
+#define NV_SI_RO_BOARD_CFG ((3 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 Follow BMC FRU format */
+#define NV_SI_RO_BOARD_S0_DIMM_AVAIL ((4 * 8) + NV_BOARD_PARAM_START) /* Default: 0x0000FFFF */
+#define NV_SI_RO_BOARD_S1_DIMM_AVAIL ((5 * 8) + NV_BOARD_PARAM_START) /* Default: 0x0000FFFF */
+#define NV_SI_RO_BOARD_SPI0CS0_FREQ_KHZ ((6 * 8) + NV_BOARD_PARAM_START) /* Default: 33000 */
+#define NV_SI_RO_BOARD_SPI0CS1_FREQ_KHZ ((7 * 8) + NV_BOARD_PARAM_START) /* Default: 33000 */
+#define NV_SI_RO_BOARD_SPI1CS0_FREQ_KHZ ((8 * 8) + NV_BOARD_PARAM_START) /* Default: 10000 */
+#define NV_SI_RO_BOARD_SPI1CS1_FREQ_KHZ ((9 * 8) + NV_BOARD_PARAM_START) /* Default: 10000 */
+#define NV_SI_RO_BOARD_TPM_LOC ((10 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
+#define NV_SI_RO_BOARD_I2C0_FREQ_KHZ ((11 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
+#define NV_SI_RO_BOARD_I2C1_FREQ_KHZ ((12 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
+#define NV_SI_RO_BOARD_I2C2_10_FREQ_KHZ ((13 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
+#define NV_SI_RO_BOARD_I2C3_FREQ_KHZ ((14 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
+#define NV_SI_RO_BOARD_I2C9_FREQ_KHZ ((15 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
+#define NV_SI_RO_BOARD_2P_CFG ((16 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFF01 */
+#define NV_SI_RO_BOARD_S0_RCA0_CFG ((17 * 8) + NV_BOARD_PARAM_START)
+#define NV_SI_RO_BOARD_S0_RCA1_CFG ((18 * 8) + NV_BOARD_PARAM_START)
+#define NV_SI_RO_BOARD_S0_RCA2_CFG ((19 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000004 */
+#define NV_SI_RO_BOARD_S0_RCA3_CFG ((20 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000004 */
+#define NV_SI_RO_BOARD_S0_RCB0_LO_CFG ((21 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
+#define NV_SI_RO_BOARD_S0_RCB0_HI_CFG ((22 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
+#define NV_SI_RO_BOARD_S0_RCB1_LO_CFG ((23 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
+#define NV_SI_RO_BOARD_S0_RCB1_HI_CFG ((24 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
+#define NV_SI_RO_BOARD_S0_RCB2_LO_CFG ((25 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
+#define NV_SI_RO_BOARD_S0_RCB2_HI_CFG ((26 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
+#define NV_SI_RO_BOARD_S0_RCB3_LO_CFG ((27 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
+#define NV_SI_RO_BOARD_S0_RCB3_HI_CFG ((28 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
+#define NV_SI_RO_BOARD_S1_RCA0_CFG ((29 * 8) + NV_BOARD_PARAM_START)
+#define NV_SI_RO_BOARD_S1_RCA1_CFG ((30 * 8) + NV_BOARD_PARAM_START)
+#define NV_SI_RO_BOARD_S1_RCA2_CFG ((31 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */
+#define NV_SI_RO_BOARD_S1_RCA3_CFG ((32 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00030003 */
+#define NV_SI_RO_BOARD_S1_RCB0_LO_CFG ((33 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
+#define NV_SI_RO_BOARD_S1_RCB0_HI_CFG ((34 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
+#define NV_SI_RO_BOARD_S1_RCB1_LO_CFG ((35 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
+#define NV_SI_RO_BOARD_S1_RCB1_HI_CFG ((36 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
+#define NV_SI_RO_BOARD_S1_RCB2_LO_CFG ((37 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
+#define NV_SI_RO_BOARD_S1_RCB2_HI_CFG ((38 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
+#define NV_SI_RO_BOARD_S1_RCB3_LO_CFG ((39 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
+#define NV_SI_RO_BOARD_S1_RCB3_HI_CFG ((40 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
+#define NV_SI_RO_BOARD_T_LTLM_DELTA_P0 ((41 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000001 */
+#define NV_SI_RO_BOARD_T_LTLM_DELTA_P1 ((42 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000002 */
+#define NV_SI_RO_BOARD_T_LTLM_DELTA_P2 ((43 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
+#define NV_SI_RO_BOARD_T_LTLM_DELTA_P3 ((44 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000004 */
+#define NV_SI_RO_BOARD_T_LTLM_DELTA_M1 ((45 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
+#define NV_SI_RO_BOARD_T_LTLM_DELTA_M2 ((46 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFE */
+#define NV_SI_RO_BOARD_T_LTLM_DELTA_M3 ((47 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFD */
+#define NV_SI_RO_BOARD_P_LM_PID_P ((48 * 8) + NV_BOARD_PARAM_START)
+#define NV_SI_RO_BOARD_P_LM_PID_I ((49 * 8) + NV_BOARD_PARAM_START)
+#define NV_SI_RO_BOARD_P_LM_PID_I_L_THOLD ((50 * 8) + NV_BOARD_PARAM_START)
+#define NV_SI_RO_BOARD_P_LM_PID_I_H_THOLD ((51 * 8) + NV_BOARD_PARAM_START)
+#define NV_SI_RO_BOARD_P_LM_PID_D ((52 * 8) + NV_BOARD_PARAM_START)
+#define NV_SI_RO_BOARD_P_LM_EXP_SMOOTH_CONST ((53 * 8) + NV_BOARD_PARAM_START)
//
// NV_SI_RO_BOARD_TPM_ALG_ID: 0=Default to SHA256, 1=SHA1, 2=SHA256
// Any other value will lead to default digest.
@@ -616,7 +616,7 @@ //
// NOTE: Add before NV_BOARD_PARAM_MAX and increase its value
//
-#define NV_BOARD_PARAM_MAX ((255 * 8) + NV_BOARD_PARAM_START)
+#define NV_BOARD_PARAM_MAX ((255 * 8) + NV_BOARD_PARAM_START)
typedef UINT32 NVPARAM;
diff --git a/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h b/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h index 1e6905368c..a115619dfc 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h +++ b/Silicon/Ampere/AmpereAltraPkg/Include/Platform/Ac01.h @@ -12,35 +12,35 @@ //
// Number of supported sockets in the platform
//
-#define PLATFORM_CPU_MAX_SOCKET 2
+#define PLATFORM_CPU_MAX_SOCKET 2
//
// Maximum number of CPMs in the chip.
//
-#define PLATFORM_CPU_MAX_CPM (FixedPcdGet32 (PcdClusterCount))
+#define PLATFORM_CPU_MAX_CPM (FixedPcdGet32 (PcdClusterCount))
//
// Number of cores per CPM.
//
-#define PLATFORM_CPU_NUM_CORES_PER_CPM (FixedPcdGet32 (PcdCoreCount) / PLATFORM_CPU_MAX_CPM)
+#define PLATFORM_CPU_NUM_CORES_PER_CPM (FixedPcdGet32 (PcdCoreCount) / PLATFORM_CPU_MAX_CPM)
//
// Maximum number of cores supported.
//
-#define PLATFORM_CPU_MAX_NUM_CORES (PLATFORM_CPU_MAX_SOCKET * PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM)
+#define PLATFORM_CPU_MAX_NUM_CORES (PLATFORM_CPU_MAX_SOCKET * PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM)
-#define MAX_AMPERE_ALTRA_CORES 80
-#define MAX_AMPERE_ALTRA_MAX_CORES 128
+#define MAX_AMPERE_ALTRA_CORES 80
+#define MAX_AMPERE_ALTRA_MAX_CORES 128
//
// Maximum number of memory region
//
-#define PLATFORM_DRAM_INFO_MAX_REGION 16
+#define PLATFORM_DRAM_INFO_MAX_REGION 16
//
// Maximum number of DDR slots supported
//
-#define PLATFORM_DIMM_INFO_MAX_SLOT 32
+#define PLATFORM_DIMM_INFO_MAX_SLOT 32
//
// CSR Address base for slave socket
@@ -50,305 +50,305 @@ //
// SMpro EFUSE Shadow register
//
-#define SMPRO_EFUSE_SHADOW0 (FixedPcdGet64 (PcdSmproEfuseShadow0))
+#define SMPRO_EFUSE_SHADOW0 (FixedPcdGet64 (PcdSmproEfuseShadow0))
//
// 2P Configuration Register
//
-#define CFG2P_OFFSET 0x200
+#define CFG2P_OFFSET 0x200
//
// Slave socket present
//
-#define SLAVE_PRESENT_N BIT1
+#define SLAVE_PRESENT_N BIT1
//
// The maximum number of I2C bus
//
-#define AC01_I2C_MAX_BUS_NUM 4
+#define AC01_I2C_MAX_BUS_NUM 4
//
// The base address of DW I2C
//
-#define AC01_I2C_BASE_ADDRESS_LIST 0x1000026B0000ULL, 0x100002750000ULL, 0x100002770000ULL, 0x500002770000ULL
+#define AC01_I2C_BASE_ADDRESS_LIST 0x1000026B0000ULL, 0x100002750000ULL, 0x100002770000ULL, 0x500002770000ULL
//
// The Array of Soc Gpio Base Address
//
-#define AC01_GPIO_BASE_ADDRESS_LIST 0x1000026f0000, 0x1000026e0000, 0x1000027b0000, 0x1000026d0000, 0x5000026f0000, 0x5000026e0000, 0x5000027b0000, 0x5000026d0000
+#define AC01_GPIO_BASE_ADDRESS_LIST 0x1000026f0000, 0x1000026e0000, 0x1000027b0000, 0x1000026d0000, 0x5000026f0000, 0x5000026e0000, 0x5000027b0000, 0x5000026d0000
//
// The Array of Soc Gpi Base Address
//
-#define AC01_GPI_BASE_ADDRESS_LIST 0x1000026d0000, 0x5000026d0000
+#define AC01_GPI_BASE_ADDRESS_LIST 0x1000026d0000, 0x5000026d0000
//
// Number of Pins Per Each Contoller
//
-#define AC01_GPIO_PINS_PER_CONTROLLER 8
+#define AC01_GPIO_PINS_PER_CONTROLLER 8
//
// Number of Pins Each Socket
//
-#define AC01_GPIO_PINS_PER_SOCKET 32
+#define AC01_GPIO_PINS_PER_SOCKET 32
//
// Maximum number of memory controller supports NVDIMM-N per socket
//
-#define AC01_NVDIMM_MAX_MCU_PER_SOCKET 2
+#define AC01_NVDIMM_MAX_MCU_PER_SOCKET 2
//
// Maximum number of NVDIMM-N per memory controller
//
-#define AC01_NVDIMM_MAX_DIMM_PER_MCU 1
+#define AC01_NVDIMM_MAX_DIMM_PER_MCU 1
//
// Maximum number of NVDIMM region per socket
//
-#define AC01_NVDIMM_MAX_REGION_PER_SOCKET 2
+#define AC01_NVDIMM_MAX_REGION_PER_SOCKET 2
//
// Socket 0 base address of NVDIMM non-hashed region 0
//
-#define AC01_NVDIMM_SK0_NHASHED_REGION0_BASE 0x0B0000000000ULL
+#define AC01_NVDIMM_SK0_NHASHED_REGION0_BASE 0x0B0000000000ULL
//
// Socket 0 base address of NVDIMM non-hashed region 1
//
-#define AC01_NVDIMM_SK0_NHASHED_REGION1_BASE 0x0F0000000000ULL
+#define AC01_NVDIMM_SK0_NHASHED_REGION1_BASE 0x0F0000000000ULL
//
// Socket 1 base address of NVDIMM non-hashed region 0
//
-#define AC01_NVDIMM_SK1_NHASHED_REGION0_BASE 0x430000000000ULL
+#define AC01_NVDIMM_SK1_NHASHED_REGION0_BASE 0x430000000000ULL
//
// Socket 1 base address of NVDIMM non-hashed region 1
//
-#define AC01_NVDIMM_SK1_NHASHED_REGION1_BASE 0x470000000000ULL
+#define AC01_NVDIMM_SK1_NHASHED_REGION1_BASE 0x470000000000ULL
//
// DIMM ID of NVDIMM-N device 1
//
-#define AC01_NVDIMM_NVD1_DIMM_ID 6
+#define AC01_NVDIMM_NVD1_DIMM_ID 6
//
// DIMM ID of NVDIMM-N device 2
//
-#define AC01_NVDIMM_NVD2_DIMM_ID 14
+#define AC01_NVDIMM_NVD2_DIMM_ID 14
//
// DIMM ID of NVDIMM-N device 3
//
-#define AC01_NVDIMM_NVD3_DIMM_ID 22
+#define AC01_NVDIMM_NVD3_DIMM_ID 22
//
// DIMM ID of NVDIMM-N device 4
//
-#define AC01_NVDIMM_NVD4_DIMM_ID 30
+#define AC01_NVDIMM_NVD4_DIMM_ID 30
//
// NFIT device handle of NVDIMM-N device 1
//
-#define AC01_NVDIMM_NVD1_DEVICE_HANDLE 0x0330
+#define AC01_NVDIMM_NVD1_DEVICE_HANDLE 0x0330
//
// NFIT device handle of NVDIMM-N device 2
//
-#define AC01_NVDIMM_NVD2_DEVICE_HANDLE 0x0770
+#define AC01_NVDIMM_NVD2_DEVICE_HANDLE 0x0770
//
// NFIT device handle of NVDIMM-N device 3
//
-#define AC01_NVDIMM_NVD3_DEVICE_HANDLE 0x1330
+#define AC01_NVDIMM_NVD3_DEVICE_HANDLE 0x1330
//
// NFIT device handle of NVDIMM-N device 4
//
-#define AC01_NVDIMM_NVD4_DEVICE_HANDLE 0x1770
+#define AC01_NVDIMM_NVD4_DEVICE_HANDLE 0x1770
//
// Interleave ways of non-hashed NVDIMM-N
//
-#define AC01_NVDIMM_NHASHED_INTERLEAVE_WAYS 1
+#define AC01_NVDIMM_NHASHED_INTERLEAVE_WAYS 1
//
// Interleave ways of hashed NVDIMM-N
//
-#define AC01_NVDIMM_HASHED_INTERLEAVE_WAYS 2
+#define AC01_NVDIMM_HASHED_INTERLEAVE_WAYS 2
//
// Region offset of hashed NVDIMM-N
//
-#define AC01_NVDIMM_HASHED_REGION_OFFSET 512
+#define AC01_NVDIMM_HASHED_REGION_OFFSET 512
//
// The base address of GIC distributor registers
//
-#define AC01_GICD_MASTER_BASE_ADDRESS 0x100100000000
+#define AC01_GICD_MASTER_BASE_ADDRESS 0x100100000000
//
// The base address of master socket GIC redistributor registers
//
-#define AC01_GICR_MASTER_BASE_ADDRESS 0x100100140000
+#define AC01_GICR_MASTER_BASE_ADDRESS 0x100100140000
//
// The base address of slave socket GIC distributor registers
//
-#define AC01_GICD_SLAVE_BASE_ADDRESS 0x500100000000
+#define AC01_GICD_SLAVE_BASE_ADDRESS 0x500100000000
//
// The base address of slave socket GIC redistributor registers
//
-#define AC01_GICR_SLAVE_BASE_ADDRESS 0x500100140000
+#define AC01_GICR_SLAVE_BASE_ADDRESS 0x500100140000
//
// Socket 0 first RC
//
-#define SOCKET0_FIRST_RC 2
+#define SOCKET0_FIRST_RC 2
//
// Socket 0 last RC
//
-#define SOCKET0_LAST_RC 7
+#define SOCKET0_LAST_RC 7
//
// Socket 1 first RC
//
-#define SOCKET1_FIRST_RC 10
+#define SOCKET1_FIRST_RC 10
//
// Socket 1 last RC
//
-#define SOCKET1_LAST_RC 15
+#define SOCKET1_LAST_RC 15
//
// Socket bit offset of core UID.
//
-#define PLATFORM_SOCKET_UID_BIT_OFFSET 16
+#define PLATFORM_SOCKET_UID_BIT_OFFSET 16
//
// CPM bit offset of core UID.
//
-#define PLATFORM_CPM_UID_BIT_OFFSET 8
+#define PLATFORM_CPM_UID_BIT_OFFSET 8
//
// MPIDR manipulation
//
#define AC01_GET_MPIDR(SocketId, ClusterId, CoreId) \
(((SocketId) << 32) | ((ClusterId) << 16) | ((CoreId) << 8))
-#define AC01_GET_SOCKET_ID(Mpidr) (((Mpidr) & ARM_CORE_AFF3) >> 32)
-#define AC01_GET_CLUSTER_ID(Mpidr) (((Mpidr) & ARM_CORE_AFF2) >> 16)
-#define AC01_GET_CORE_ID(Mpidr) (((Mpidr) & ARM_CORE_AFF1) >> 8)
+#define AC01_GET_SOCKET_ID(Mpidr) (((Mpidr) & ARM_CORE_AFF3) >> 32)
+#define AC01_GET_CLUSTER_ID(Mpidr) (((Mpidr) & ARM_CORE_AFF2) >> 16)
+#define AC01_GET_CORE_ID(Mpidr) (((Mpidr) & ARM_CORE_AFF1) >> 8)
//
// Max number for AC01 PCIE Root Complexes
//
-#define AC01_PCIE_MAX_ROOT_COMPLEX 16
+#define AC01_PCIE_MAX_ROOT_COMPLEX 16
//
// Max number for AC01 PCIE Root Complexes per socket
//
-#define AC01_PCIE_MAX_RCS_PER_SOCKET 8
+#define AC01_PCIE_MAX_RCS_PER_SOCKET 8
//
// The size of IO space
//
-#define AC01_PCIE_IO_SIZE 0x2000
+#define AC01_PCIE_IO_SIZE 0x2000
//
// The base address of {TCU, CSR, MMCONFIG} Registers
//
-#define AC01_PCIE_CSR_BASE_LIST 0x33FFE0000000, 0x37FFE0000000, 0x3BFFE0000000, 0x3FFFE0000000, 0x23FFE0000000, 0x27FFE0000000, 0x2BFFE0000000, 0x2FFFE0000000, 0x73FFE0000000, 0x77FFE0000000, 0x7BFFE0000000, 0x7FFFE0000000, 0x63FFE0000000, 0x67FFE0000000, 0x6BFFE0000000, 0x6FFFE0000000
+#define AC01_PCIE_CSR_BASE_LIST 0x33FFE0000000, 0x37FFE0000000, 0x3BFFE0000000, 0x3FFFE0000000, 0x23FFE0000000, 0x27FFE0000000, 0x2BFFE0000000, 0x2FFFE0000000, 0x73FFE0000000, 0x77FFE0000000, 0x7BFFE0000000, 0x7FFFE0000000, 0x63FFE0000000, 0x67FFE0000000, 0x6BFFE0000000, 0x6FFFE0000000
//
// The base address of MMIO Registers
//
-#define AC01_PCIE_MMIO_BASE_LIST 0x300000000000, 0x340000000000, 0x380000000000, 0x3C0000000000, 0x200000000000, 0x240000000000, 0x280000000000, 0x2C0000000000, 0x700000000000, 0x740000000000, 0x780000000000, 0x7C0000000000, 0x600000000000, 0x640000000000, 0x680000000000, 0x6C0000000000
+#define AC01_PCIE_MMIO_BASE_LIST 0x300000000000, 0x340000000000, 0x380000000000, 0x3C0000000000, 0x200000000000, 0x240000000000, 0x280000000000, 0x2C0000000000, 0x700000000000, 0x740000000000, 0x780000000000, 0x7C0000000000, 0x600000000000, 0x640000000000, 0x680000000000, 0x6C0000000000
//
// The size of MMIO space
//
-#define AC01_PCIE_MMIO_SIZE_LIST 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000
+#define AC01_PCIE_MMIO_SIZE_LIST 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000, 0x3FFE0000000
//
// The base address of MMIO32 Registers
//
-#define AC01_PCIE_MMIO32_BASE_LIST 0x000020000000, 0x000028000000, 0x000030000000, 0x000038000000, 0x000004000000, 0x000008000000, 0x000010000000, 0x000018000000, 0x000060000000, 0x000068000000, 0x000070000000, 0x000078000000, 0x000040000000, 0x000048000000, 0x000050000000, 0x000058000000
+#define AC01_PCIE_MMIO32_BASE_LIST 0x000020000000, 0x000028000000, 0x000030000000, 0x000038000000, 0x000004000000, 0x000008000000, 0x000010000000, 0x000018000000, 0x000060000000, 0x000068000000, 0x000070000000, 0x000078000000, 0x000040000000, 0x000048000000, 0x000050000000, 0x000058000000
//
// The size of MMIO32 space
//
-#define AC01_PCIE_MMIO32_SIZE_LIST 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x4000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000
+#define AC01_PCIE_MMIO32_SIZE_LIST 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x4000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000, 0x8000000
//
// The base address of MMIO32 Registers
//
-#define AC01_PCIE_MMIO32_BASE_1P_LIST 0x000040000000, 0x000050000000, 0x000060000000, 0x000070000000, 0x000008000000, 0x000010000000, 0x000020000000, 0x000030000000, 0, 0, 0, 0, 0, 0, 0, 0
+#define AC01_PCIE_MMIO32_BASE_1P_LIST 0x000040000000, 0x000050000000, 0x000060000000, 0x000070000000, 0x000008000000, 0x000010000000, 0x000020000000, 0x000030000000, 0, 0, 0, 0, 0, 0, 0, 0
//
// The size of MMIO32 1P space
//
-#define AC01_PCIE_MMIO32_SIZE_1P_LIST 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x8000000, 0x10000000, 0x10000000, 0x10000000, 0, 0, 0, 0, 0, 0, 0, 0
+#define AC01_PCIE_MMIO32_SIZE_1P_LIST 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x8000000, 0x10000000, 0x10000000, 0x10000000, 0, 0, 0, 0, 0, 0, 0, 0
//
// DSDT RCA2 PCIe MMIO32 Attribute
//
-#define AC01_PCIE_RCA2_QMEM_LIST 0x0000000000000000, 0x0000000060000000, 0x000000006FFFFFFF, 0x0000000000000000, 0x0000000010000000
+#define AC01_PCIE_RCA2_QMEM_LIST 0x0000000000000000, 0x0000000060000000, 0x000000006FFFFFFF, 0x0000000000000000, 0x0000000010000000
//
// DSDT RCA3 PCIe MMIO32 Attribute
//
-#define AC01_PCIE_RCA3_QMEM_LIST 0x0000000000000000, 0x0000000070000000, 0x000000007FFFFFFF, 0x0000000000000000, 0x0000000010000000
+#define AC01_PCIE_RCA3_QMEM_LIST 0x0000000000000000, 0x0000000070000000, 0x000000007FFFFFFF, 0x0000000000000000, 0x0000000010000000
//
// DSDT RCB0 PCIe MMIO32 Attribute
//
-#define AC01_PCIE_RCB0_QMEM_LIST 0x0000000000000000, 0x0000000008000000, 0x000000000FFFFFFF, 0x0000000000000000, 0x0000000008000000
+#define AC01_PCIE_RCB0_QMEM_LIST 0x0000000000000000, 0x0000000008000000, 0x000000000FFFFFFF, 0x0000000000000000, 0x0000000008000000
//
// DSDT RCB1 PCIe MMIO32 Attribute
//
-#define AC01_PCIE_RCB1_QMEM_LIST 0x0000000000000000, 0x0000000010000000, 0x000000001FFFFFFF, 0x0000000000000000, 0x0000000010000000
+#define AC01_PCIE_RCB1_QMEM_LIST 0x0000000000000000, 0x0000000010000000, 0x000000001FFFFFFF, 0x0000000000000000, 0x0000000010000000
//
// DSDT RCB2 PCIe MMIO32 Attribute
//
-#define AC01_PCIE_RCB2_QMEM_LIST 0x0000000000000000, 0x0000000020000000, 0x000000002FFFFFFF, 0x0000000000000000, 0x0000000010000000
+#define AC01_PCIE_RCB2_QMEM_LIST 0x0000000000000000, 0x0000000020000000, 0x000000002FFFFFFF, 0x0000000000000000, 0x0000000010000000
//
// DSDT RCB3 PCIe MMIO32 Attribute
//
-#define AC01_PCIE_RCB3_QMEM_LIST 0x0000000000000000, 0x0000000030000000, 0x000000003FFFFFFF, 0x0000000000000000, 0x0000000010000000
+#define AC01_PCIE_RCB3_QMEM_LIST 0x0000000000000000, 0x0000000030000000, 0x000000003FFFFFFF, 0x0000000000000000, 0x0000000010000000
//
// TBU PMU IRQ array
//
-#define AC01_SMMU_TBU_PMU_IRQS_LIST 224, 230, 236, 242, 160, 170, 180, 190, 544, 550, 556, 562, 480, 490, 500, 510
+#define AC01_SMMU_TBU_PMU_IRQS_LIST 224, 230, 236, 242, 160, 170, 180, 190, 544, 550, 556, 562, 480, 490, 500, 510
//
// TCU PMU IRQ array
//
-#define AC01_SMMU_TCU_PMU_IRQS_LIST 256, 257, 258, 259, 260, 261, 262, 263, 576, 577, 578, 579, 580, 581, 582, 583
+#define AC01_SMMU_TCU_PMU_IRQS_LIST 256, 257, 258, 259, 260, 261, 262, 263, 576, 577, 578, 579, 580, 581, 582, 583
//
// Max TBU PMU of Root Complex A
//
-#define AC01_RCA_MAX_TBU_PMU 6
+#define AC01_RCA_MAX_TBU_PMU 6
//
// Max TBU PMU of Root Complex B
//
-#define AC01_RCB_MAX_TBU_PMU 10
+#define AC01_RCB_MAX_TBU_PMU 10
//
// TBU Base offset of Root Complex A
//
-#define AC01_RCA_TBU_PMU_OFFSET_LIST 0x40000, 0x60000, 0xA0000, 0xE0000, 0x100000, 0x140000
+#define AC01_RCA_TBU_PMU_OFFSET_LIST 0x40000, 0x60000, 0xA0000, 0xE0000, 0x100000, 0x140000
//
// TBU Base offset of Root Complex B
//
-#define AC01_RCB_TBU_PMU_OFFSET_LIST 0x40000, 0x60000, 0xA0000, 0xE0000, 0x120000, 0x160000, 0x180000, 0x1C0000, 0x200000, 0x240000
+#define AC01_RCB_TBU_PMU_OFFSET_LIST 0x40000, 0x60000, 0xA0000, 0xE0000, 0x120000, 0x160000, 0x180000, 0x1C0000, 0x200000, 0x240000
#endif /* PLATFORM_AC01_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c index c911ff7e21..ff97a7dd0d 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.c @@ -26,9 +26,9 @@ VOID
EnableDbiAccess (
- AC01_ROOT_COMPLEX *RootComplex,
- UINT32 PcieIndex,
- BOOLEAN EnableDbi
+ AC01_ROOT_COMPLEX *RootComplex,
+ UINT32 PcieIndex,
+ BOOLEAN EnableDbi
);
BOOLEAN
@@ -40,7 +40,7 @@ EndpointCfgReady ( BOOLEAN
PcieLinkUpCheck (
- IN AC01_PCIE_CONTROLLER *Pcie
+ IN AC01_PCIE_CONTROLLER *Pcie
);
/**
@@ -54,20 +54,20 @@ PcieLinkUpCheck ( **/
PHYSICAL_ADDRESS
GetCapabilityBase (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN UINT8 PcieIndex,
- IN BOOLEAN IsRootComplex,
- IN UINT16 ExtCapabilityId
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN UINT8 PcieIndex,
+ IN BOOLEAN IsRootComplex,
+ IN UINT16 ExtCapabilityId
)
{
- BOOLEAN IsExtCapability = FALSE;
- PHYSICAL_ADDRESS CfgBase;
- PHYSICAL_ADDRESS Ret = 0;
- PHYSICAL_ADDRESS RootComplexCfgBase;
- UINT32 CapabilityId;
- UINT32 NextCapabilityPtr;
- UINT32 Val;
- UINT32 RestoreVal;
+ BOOLEAN IsExtCapability = FALSE;
+ PHYSICAL_ADDRESS CfgBase;
+ PHYSICAL_ADDRESS Ret = 0;
+ PHYSICAL_ADDRESS RootComplexCfgBase;
+ UINT32 CapabilityId;
+ UINT32 NextCapabilityPtr;
+ UINT32 Val;
+ UINT32 RestoreVal;
RootComplexCfgBase = RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].DevNum << DEV_SHIFT);
if (!IsRootComplex) {
@@ -96,7 +96,7 @@ GetCapabilityBase ( goto _CheckCapEnd;
}
- Val = MmioRead32 (CfgBase + TYPE1_CAP_PTR_REG);
+ Val = MmioRead32 (CfgBase + TYPE1_CAP_PTR_REG);
NextCapabilityPtr = GET_LOW_8_BITS (Val);
// Loop untill desired capability is found else return 0
@@ -126,7 +126,7 @@ GetCapabilityBase ( }
if ((NextCapabilityPtr == 0) && !IsExtCapability) {
- IsExtCapability = TRUE;
+ IsExtCapability = TRUE;
NextCapabilityPtr = EXT_CAPABILITY_START_BASE;
}
@@ -156,14 +156,14 @@ _CheckCapEnd: STATIC
VOID
ConfigureEqualization (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN UINT8 PcieIndex
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN UINT8 PcieIndex
)
{
- PHYSICAL_ADDRESS CfgBase;
- PHYSICAL_ADDRESS Gen3RelatedAddr;
- PHYSICAL_ADDRESS Gen3EqControlAddr;
- UINT32 Val;
+ PHYSICAL_ADDRESS CfgBase;
+ PHYSICAL_ADDRESS Gen3RelatedAddr;
+ PHYSICAL_ADDRESS Gen3EqControlAddr;
+ UINT32 Val;
CfgBase = RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].DevNum << DEV_SHIFT);
@@ -172,7 +172,7 @@ ConfigureEqualization ( // GEN3_RELATED_OFF and GEN3_EQ_CONTROL_OFF. Both are shadow registers
// and controlled by GEN3_RELATED_OFF[25:24].
//
- Gen3RelatedAddr = CfgBase + GEN3_RELATED_OFF;
+ Gen3RelatedAddr = CfgBase + GEN3_RELATED_OFF;
Gen3EqControlAddr = CfgBase + GEN3_EQ_CONTROL_OFF;
//
@@ -219,15 +219,15 @@ ConfigureEqualization ( STATIC
VOID
ConfigurePresetGen3 (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN UINT8 PcieIndex
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN UINT8 PcieIndex
)
{
- PHYSICAL_ADDRESS LaneEqControlAddr;
- PHYSICAL_ADDRESS SpcieCapabilityBase;
- UINT32 Idx;
- UINT32 LinkWidth;
- UINT32 Val;
+ PHYSICAL_ADDRESS LaneEqControlAddr;
+ PHYSICAL_ADDRESS SpcieCapabilityBase;
+ UINT32 Idx;
+ UINT32 LinkWidth;
+ UINT32 Val;
// Get the Secondary PCI Express Extended capability base address
SpcieCapabilityBase = GetCapabilityBase (RootComplex, PcieIndex, TRUE, SPCIE_CAPABILITY_ID);
@@ -246,9 +246,9 @@ ConfigurePresetGen3 ( // Each register holds the Preset for 2 lanes
for (Idx = 0; Idx < (LinkWidth / 2); Idx++) {
LaneEqControlAddr = SpcieCapabilityBase + SPCIE_CAP_OFF_0C_REG + Idx * sizeof (UINT32);
- Val = MmioRead32 (LaneEqControlAddr);
- Val = DSP_TX_PRESET0_SET (Val, DEFAULT_GEN3_PRESET);
- Val = DSP_TX_PRESET1_SET (Val, DEFAULT_GEN3_PRESET);
+ Val = MmioRead32 (LaneEqControlAddr);
+ Val = DSP_TX_PRESET0_SET (Val, DEFAULT_GEN3_PRESET);
+ Val = DSP_TX_PRESET1_SET (Val, DEFAULT_GEN3_PRESET);
MmioWrite32 (LaneEqControlAddr, Val);
}
}
@@ -262,16 +262,16 @@ ConfigurePresetGen3 ( STATIC
VOID
ConfigurePresetGen4 (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN UINT8 PcieIndex
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN UINT8 PcieIndex
)
{
- PHYSICAL_ADDRESS LaneEqControlAddr;
- PHYSICAL_ADDRESS Pl16gCapabilityBase;
- UINT32 Idx;
- UINT32 LinkWidth;
- UINT32 Val;
- UINT8 Preset;
+ PHYSICAL_ADDRESS LaneEqControlAddr;
+ PHYSICAL_ADDRESS Pl16gCapabilityBase;
+ UINT32 Idx;
+ UINT32 LinkWidth;
+ UINT32 Val;
+ UINT8 Preset;
// Get the Physical Layer 16.0 GT/s Extended capability base address
Pl16gCapabilityBase = GetCapabilityBase (RootComplex, PcieIndex, TRUE, PL16G_CAPABILITY_ID);
@@ -295,19 +295,19 @@ ConfigurePresetGen4 ( if (LinkWidth == CAP_MAX_LINK_WIDTH_X2) {
LaneEqControlAddr = Pl16gCapabilityBase + PL16G_CAP_OFF_20H_REG;
- Val = MmioRead32 (LaneEqControlAddr);
- Val = DSP_16G_RXTX_PRESET0_SET (Val, Preset);
- Val = DSP_16G_RXTX_PRESET1_SET (Val, Preset);
+ Val = MmioRead32 (LaneEqControlAddr);
+ Val = DSP_16G_RXTX_PRESET0_SET (Val, Preset);
+ Val = DSP_16G_RXTX_PRESET1_SET (Val, Preset);
MmioWrite32 (LaneEqControlAddr, Val);
} else {
// Each register holds the Preset for 4 lanes
for (Idx = 0; Idx < (LinkWidth / 4); Idx++) {
LaneEqControlAddr = Pl16gCapabilityBase + PL16G_CAP_OFF_20H_REG + Idx * sizeof (UINT32);
- Val = MmioRead32 (LaneEqControlAddr);
- Val = DSP_16G_RXTX_PRESET0_SET (Val, Preset);
- Val = DSP_16G_RXTX_PRESET1_SET (Val, Preset);
- Val = DSP_16G_RXTX_PRESET2_SET (Val, Preset);
- Val = DSP_16G_RXTX_PRESET3_SET (Val, Preset);
+ Val = MmioRead32 (LaneEqControlAddr);
+ Val = DSP_16G_RXTX_PRESET0_SET (Val, Preset);
+ Val = DSP_16G_RXTX_PRESET1_SET (Val, Preset);
+ Val = DSP_16G_RXTX_PRESET2_SET (Val, Preset);
+ Val = DSP_16G_RXTX_PRESET3_SET (Val, Preset);
MmioWrite32 (LaneEqControlAddr, Val);
}
}
@@ -315,25 +315,25 @@ ConfigurePresetGen4 ( VOID
ProgramHostBridgeInfo (
- AC01_ROOT_COMPLEX *RootComplex
+ AC01_ROOT_COMPLEX *RootComplex
)
{
- EFI_STATUS Status;
- PHYSICAL_ADDRESS TargetAddress;
- UINT32 Val;
+ EFI_STATUS Status;
+ PHYSICAL_ADDRESS TargetAddress;
+ UINT32 Val;
// Program Root Complex Bifurcation
if (RootComplex->Active) {
if (RootComplex->Type == RootComplexTypeA) {
TargetAddress = RootComplex->HostBridgeBase + AC01_HOST_BRIDGE_RCA_DEV_MAP_REG;
- Status = MailboxMsgRegisterRead (RootComplex->Socket, TargetAddress, &Val);
+ Status = MailboxMsgRegisterRead (RootComplex->Socket, TargetAddress, &Val);
if (!RETURN_ERROR (Status)) {
Val = RCA_DEV_MAP_SET (Val, RootComplex->DevMapLow);
MailboxMsgRegisterWrite (RootComplex->Socket, TargetAddress, Val);
}
} else {
TargetAddress = RootComplex->HostBridgeBase + AC01_HOST_BRIDGE_RCB_DEV_MAP_REG;
- Status = MailboxMsgRegisterRead (RootComplex->Socket, TargetAddress, &Val);
+ Status = MailboxMsgRegisterRead (RootComplex->Socket, TargetAddress, &Val);
if (!RETURN_ERROR (Status)) {
Val = RCB_DEV_MAP_LOW_SET (Val, RootComplex->DevMapLow);
Val = RCB_DEV_MAP_HIGH_SET (Val, RootComplex->DevMapHigh);
@@ -344,7 +344,7 @@ ProgramHostBridgeInfo ( // Program Vendor ID and Device ID
TargetAddress = RootComplex->HostBridgeBase + AC01_HOST_BRIDGE_VENDOR_DEVICE_ID_REG;
- Status = MailboxMsgRegisterRead (RootComplex->Socket, TargetAddress, &Val);
+ Status = MailboxMsgRegisterRead (RootComplex->Socket, TargetAddress, &Val);
if (!RETURN_ERROR (Status)) {
Val = VENDOR_ID_SET (Val, AMPERE_PCIE_VENDOR_ID);
if (RootComplexTypeA == RootComplex->Type) {
@@ -352,164 +352,170 @@ ProgramHostBridgeInfo ( } else {
Val = DEVICE_ID_SET (Val, AC01_HOST_BRIDGE_DEVICE_ID_RCB);
}
+
MailboxMsgRegisterWrite (RootComplex->Socket, TargetAddress, Val);
}
}
VOID
ProgramRootPortInfo (
- AC01_ROOT_COMPLEX *RootComplex,
- UINT32 PcieIndex
+ AC01_ROOT_COMPLEX *RootComplex,
+ UINT32 PcieIndex
)
{
- PHYSICAL_ADDRESS CfgBase;
- PHYSICAL_ADDRESS TargetAddress;
- UINT32 Val;
+ PHYSICAL_ADDRESS CfgBase;
+ PHYSICAL_ADDRESS TargetAddress;
+ UINT32 Val;
CfgBase = RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].DevNum << DEV_SHIFT);
// Program Class Code
TargetAddress = CfgBase + TYPE1_CLASS_CODE_REV_ID_REG;
- Val = MmioRead32 (TargetAddress);
- Val = REVISION_ID_SET (Val, DEFAULT_REVISION_ID);
- Val = SUB_CLASS_CODE_SET (Val, DEFAULT_SUB_CLASS_CODE);
- Val = BASE_CLASS_CODE_SET (Val, DEFAULT_BASE_CLASS_CODE);
+ Val = MmioRead32 (TargetAddress);
+ Val = REVISION_ID_SET (Val, DEFAULT_REVISION_ID);
+ Val = SUB_CLASS_CODE_SET (Val, DEFAULT_SUB_CLASS_CODE);
+ Val = BASE_CLASS_CODE_SET (Val, DEFAULT_BASE_CLASS_CODE);
MmioWrite32 (TargetAddress, Val);
// Program Vendor ID and Device ID
TargetAddress = CfgBase + TYPE1_DEV_ID_VEND_ID_REG;
- Val = MmioRead32 (TargetAddress);
- Val = VENDOR_ID_SET (Val, AMPERE_PCIE_VENDOR_ID);
+ Val = MmioRead32 (TargetAddress);
+ Val = VENDOR_ID_SET (Val, AMPERE_PCIE_VENDOR_ID);
if (RootComplexTypeA == RootComplex->Type) {
Val = DEVICE_ID_SET (Val, AC01_PCIE_BRIDGE_DEVICE_ID_RCA + PcieIndex);
} else {
Val = DEVICE_ID_SET (Val, AC01_PCIE_BRIDGE_DEVICE_ID_RCB + PcieIndex);
}
+
MmioWrite32 (TargetAddress, Val);
}
VOID
ProgramLinkCapabilities (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN UINT8 PcieIndex
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN UINT8 PcieIndex
)
{
- PHYSICAL_ADDRESS CfgBase;
- PHYSICAL_ADDRESS TargetAddress;
- UINT32 Val;
- UINT8 MaxWidth;
- UINT8 MaxGen;
+ PHYSICAL_ADDRESS CfgBase;
+ PHYSICAL_ADDRESS TargetAddress;
+ UINT32 Val;
+ UINT8 MaxWidth;
+ UINT8 MaxGen;
CfgBase = RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].DevNum << DEV_SHIFT);
MaxWidth = RootComplex->Pcie[PcieIndex].MaxWidth;
- MaxGen = RootComplex->Pcie[PcieIndex].MaxGen;
+ MaxGen = RootComplex->Pcie[PcieIndex].MaxGen;
TargetAddress = CfgBase + PORT_LINK_CTRL_OFF;
- Val = MmioRead32 (TargetAddress);
+ Val = MmioRead32 (TargetAddress);
switch (MaxWidth) {
- case LINK_WIDTH_X2:
- Val = LINK_CAPABLE_SET (Val, LINK_CAPABLE_X2);
- break;
-
- case LINK_WIDTH_X4:
- Val = LINK_CAPABLE_SET (Val, LINK_CAPABLE_X4);
- break;
-
- case LINK_WIDTH_X8:
- Val = LINK_CAPABLE_SET (Val, LINK_CAPABLE_X8);
- break;
-
- case LINK_WIDTH_X16:
- default:
- Val = LINK_CAPABLE_SET (Val, LINK_CAPABLE_X16);
- break;
+ case LINK_WIDTH_X2:
+ Val = LINK_CAPABLE_SET (Val, LINK_CAPABLE_X2);
+ break;
+
+ case LINK_WIDTH_X4:
+ Val = LINK_CAPABLE_SET (Val, LINK_CAPABLE_X4);
+ break;
+
+ case LINK_WIDTH_X8:
+ Val = LINK_CAPABLE_SET (Val, LINK_CAPABLE_X8);
+ break;
+
+ case LINK_WIDTH_X16:
+ default:
+ Val = LINK_CAPABLE_SET (Val, LINK_CAPABLE_X16);
+ break;
}
+
MmioWrite32 (TargetAddress, Val);
TargetAddress = CfgBase + GEN2_CTRL_OFF;
- Val = MmioRead32 (TargetAddress);
+ Val = MmioRead32 (TargetAddress);
switch (MaxWidth) {
- case LINK_WIDTH_X2:
- Val = NUM_OF_LANES_SET (Val, NUM_OF_LANES_X2);
- break;
-
- case LINK_WIDTH_X4:
- Val = NUM_OF_LANES_SET (Val, NUM_OF_LANES_X4);
- break;
-
- case LINK_WIDTH_X8:
- Val = NUM_OF_LANES_SET (Val, NUM_OF_LANES_X8);
- break;
-
- case LINK_WIDTH_X16:
- default:
- Val = NUM_OF_LANES_SET (Val, NUM_OF_LANES_X16);
- break;
+ case LINK_WIDTH_X2:
+ Val = NUM_OF_LANES_SET (Val, NUM_OF_LANES_X2);
+ break;
+
+ case LINK_WIDTH_X4:
+ Val = NUM_OF_LANES_SET (Val, NUM_OF_LANES_X4);
+ break;
+
+ case LINK_WIDTH_X8:
+ Val = NUM_OF_LANES_SET (Val, NUM_OF_LANES_X8);
+ break;
+
+ case LINK_WIDTH_X16:
+ default:
+ Val = NUM_OF_LANES_SET (Val, NUM_OF_LANES_X16);
+ break;
}
+
MmioWrite32 (TargetAddress, Val);
TargetAddress = CfgBase + PCIE_CAPABILITY_BASE + LINK_CAPABILITIES_REG;
- Val = MmioRead32 (TargetAddress);
+ Val = MmioRead32 (TargetAddress);
switch (MaxWidth) {
- case LINK_WIDTH_X2:
- Val = CAP_MAX_LINK_WIDTH_SET (Val, CAP_MAX_LINK_WIDTH_X2);
- break;
-
- case LINK_WIDTH_X4:
- Val = CAP_MAX_LINK_WIDTH_SET (Val, CAP_MAX_LINK_WIDTH_X4);
- break;
-
- case LINK_WIDTH_X8:
- Val = CAP_MAX_LINK_WIDTH_SET (Val, CAP_MAX_LINK_WIDTH_X8);
- break;
-
- case LINK_WIDTH_X16:
- default:
- Val = CAP_MAX_LINK_WIDTH_SET (Val, CAP_MAX_LINK_WIDTH_X16);
- break;
+ case LINK_WIDTH_X2:
+ Val = CAP_MAX_LINK_WIDTH_SET (Val, CAP_MAX_LINK_WIDTH_X2);
+ break;
+
+ case LINK_WIDTH_X4:
+ Val = CAP_MAX_LINK_WIDTH_SET (Val, CAP_MAX_LINK_WIDTH_X4);
+ break;
+
+ case LINK_WIDTH_X8:
+ Val = CAP_MAX_LINK_WIDTH_SET (Val, CAP_MAX_LINK_WIDTH_X8);
+ break;
+
+ case LINK_WIDTH_X16:
+ default:
+ Val = CAP_MAX_LINK_WIDTH_SET (Val, CAP_MAX_LINK_WIDTH_X16);
+ break;
}
switch (MaxGen) {
- case LINK_SPEED_GEN1:
- Val = CAP_MAX_LINK_SPEED_SET (Val, MAX_LINK_SPEED_25);
- break;
+ case LINK_SPEED_GEN1:
+ Val = CAP_MAX_LINK_SPEED_SET (Val, MAX_LINK_SPEED_25);
+ break;
- case LINK_SPEED_GEN2:
- Val = CAP_MAX_LINK_SPEED_SET (Val, MAX_LINK_SPEED_50);
- break;
+ case LINK_SPEED_GEN2:
+ Val = CAP_MAX_LINK_SPEED_SET (Val, MAX_LINK_SPEED_50);
+ break;
- case LINK_SPEED_GEN3:
- Val = CAP_MAX_LINK_SPEED_SET (Val, MAX_LINK_SPEED_80);
- break;
+ case LINK_SPEED_GEN3:
+ Val = CAP_MAX_LINK_SPEED_SET (Val, MAX_LINK_SPEED_80);
+ break;
- default:
- Val = CAP_MAX_LINK_SPEED_SET (Val, MAX_LINK_SPEED_160);
- break;
+ default:
+ Val = CAP_MAX_LINK_SPEED_SET (Val, MAX_LINK_SPEED_160);
+ break;
}
+
// Enable ASPM Capability
Val = CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SET (Val, L0S_L1_SUPPORTED);
MmioWrite32 (TargetAddress, Val);
TargetAddress = CfgBase + PCIE_CAPABILITY_BASE + LINK_CONTROL2_LINK_STATUS2_REG;
- Val = MmioRead32 (TargetAddress);
+ Val = MmioRead32 (TargetAddress);
switch (MaxGen) {
- case LINK_SPEED_GEN1:
- Val = CAP_TARGET_LINK_SPEED_SET (Val, MAX_LINK_SPEED_25);
- break;
+ case LINK_SPEED_GEN1:
+ Val = CAP_TARGET_LINK_SPEED_SET (Val, MAX_LINK_SPEED_25);
+ break;
- case LINK_SPEED_GEN2:
- Val = CAP_TARGET_LINK_SPEED_SET (Val, MAX_LINK_SPEED_50);
- break;
+ case LINK_SPEED_GEN2:
+ Val = CAP_TARGET_LINK_SPEED_SET (Val, MAX_LINK_SPEED_50);
+ break;
- case LINK_SPEED_GEN3:
- Val = CAP_TARGET_LINK_SPEED_SET (Val, MAX_LINK_SPEED_80);
- break;
+ case LINK_SPEED_GEN3:
+ Val = CAP_TARGET_LINK_SPEED_SET (Val, MAX_LINK_SPEED_80);
+ break;
- default:
- Val = CAP_TARGET_LINK_SPEED_SET (Val, MAX_LINK_SPEED_160);
- break;
+ default:
+ Val = CAP_TARGET_LINK_SPEED_SET (Val, MAX_LINK_SPEED_160);
+ break;
}
+
MmioWrite32 (TargetAddress, Val);
}
@@ -520,35 +526,35 @@ DisableCompletionTimeOut ( IN BOOLEAN IsMask
)
{
- PHYSICAL_ADDRESS CfgBase;
- PHYSICAL_ADDRESS TargetAddress;
- UINT32 Val;
+ PHYSICAL_ADDRESS CfgBase;
+ PHYSICAL_ADDRESS TargetAddress;
+ UINT32 Val;
CfgBase = RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].DevNum << DEV_SHIFT);
TargetAddress = CfgBase + AER_CAPABILITY_BASE + UNCORR_ERR_MASK_OFF;
- Val = MmioRead32 (TargetAddress);
- Val = CMPLT_TIMEOUT_ERR_MASK_SET (Val, IsMask ? 1 : 0);
+ Val = MmioRead32 (TargetAddress);
+ Val = CMPLT_TIMEOUT_ERR_MASK_SET (Val, IsMask ? 1 : 0);
MmioWrite32 (TargetAddress, Val);
}
BOOLEAN
EnableItsMemory (
- AC01_ROOT_COMPLEX *RootComplex,
- UINT32 PcieIndex
+ AC01_ROOT_COMPLEX *RootComplex,
+ UINT32 PcieIndex
)
{
- PHYSICAL_ADDRESS CsrBase;
- PHYSICAL_ADDRESS TargetAddress;
- UINT32 TimeOut;
- UINT32 Val;
+ PHYSICAL_ADDRESS CsrBase;
+ PHYSICAL_ADDRESS TargetAddress;
+ UINT32 TimeOut;
+ UINT32 Val;
CsrBase = RootComplex->Pcie[PcieIndex].CsrBase;
// Clear memory shutdown
TargetAddress = CsrBase + AC01_PCIE_CORE_RAM_SHUTDOWN_REG;
- Val = MmioRead32 (TargetAddress);
- Val = SD_SET (Val, 0);
+ Val = MmioRead32 (TargetAddress);
+ Val = SD_SET (Val, 0);
MmioWrite32 (TargetAddress, Val);
// Poll till ITS Memory is ready
@@ -568,26 +574,26 @@ EnableItsMemory ( BOOLEAN
EnableAxiPipeClock (
- AC01_ROOT_COMPLEX *RootComplex,
- UINT32 PcieIndex
+ AC01_ROOT_COMPLEX *RootComplex,
+ UINT32 PcieIndex
)
{
- PHYSICAL_ADDRESS CsrBase;
- PHYSICAL_ADDRESS TargetAddress;
- UINT32 TimeOut;
- UINT32 Val;
+ PHYSICAL_ADDRESS CsrBase;
+ PHYSICAL_ADDRESS TargetAddress;
+ UINT32 TimeOut;
+ UINT32 Val;
CsrBase = RootComplex->Pcie[PcieIndex].CsrBase;
// Enable subsystem clock and release reset
TargetAddress = CsrBase + AC01_PCIE_CORE_CLOCK_REG;
- Val = MmioRead32 (TargetAddress);
- Val = AXIPIPE_SET (Val, 1);
+ Val = MmioRead32 (TargetAddress);
+ Val = AXIPIPE_SET (Val, 1);
MmioWrite32 (TargetAddress, Val);
TargetAddress = CsrBase + AC01_PCIE_CORE_RESET_REG;
- Val = MmioRead32 (TargetAddress);
- Val = DWC_PCIE_SET (Val, 0);
+ Val = MmioRead32 (TargetAddress);
+ Val = DWC_PCIE_SET (Val, 0);
MmioWrite32 (TargetAddress, Val);
//
@@ -613,13 +619,13 @@ EnableAxiPipeClock ( VOID
SetLinkTimeout (
- AC01_ROOT_COMPLEX *RootComplex,
- UINT32 PcieIndex,
- UINTN Timeout
+ AC01_ROOT_COMPLEX *RootComplex,
+ UINT32 PcieIndex,
+ UINTN Timeout
)
{
- PHYSICAL_ADDRESS TargetAddress;
- UINT32 Val;
+ PHYSICAL_ADDRESS TargetAddress;
+ UINT32 Val;
TargetAddress = RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].DevNum << DEV_SHIFT)
+ AMBA_LINK_TIMEOUT_OFF;
@@ -631,13 +637,13 @@ SetLinkTimeout ( VOID
StartLinkTraining (
- AC01_ROOT_COMPLEX *RootComplex,
- UINT32 PcieIndex,
- BOOLEAN StartLink
+ AC01_ROOT_COMPLEX *RootComplex,
+ UINT32 PcieIndex,
+ BOOLEAN StartLink
)
{
- PHYSICAL_ADDRESS TargetAddress;
- UINT32 Val;
+ PHYSICAL_ADDRESS TargetAddress;
+ UINT32 Val;
TargetAddress = RootComplex->Pcie[PcieIndex].CsrBase + AC01_PCIE_CORE_LINK_CTRL_REG;
@@ -648,13 +654,13 @@ StartLinkTraining ( VOID
EnableDbiAccess (
- AC01_ROOT_COMPLEX *RootComplex,
- UINT32 PcieIndex,
- BOOLEAN EnableDbi
+ AC01_ROOT_COMPLEX *RootComplex,
+ UINT32 PcieIndex,
+ BOOLEAN EnableDbi
)
{
- PHYSICAL_ADDRESS TargetAddress;
- UINT32 Val;
+ PHYSICAL_ADDRESS TargetAddress;
+ UINT32 Val;
TargetAddress = RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].DevNum << DEV_SHIFT)
+ MISC_CONTROL_1_OFF;
@@ -666,163 +672,163 @@ EnableDbiAccess ( VOID
Ac01PcieUpdateMaxWidth (
- IN AC01_ROOT_COMPLEX *RootComplex
+ IN AC01_ROOT_COMPLEX *RootComplex
)
{
if (RootComplex->Type == RootComplexTypeA) {
switch (RootComplex->DevMapLow) {
- case DevMapMode1:
- RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X16;
- break;
+ case DevMapMode1:
+ RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X16;
+ break;
- case DevMapMode2:
- RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
- RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
- break;
+ case DevMapMode2:
+ RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
+ RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
+ break;
- case DevMapMode3:
- RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
- RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
- RootComplex->Pcie[PcieController3].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
- break;
+ case DevMapMode3:
+ RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
+ RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+ RootComplex->Pcie[PcieController3].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+ break;
- case DevMapMode4:
- RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
- RootComplex->Pcie[PcieController1].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
- RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
- RootComplex->Pcie[PcieController3].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
- break;
+ case DevMapMode4:
+ RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+ RootComplex->Pcie[PcieController1].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+ RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+ RootComplex->Pcie[PcieController3].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+ break;
- default:
- ASSERT (FALSE);
+ default:
+ ASSERT (FALSE);
}
} else {
switch (RootComplex->DevMapLow) {
- case DevMapMode1:
- RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
- break;
+ case DevMapMode1:
+ RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
+ break;
- case DevMapMode2:
- RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
- RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
- break;
+ case DevMapMode2:
+ RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+ RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+ break;
- case DevMapMode3:
- RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
- RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
- RootComplex->Pcie[PcieController3].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
- break;
+ case DevMapMode3:
+ RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+ RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+ RootComplex->Pcie[PcieController3].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+ break;
- case DevMapMode4:
- RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
- RootComplex->Pcie[PcieController1].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
- RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
- RootComplex->Pcie[PcieController3].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
- break;
+ case DevMapMode4:
+ RootComplex->Pcie[PcieController0].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+ RootComplex->Pcie[PcieController1].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+ RootComplex->Pcie[PcieController2].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+ RootComplex->Pcie[PcieController3].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+ break;
- default:
- ASSERT (FALSE);
+ default:
+ ASSERT (FALSE);
}
switch (RootComplex->DevMapHigh) {
- case DevMapMode1:
- RootComplex->Pcie[PcieController4].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
- break;
+ case DevMapMode1:
+ RootComplex->Pcie[PcieController4].MaxWidth = CAP_MAX_LINK_WIDTH_X8;
+ break;
- case DevMapMode2:
- RootComplex->Pcie[PcieController4].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
- RootComplex->Pcie[PcieController6].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
- break;
+ case DevMapMode2:
+ RootComplex->Pcie[PcieController4].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+ RootComplex->Pcie[PcieController6].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+ break;
- case DevMapMode3:
- RootComplex->Pcie[PcieController4].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
- RootComplex->Pcie[PcieController6].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
- RootComplex->Pcie[PcieController7].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
- break;
+ case DevMapMode3:
+ RootComplex->Pcie[PcieController4].MaxWidth = CAP_MAX_LINK_WIDTH_X4;
+ RootComplex->Pcie[PcieController6].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+ RootComplex->Pcie[PcieController7].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+ break;
- case DevMapMode4:
- RootComplex->Pcie[PcieController4].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
- RootComplex->Pcie[PcieController5].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
- RootComplex->Pcie[PcieController6].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
- RootComplex->Pcie[PcieController7].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
- break;
+ case DevMapMode4:
+ RootComplex->Pcie[PcieController4].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+ RootComplex->Pcie[PcieController5].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+ RootComplex->Pcie[PcieController6].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+ RootComplex->Pcie[PcieController7].MaxWidth = CAP_MAX_LINK_WIDTH_X2;
+ break;
- default:
- ASSERT (FALSE);
+ default:
+ ASSERT (FALSE);
}
}
}
VOID
Ac01PcieUpdateActive (
- IN AC01_ROOT_COMPLEX *RootComplex
+ IN AC01_ROOT_COMPLEX *RootComplex
)
{
switch (RootComplex->DevMapLow) {
- case DevMapMode1:
- RootComplex->Pcie[PcieController0].Active = TRUE;
- RootComplex->Pcie[PcieController1].Active = FALSE;
- RootComplex->Pcie[PcieController2].Active = FALSE;
- RootComplex->Pcie[PcieController3].Active = FALSE;
- break;
-
- case DevMapMode2:
- RootComplex->Pcie[PcieController0].Active = TRUE;
- RootComplex->Pcie[PcieController1].Active = FALSE;
- RootComplex->Pcie[PcieController2].Active = TRUE;
- RootComplex->Pcie[PcieController3].Active = FALSE;
- break;
-
- case DevMapMode3:
- RootComplex->Pcie[PcieController0].Active = TRUE;
- RootComplex->Pcie[PcieController1].Active = FALSE;
- RootComplex->Pcie[PcieController2].Active = TRUE;
- RootComplex->Pcie[PcieController3].Active = TRUE;
- break;
-
- case DevMapMode4:
- RootComplex->Pcie[PcieController0].Active = TRUE;
- RootComplex->Pcie[PcieController1].Active = TRUE;
- RootComplex->Pcie[PcieController2].Active = TRUE;
- RootComplex->Pcie[PcieController3].Active = TRUE;
- break;
-
- default:
- ASSERT (FALSE);
- }
-
- if (RootComplex->Type == RootComplexTypeB) {
- switch (RootComplex->DevMapHigh) {
case DevMapMode1:
- RootComplex->Pcie[PcieController4].Active = TRUE;
- RootComplex->Pcie[PcieController5].Active = FALSE;
- RootComplex->Pcie[PcieController6].Active = FALSE;
- RootComplex->Pcie[PcieController7].Active = FALSE;
+ RootComplex->Pcie[PcieController0].Active = TRUE;
+ RootComplex->Pcie[PcieController1].Active = FALSE;
+ RootComplex->Pcie[PcieController2].Active = FALSE;
+ RootComplex->Pcie[PcieController3].Active = FALSE;
break;
case DevMapMode2:
- RootComplex->Pcie[PcieController4].Active = TRUE;
- RootComplex->Pcie[PcieController5].Active = FALSE;
- RootComplex->Pcie[PcieController6].Active = TRUE;
- RootComplex->Pcie[PcieController7].Active = FALSE;
+ RootComplex->Pcie[PcieController0].Active = TRUE;
+ RootComplex->Pcie[PcieController1].Active = FALSE;
+ RootComplex->Pcie[PcieController2].Active = TRUE;
+ RootComplex->Pcie[PcieController3].Active = FALSE;
break;
case DevMapMode3:
- RootComplex->Pcie[PcieController4].Active = TRUE;
- RootComplex->Pcie[PcieController5].Active = FALSE;
- RootComplex->Pcie[PcieController6].Active = TRUE;
- RootComplex->Pcie[PcieController7].Active = TRUE;
+ RootComplex->Pcie[PcieController0].Active = TRUE;
+ RootComplex->Pcie[PcieController1].Active = FALSE;
+ RootComplex->Pcie[PcieController2].Active = TRUE;
+ RootComplex->Pcie[PcieController3].Active = TRUE;
break;
case DevMapMode4:
- RootComplex->Pcie[PcieController4].Active = TRUE;
- RootComplex->Pcie[PcieController5].Active = TRUE;
- RootComplex->Pcie[PcieController6].Active = TRUE;
- RootComplex->Pcie[PcieController7].Active = TRUE;
+ RootComplex->Pcie[PcieController0].Active = TRUE;
+ RootComplex->Pcie[PcieController1].Active = TRUE;
+ RootComplex->Pcie[PcieController2].Active = TRUE;
+ RootComplex->Pcie[PcieController3].Active = TRUE;
break;
default:
ASSERT (FALSE);
+ }
+
+ if (RootComplex->Type == RootComplexTypeB) {
+ switch (RootComplex->DevMapHigh) {
+ case DevMapMode1:
+ RootComplex->Pcie[PcieController4].Active = TRUE;
+ RootComplex->Pcie[PcieController5].Active = FALSE;
+ RootComplex->Pcie[PcieController6].Active = FALSE;
+ RootComplex->Pcie[PcieController7].Active = FALSE;
+ break;
+
+ case DevMapMode2:
+ RootComplex->Pcie[PcieController4].Active = TRUE;
+ RootComplex->Pcie[PcieController5].Active = FALSE;
+ RootComplex->Pcie[PcieController6].Active = TRUE;
+ RootComplex->Pcie[PcieController7].Active = FALSE;
+ break;
+
+ case DevMapMode3:
+ RootComplex->Pcie[PcieController4].Active = TRUE;
+ RootComplex->Pcie[PcieController5].Active = FALSE;
+ RootComplex->Pcie[PcieController6].Active = TRUE;
+ RootComplex->Pcie[PcieController7].Active = TRUE;
+ break;
+
+ case DevMapMode4:
+ RootComplex->Pcie[PcieController4].Active = TRUE;
+ RootComplex->Pcie[PcieController5].Active = TRUE;
+ RootComplex->Pcie[PcieController6].Active = TRUE;
+ RootComplex->Pcie[PcieController7].Active = TRUE;
+ break;
+
+ default:
+ ASSERT (FALSE);
}
}
}
@@ -841,7 +847,7 @@ Ac01PcieCorrectBifurcation ( Status = EFI_SUCCESS;
- if (RootComplex == NULL || LinkCap == NULL || Bifur == NULL) {
+ if ((RootComplex == NULL) || (LinkCap == NULL) || (Bifur == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -864,62 +870,67 @@ Ac01PcieCorrectBifurcation ( }
switch (Count) {
- case 3:
- // Bifurcation should be X/0/X/X
- *Bifur = BIFURCATION_X0XX;
- break;
-
- case 2:
- if (LinkCap[PcieController0].Uint32 != 0) {
- if (LinkCap[PcieController2].Uint32) {
- *Bifur = BIFURCATION_X0X0;
- } else {
- *Bifur = BIFURCATION_X0XX;
- }
- } else {
- *Bifur = BIFURCATION_XXXX;
- }
- break;
-
- case 1:
- if (LinkCap[PcieController0].Uint32 != 0) {
- *Bifur = BIFURCATION_X000;
- } else if (LinkCap[PcieController2].Uint32 != 0) {
- *Bifur = BIFURCATION_X0X0;
- } else {
- // In the lane reverse case, we choose best width
- switch (LinkCap[PcieController3].Bits.MaxLinkWidth) { /* MAX_SPEED [9:4] */
- case CAP_MAX_LINK_WIDTH_X1:
- case CAP_MAX_LINK_WIDTH_X2:
- *Bifur = BIFURCATION_XXXX;
- break;
-
- case CAP_MAX_LINK_WIDTH_X4:
- if (RootComplex->Type == RootComplexTypeA) {
- *Bifur = BIFURCATION_XXXX;
- } else {
- *Bifur = BIFURCATION_X0X0;
- }
- break;
+ case 3:
+ // Bifurcation should be X/0/X/X
+ *Bifur = BIFURCATION_X0XX;
+ break;
- case CAP_MAX_LINK_WIDTH_X8:
- if (RootComplex->Type == RootComplexTypeA) {
+ case 2:
+ if (LinkCap[PcieController0].Uint32 != 0) {
+ if (LinkCap[PcieController2].Uint32) {
*Bifur = BIFURCATION_X0X0;
} else {
- *Bifur = BIFURCATION_X000;
+ *Bifur = BIFURCATION_X0XX;
}
- break;
+ } else {
+ *Bifur = BIFURCATION_XXXX;
+ }
- default:
+ break;
+
+ case 1:
+ if (LinkCap[PcieController0].Uint32 != 0) {
*Bifur = BIFURCATION_X000;
- break;
+ } else if (LinkCap[PcieController2].Uint32 != 0) {
+ *Bifur = BIFURCATION_X0X0;
+ } else {
+ // In the lane reverse case, we choose best width
+ switch (LinkCap[PcieController3].Bits.MaxLinkWidth) {
+ /* MAX_SPEED [9:4] */
+ case CAP_MAX_LINK_WIDTH_X1:
+ case CAP_MAX_LINK_WIDTH_X2:
+ *Bifur = BIFURCATION_XXXX;
+ break;
+
+ case CAP_MAX_LINK_WIDTH_X4:
+ if (RootComplex->Type == RootComplexTypeA) {
+ *Bifur = BIFURCATION_XXXX;
+ } else {
+ *Bifur = BIFURCATION_X0X0;
+ }
+
+ break;
+
+ case CAP_MAX_LINK_WIDTH_X8:
+ if (RootComplex->Type == RootComplexTypeA) {
+ *Bifur = BIFURCATION_X0X0;
+ } else {
+ *Bifur = BIFURCATION_X000;
+ }
+
+ break;
+
+ default:
+ *Bifur = BIFURCATION_X000;
+ break;
+ }
}
- }
- break;
- default:
- Status = EFI_NOT_AVAILABLE_YET;
- break;
+ break;
+
+ default:
+ Status = EFI_NOT_AVAILABLE_YET;
+ break;
}
return Status;
@@ -937,17 +948,17 @@ Ac01PcieCorrectBifurcation ( **/
RETURN_STATUS
Ac01PcieCoreSetupRC (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN BOOLEAN ReInit,
- IN UINT8 ReInitPcieIndex
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN BOOLEAN ReInit,
+ IN UINT8 ReInitPcieIndex
)
{
- PHYSICAL_ADDRESS CfgBase;
- PHYSICAL_ADDRESS CsrBase;
- PHYSICAL_ADDRESS TargetAddress;
- RETURN_STATUS Status;
- UINT32 Val;
- UINT8 PcieIndex;
+ PHYSICAL_ADDRESS CfgBase;
+ PHYSICAL_ADDRESS CsrBase;
+ PHYSICAL_ADDRESS TargetAddress;
+ RETURN_STATUS Status;
+ UINT32 Val;
+ UINT8 PcieIndex;
BOOLEAN AutoLaneBifurcationEnabled = FALSE;
PCI_REG_PCIE_LINK_CAPABILITY LinkCap[MaxPcieController];
AC01_PCIE_CONTROLLER *Pcie;
@@ -971,11 +982,13 @@ AutoLaneBifurcationRetry: if (!Pcie->Active || !PcieLinkUpCheck (Pcie)) {
continue;
}
+
DEBUG ((DEBUG_INFO, "RootComplex->ID:%d Port:%d link up\n", RootComplex->ID, PcieIndex));
TargetAddress = GetCapabilityBase (RootComplex, PcieIndex, FALSE, EFI_PCI_CAPABILITY_ID_PCIEXP);
if (TargetAddress == 0) {
continue;
}
+
LinkCap[PcieIndex].Uint32 = MmioRead32 (TargetAddress + LINK_CAPABILITIES_REG);
}
@@ -1038,7 +1051,6 @@ AutoLaneBifurcationRetry: // Setup each controller
for (PcieIndex = 0; PcieIndex < RootComplex->MaxPcieController; PcieIndex++) {
-
if (ReInit) {
PcieIndex = ReInitPcieIndex;
}
@@ -1054,7 +1066,7 @@ AutoLaneBifurcationRetry: // Put Controller into reset if not in reset already
TargetAddress = CsrBase + AC01_PCIE_CORE_RESET_REG;
- Val = MmioRead32 (TargetAddress);
+ Val = MmioRead32 (TargetAddress);
if (!(Val & RESET_MASK)) {
Val = DWC_PCIE_SET (Val, ASSERT_RESET);
MmioWrite32 (TargetAddress, Val);
@@ -1092,19 +1104,19 @@ AutoLaneBifurcationRetry: // Program the power limit
TargetAddress = CfgBase + PCIE_CAPABILITY_BASE + SLOT_CAPABILITIES_REG;
- Val = MmioRead32 (TargetAddress);
+ Val = MmioRead32 (TargetAddress);
// In order to detect the NVMe after OS boots successfully but
// that NVMe's not present previously. Hot Plug Slot Capable
// will help PCI Linux driver to initialize its slot iomem resource
// which is used for detecting the disk when it's inserted.
- Val = SLOT_HPC_SET(Val, 1);
+ Val = SLOT_HPC_SET (Val, 1);
Val = SLOT_CAP_SLOT_POWER_LIMIT_VALUE_SET (Val, SLOT_POWER_LIMIT_75W);
MmioWrite32 (TargetAddress, Val);
// Program DTI for ATS support
TargetAddress = CfgBase + DTIM_CTRL0_OFF;
- Val = MmioRead32 (TargetAddress);
- Val = DTIM_CTRL0_ROOT_PORT_ID_SET (Val, 0);
+ Val = MmioRead32 (TargetAddress);
+ Val = DTIM_CTRL0_ROOT_PORT_ID_SET (Val, 0);
MmioWrite32 (TargetAddress, Val);
//
@@ -1117,15 +1129,15 @@ AutoLaneBifurcationRetry: // Set Zero byte request handling
TargetAddress = CfgBase + FILTER_MASK_2_OFF;
- Val = MmioRead32 (TargetAddress);
- Val = CX_FLT_MASK_VENMSG0_DROP_SET (Val, 0);
- Val = CX_FLT_MASK_VENMSG1_DROP_SET (Val, 0);
- Val = CX_FLT_MASK_DABORT_4UCPL_SET (Val, 0);
+ Val = MmioRead32 (TargetAddress);
+ Val = CX_FLT_MASK_VENMSG0_DROP_SET (Val, 0);
+ Val = CX_FLT_MASK_VENMSG1_DROP_SET (Val, 0);
+ Val = CX_FLT_MASK_DABORT_4UCPL_SET (Val, 0);
MmioWrite32 (TargetAddress, Val);
TargetAddress = CfgBase + AMBA_ORDERING_CTRL_OFF;
- Val = MmioRead32 (TargetAddress);
- Val = AX_MSTR_ZEROLREAD_FW_SET (Val, 0);
+ Val = MmioRead32 (TargetAddress);
+ Val = AX_MSTR_ZEROLREAD_FW_SET (Val, 0);
MmioWrite32 (TargetAddress, Val);
//
@@ -1133,20 +1145,20 @@ AutoLaneBifurcationRetry: // Set Completion with CA/UR handling non-CFG Request
//
TargetAddress = CfgBase + AMBA_ERROR_RESPONSE_DEFAULT_OFF;
- Val = MmioRead32 (TargetAddress);
+ Val = MmioRead32 (TargetAddress);
// 0x2: OKAY with FFFF_0001 and FFFF_FFFF
Val = AMBA_ERROR_RESPONSE_CRS_SET (Val, 0x2);
MmioWrite32 (TargetAddress, Val);
// Set Legacy PCIE interrupt map to INTA
TargetAddress = CfgBase + BRIDGE_CTRL_INT_PIN_INT_LINE_REG;
- Val = MmioRead32 (TargetAddress);
- Val = INT_PIN_SET (Val, IRQ_INT_A);
+ Val = MmioRead32 (TargetAddress);
+ Val = INT_PIN_SET (Val, IRQ_INT_A);
MmioWrite32 (TargetAddress, Val);
TargetAddress = CsrBase + AC01_PCIE_CORE_IRQ_SEL_REG;
- Val = MmioRead32 (TargetAddress);
- Val = INTPIN_SET (Val, IRQ_INT_A);
+ Val = MmioRead32 (TargetAddress);
+ Val = INTPIN_SET (Val, IRQ_INT_A);
MmioWrite32 (TargetAddress, Val);
if (RootComplex->Pcie[PcieIndex].MaxGen >= LINK_SPEED_GEN2) {
@@ -1172,15 +1184,15 @@ AutoLaneBifurcationRetry: // Enable common clock for downstream
TargetAddress = CfgBase + PCIE_CAPABILITY_BASE + LINK_CONTROL_LINK_STATUS_REG;
- Val = MmioRead32 (TargetAddress);
- Val = CAP_SLOT_CLK_CONFIG_SET (Val, 1);
- Val = CAP_COMMON_CLK_SET (Val, 1);
+ Val = MmioRead32 (TargetAddress);
+ Val = CAP_SLOT_CLK_CONFIG_SET (Val, 1);
+ Val = CAP_COMMON_CLK_SET (Val, 1);
MmioWrite32 (TargetAddress, Val);
// Match aux_clk to system
TargetAddress = CfgBase + AUX_CLK_FREQ_OFF;
- Val = MmioRead32 (TargetAddress);
- Val = AUX_CLK_FREQ_SET (Val, AUX_CLK_500MHZ);
+ Val = MmioRead32 (TargetAddress);
+ Val = AUX_CLK_FREQ_SET (Val, AUX_CLK_500MHZ);
MmioWrite32 (TargetAddress, Val);
// Assert PERST low to reset endpoint
@@ -1193,7 +1205,7 @@ AutoLaneBifurcationRetry: StartLinkTraining (RootComplex, PcieIndex, TRUE);
// Lock programming of config space
- EnableDbiAccess (RootComplex, PcieIndex, FALSE);
+ EnableDbiAccess (RootComplex, PcieIndex, FALSE);
if (ReInit) {
return RETURN_SUCCESS;
@@ -1209,12 +1221,12 @@ AutoLaneBifurcationRetry: BOOLEAN
PcieLinkUpCheck (
- IN AC01_PCIE_CONTROLLER *Pcie
+ IN AC01_PCIE_CONTROLLER *Pcie
)
{
- PHYSICAL_ADDRESS CsrBase;
- UINT32 BlockEvent;
- UINT32 LinkStat;
+ PHYSICAL_ADDRESS CsrBase;
+ UINT32 BlockEvent;
+ UINT32 LinkStat;
CsrBase = Pcie->CsrBase;
@@ -1231,10 +1243,11 @@ PcieLinkUpCheck ( }
BlockEvent = MmioRead32 (CsrBase + AC01_PCIE_CORE_BLOCK_EVENT_STAT_REG);
- LinkStat = MmioRead32 (CsrBase + AC01_PCIE_CORE_LINK_STAT_REG);
+ LinkStat = MmioRead32 (CsrBase + AC01_PCIE_CORE_LINK_STAT_REG);
- if (((BlockEvent & LINKUP_MASK) != 0)
- && (SMLH_LTSSM_STATE_GET(LinkStat) == LTSSM_STATE_L0)) {
+ if ( ((BlockEvent & LINKUP_MASK) != 0)
+ && (SMLH_LTSSM_STATE_GET (LinkStat) == LTSSM_STATE_L0))
+ {
return TRUE;
}
@@ -1248,15 +1261,14 @@ PcieLinkUpCheck ( **/
VOID
Ac01PcieCoreEndEnumeration (
- IN AC01_ROOT_COMPLEX *RootComplex
+ IN AC01_ROOT_COMPLEX *RootComplex
)
{
+ PHYSICAL_ADDRESS TargetAddress;
+ UINT32 PcieIndex;
+ UINT32 Val;
- PHYSICAL_ADDRESS TargetAddress;
- UINT32 PcieIndex;
- UINT32 Val;
-
- if (RootComplex == NULL || !RootComplex->Active) {
+ if ((RootComplex == NULL) || !RootComplex->Active) {
return;
}
@@ -1266,7 +1278,7 @@ Ac01PcieCoreEndEnumeration ( continue;
}
- if (!PcieLinkUpCheck(&RootComplex->Pcie[PcieIndex])) {
+ if (!PcieLinkUpCheck (&RootComplex->Pcie[PcieIndex])) {
// If link down/disabled after enumeration, disable completed time out
DisableCompletionTimeOut (RootComplex, PcieIndex, TRUE);
}
@@ -1302,16 +1314,17 @@ Ac01PcieCoreLinkCheck ( IN UINT8 EpMaxGen
)
{
- PHYSICAL_ADDRESS CsrBase, CfgBase;
- UINT32 Val, LinkStat;
- UINT32 MaxWidth, MaxGen;
+ PHYSICAL_ADDRESS CsrBase, CfgBase;
+ UINT32 Val, LinkStat;
+ UINT32 MaxWidth, MaxGen;
CsrBase = RootComplex->Pcie[PcieIndex].CsrBase;
CfgBase = RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].DevNum << DEV_SHIFT);
Val = MmioRead32 (CfgBase + PCIE_CAPABILITY_BASE + LINK_CAPABILITIES_REG);
if ((CAP_MAX_LINK_WIDTH_GET (Val) == 0) ||
- (CAP_MAX_LINK_SPEED_GET (Val) == 0)) {
+ (CAP_MAX_LINK_SPEED_GET (Val) == 0))
+ {
DEBUG ((DEBUG_INFO, "\tPCIE%d.%d: Wrong RootComplex capabilities\n", RootComplex->ID, PcieIndex));
return LINK_CHECK_WRONG_PARAMETER;
}
@@ -1336,7 +1349,7 @@ Ac01PcieCoreLinkCheck ( }
LinkStat = MmioRead32 (CsrBase + AC01_PCIE_CORE_LINK_STAT_REG);
- Val = MmioRead32 (CfgBase + PCIE_CAPABILITY_BASE + LINK_CONTROL_LINK_STATUS_REG);
+ Val = MmioRead32 (CfgBase + PCIE_CAPABILITY_BASE + LINK_CONTROL_LINK_STATUS_REG);
DEBUG ((
DEBUG_INFO,
"PCIE%d.%d: Link MaxWidth %d MaxGen %d, AC01_PCIE_CORE_LINK_STAT_REG 0x%x",
@@ -1363,21 +1376,21 @@ Ac01PcieCoreLinkCheck ( INT32
PFACounterRead (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN UINT8 PcieIndex,
- IN UINT64 RasDesCapabilityBase
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN UINT8 PcieIndex,
+ IN UINT64 RasDesCapabilityBase
)
{
- INT32 Ret = LINK_CHECK_SUCCESS;
- UINT32 Val;
- UINT8 ErrCode, ErrGrpNum;
+ INT32 Ret = LINK_CHECK_SUCCESS;
+ UINT32 Val;
+ UINT8 ErrCode, ErrGrpNum;
- UINT32 ErrCtrlCfg[] = {
+ UINT32 ErrCtrlCfg[] = {
0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007, 0x008, 0x009, 0x00A, // Per Lane
0x105, 0x106, 0x107, 0x108, 0x109, 0x10A,
0x200, 0x201, 0x202, 0x203, 0x204, 0x205, 0x206, 0x207,
0x300, 0x301, 0x302, 0x303, 0x304, 0x305,
- 0x400, 0x401, // Per Lane
+ 0x400, 0x401, // Per Lane
0x500, 0x501, 0x502, 0x503, 0x504, 0x505, 0x506, 0x507, 0x508, 0x509, 0x50A, 0x50B, 0x50C, 0x50D
};
@@ -1394,6 +1407,7 @@ PFACounterRead ( // RootComplexTypeB - 8 PCIe controller per port, 1 controller in charge of 2 lanes
Val = ECCR_LANE_SEL_SET (Val, PcieIndex * 2);
}
+
Val = ECCR_GROUP_EVENT_SEL_SET (Val, ErrCtrlCfg[ErrCode]);
MmioWrite32 (RasDesCapabilityBase + EVENT_COUNTER_CONTROL_REG, Val);
@@ -1431,15 +1445,15 @@ PFACounterRead ( **/
INT32
Ac01PFACommand (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN UINT8 PcieIndex,
- IN UINT8 PFAMode
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN UINT8 PcieIndex,
+ IN UINT8 PFAMode
)
{
- PHYSICAL_ADDRESS RasDesCapabilityBase;
- PHYSICAL_ADDRESS TargetAddress;
- INT32 Ret = LINK_CHECK_SUCCESS;
- UINT32 Val;
+ PHYSICAL_ADDRESS RasDesCapabilityBase;
+ PHYSICAL_ADDRESS TargetAddress;
+ INT32 Ret = LINK_CHECK_SUCCESS;
+ UINT32 Val;
// Allow programming to config space
EnableDbiAccess (RootComplex, PcieIndex, TRUE);
@@ -1454,26 +1468,26 @@ Ac01PFACommand ( TargetAddress = RasDesCapabilityBase + EVENT_COUNTER_CONTROL_REG;
switch (PFAMode) {
- case PFA_MODE_ENABLE:
- Val = MmioRead32 (TargetAddress);
- Val = ECCR_EVENT_COUNTER_ENABLE_SET (Val, EVENT_COUNTER_ENABLE_ALL_ON);
- Val = ECCR_EVENT_COUNTER_CLEAR_SET (Val, EVENT_COUNTER_CLEAR_NO_CHANGE);
- MmioWrite32 (TargetAddress, Val);
- break;
+ case PFA_MODE_ENABLE:
+ Val = MmioRead32 (TargetAddress);
+ Val = ECCR_EVENT_COUNTER_ENABLE_SET (Val, EVENT_COUNTER_ENABLE_ALL_ON);
+ Val = ECCR_EVENT_COUNTER_CLEAR_SET (Val, EVENT_COUNTER_CLEAR_NO_CHANGE);
+ MmioWrite32 (TargetAddress, Val);
+ break;
- case PFA_MODE_CLEAR:
- Val = MmioRead32 (TargetAddress);
- Val = ECCR_EVENT_COUNTER_ENABLE_SET (Val, EVENT_COUNTER_ENABLE_NO_CHANGE);
- Val = ECCR_EVENT_COUNTER_CLEAR_SET (Val, EVENT_COUNTER_CLEAR_ALL_CLEAR);
- MmioWrite32 (TargetAddress, Val);
- break;
+ case PFA_MODE_CLEAR:
+ Val = MmioRead32 (TargetAddress);
+ Val = ECCR_EVENT_COUNTER_ENABLE_SET (Val, EVENT_COUNTER_ENABLE_NO_CHANGE);
+ Val = ECCR_EVENT_COUNTER_CLEAR_SET (Val, EVENT_COUNTER_CLEAR_ALL_CLEAR);
+ MmioWrite32 (TargetAddress, Val);
+ break;
- case PFA_MODE_READ:
- Ret = PFACounterRead (RootComplex, PcieIndex, RasDesCapabilityBase);
- break;
+ case PFA_MODE_READ:
+ Ret = PFACounterRead (RootComplex, PcieIndex, RasDesCapabilityBase);
+ break;
- default:
- DEBUG ((DEBUG_ERROR, "%a: Invalid PFA mode\n"));
+ default:
+ DEBUG ((DEBUG_ERROR, "%a: Invalid PFA mode\n"));
}
// Disable programming to config space
@@ -1484,13 +1498,13 @@ Ac01PFACommand ( BOOLEAN
EndpointCfgReady (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN UINT8 PcieIndex,
- IN UINT32 TimeOut
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN UINT8 PcieIndex,
+ IN UINT32 TimeOut
)
{
- PHYSICAL_ADDRESS CfgBase;
- UINT32 Val;
+ PHYSICAL_ADDRESS CfgBase;
+ UINT32 Val;
CfgBase = RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].DevNum << BUS_SHIFT);
@@ -1498,7 +1512,7 @@ EndpointCfgReady ( // reach to Timeout (or more depend on card)
do {
Val = MmioRead32 (CfgBase);
- if (Val != 0xFFFF0001 && Val != 0xFFFFFFFF) {
+ if ((Val != 0xFFFF0001) && (Val != 0xFFFFFFFF)) {
return TRUE;
}
@@ -1525,28 +1539,28 @@ Ac01PcieCoreGetEndpointInfo ( OUT UINT8 *EpMaxGen
)
{
- PHYSICAL_ADDRESS CfgBase;
- PHYSICAL_ADDRESS EpCfgAddr;
- PHYSICAL_ADDRESS PcieCapBase;
- PHYSICAL_ADDRESS SecLatTimerAddr;
- PHYSICAL_ADDRESS TargetAddress;
- UINT32 RestoreVal;
- UINT32 Val;
+ PHYSICAL_ADDRESS CfgBase;
+ PHYSICAL_ADDRESS EpCfgAddr;
+ PHYSICAL_ADDRESS PcieCapBase;
+ PHYSICAL_ADDRESS SecLatTimerAddr;
+ PHYSICAL_ADDRESS TargetAddress;
+ UINT32 RestoreVal;
+ UINT32 Val;
- CfgBase = RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].DevNum << DEV_SHIFT);
- SecLatTimerAddr = CfgBase + SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG;
+ CfgBase = RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].DevNum << DEV_SHIFT);
+ SecLatTimerAddr = CfgBase + SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG;
*EpMaxWidth = 0;
- *EpMaxGen = 0;
+ *EpMaxGen = 0;
// Allow programming to config space
EnableDbiAccess (RootComplex, PcieIndex, TRUE);
- Val = MmioRead32 (SecLatTimerAddr);
+ Val = MmioRead32 (SecLatTimerAddr);
RestoreVal = Val;
- Val = SUB_BUS_SET (Val, DEFAULT_SUB_BUS);
- Val = SEC_BUS_SET (Val, RootComplex->Pcie[PcieIndex].DevNum);
- Val = PRIM_BUS_SET (Val, DEFAULT_PRIM_BUS);
+ Val = SUB_BUS_SET (Val, DEFAULT_SUB_BUS);
+ Val = SEC_BUS_SET (Val, RootComplex->Pcie[PcieIndex].DevNum);
+ Val = PRIM_BUS_SET (Val, DEFAULT_PRIM_BUS);
MmioWrite32 (SecLatTimerAddr, Val);
EpCfgAddr = RootComplex->MmcfgBase + (RootComplex->Pcie[PcieIndex].DevNum << BUS_SHIFT);
@@ -1574,12 +1588,13 @@ Ac01PcieCoreGetEndpointInfo ( PcieIndex
));
} else {
- Val = MmioRead32 (PcieCapBase + LINK_CAPABILITIES_REG);
+ Val = MmioRead32 (PcieCapBase + LINK_CAPABILITIES_REG);
*EpMaxWidth = CAP_MAX_LINK_WIDTH_GET (Val);
- *EpMaxGen = CAP_MAX_LINK_SPEED_GET (Val);
+ *EpMaxGen = CAP_MAX_LINK_SPEED_GET (Val);
DEBUG ((
DEBUG_INFO,
- "PCIE%d.%d EP MaxWidth %d EP MaxGen %d \n", RootComplex->ID,
+ "PCIE%d.%d EP MaxWidth %d EP MaxGen %d \n",
+ RootComplex->ID,
PcieIndex,
*EpMaxWidth,
*EpMaxGen
@@ -1587,9 +1602,9 @@ Ac01PcieCoreGetEndpointInfo ( // From EP, enabling common clock for upstream
TargetAddress = PcieCapBase + LINK_CONTROL_LINK_STATUS_REG;
- Val = MmioRead32 (TargetAddress);
- Val = CAP_SLOT_CLK_CONFIG_SET (Val, 1);
- Val = CAP_COMMON_CLK_SET (Val, 1);
+ Val = MmioRead32 (TargetAddress);
+ Val = CAP_SLOT_CLK_CONFIG_SET (Val, 1);
+ Val = CAP_COMMON_CLK_SET (Val, 1);
MmioWrite32 (TargetAddress, Val);
}
}
@@ -1604,11 +1619,11 @@ Exit: VOID
PollLinkUp (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN UINT8 PcieIndex
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN UINT8 PcieIndex
)
{
- UINT32 TimeOut;
+ UINT32 TimeOut;
// Poll until link up
// This checking for linkup status and
@@ -1652,13 +1667,13 @@ PollLinkUp ( **/
INT32
Ac01PcieCoreQoSLinkCheckRecovery (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN UINT8 PcieIndex
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN UINT8 PcieIndex
)
{
- INT32 LinkStatusCheck, RasdesChecking;
- INT32 NumberOfReset = MAX_REINIT;
- UINT8 EpMaxWidth, EpMaxGen;
+ INT32 LinkStatusCheck, RasdesChecking;
+ INT32 NumberOfReset = MAX_REINIT;
+ UINT8 EpMaxWidth, EpMaxGen;
// PCIe controller is not active or Link is not up
// Nothing to be done
@@ -1689,8 +1704,8 @@ Ac01PcieCoreQoSLinkCheckRecovery ( // If link check functions return passed, then breaking out
// else go to soft reset
- if (LinkStatusCheck != LINK_CHECK_FAILED &&
- RasdesChecking != LINK_CHECK_FAILED &&
+ if ((LinkStatusCheck != LINK_CHECK_FAILED) &&
+ (RasdesChecking != LINK_CHECK_FAILED) &&
PcieLinkUpCheck (&RootComplex->Pcie[PcieIndex]))
{
return LINK_CHECK_SUCCESS;
@@ -1713,7 +1728,7 @@ Ac01PcieCoreQoSLinkCheckRecovery ( BOOLEAN
Ac01PcieCoreCheckCardPresent (
- IN AC01_PCIE_CONTROLLER *PcieController
+ IN AC01_PCIE_CONTROLLER *PcieController
)
{
EFI_PHYSICAL_ADDRESS TargetAddress;
@@ -1737,15 +1752,15 @@ Ac01PcieCoreCheckCardPresent ( VOID
Ac01PcieCoreUpdateLink (
- IN AC01_ROOT_COMPLEX *RootComplex,
- OUT BOOLEAN *IsNextRoundNeeded,
- OUT INT8 *FailedPciePtr,
- OUT INT8 *FailedPcieCount
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ OUT BOOLEAN *IsNextRoundNeeded,
+ OUT INT8 *FailedPciePtr,
+ OUT INT8 *FailedPcieCount
)
{
- AC01_PCIE_CONTROLLER *Pcie;
- UINT8 PcieIndex;
- UINT32 Index;
+ AC01_PCIE_CONTROLLER *Pcie;
+ UINT8 PcieIndex;
+ UINT32 Index;
*IsNextRoundNeeded = FALSE;
*FailedPcieCount = 0;
@@ -1770,10 +1785,9 @@ Ac01PcieCoreUpdateLink ( // Un-mask Completion Timeout
DisableCompletionTimeOut (RootComplex, PcieIndex, FALSE);
-
} else {
FailedPciePtr[*FailedPcieCount] = PcieIndex;
- *FailedPcieCount += 1;
+ *FailedPcieCount += 1;
if (Ac01PcieCoreCheckCardPresent (Pcie)) {
*IsNextRoundNeeded = TRUE;
@@ -1791,16 +1805,16 @@ Ac01PcieCoreUpdateLink ( **/
VOID
Ac01PcieCorePostSetupRC (
- IN AC01_ROOT_COMPLEX *RootComplexList
+ IN AC01_ROOT_COMPLEX *RootComplexList
)
{
- UINT8 RCIndex, Idx;
- BOOLEAN IsNextRoundNeeded, NextRoundNeeded;
- UINT64 PrevTick, CurrTick, ElapsedCycle;
- UINT64 TimerTicks64;
- UINT8 ReInit;
- INT8 FailedPciePtr[MaxPcieControllerOfRootComplexB];
- INT8 FailedPcieCount;
+ UINT8 RCIndex, Idx;
+ BOOLEAN IsNextRoundNeeded, NextRoundNeeded;
+ UINT64 PrevTick, CurrTick, ElapsedCycle;
+ UINT64 TimerTicks64;
+ UINT8 ReInit;
+ INT8 FailedPciePtr[MaxPcieControllerOfRootComplexB];
+ INT8 FailedPcieCount;
ReInit = 0;
@@ -1811,17 +1825,18 @@ _link_polling: // Calculate system ticks for link training.
//
TimerTicks64 = ArmGenericTimerGetTimerFreq (); /* 1 Second */
- PrevTick = ArmGenericTimerGetSystemCount ();
+ PrevTick = ArmGenericTimerGetSystemCount ();
ElapsedCycle = 0;
do {
CurrTick = ArmGenericTimerGetSystemCount ();
if (CurrTick < PrevTick) {
ElapsedCycle += MAX_UINT64 - PrevTick;
- PrevTick = 0;
+ PrevTick = 0;
}
+
ElapsedCycle += (CurrTick - PrevTick);
- PrevTick = CurrTick;
+ PrevTick = CurrTick;
} while (ElapsedCycle < TimerTicks64);
for (RCIndex = 0; RCIndex < AC01_PCIE_MAX_ROOT_COMPLEX; RCIndex++) {
@@ -1831,7 +1846,7 @@ _link_polling: }
}
- if (NextRoundNeeded && ReInit < MAX_REINIT) {
+ if (NextRoundNeeded && (ReInit < MAX_REINIT)) {
//
// Timer is up. Give another chance to re-program controller
//
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h index 988450a542..bd56e82c31 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h +++ b/Silicon/Ampere/AmpereAltraPkg/Library/Ac01PcieLib/PcieCore.h @@ -9,115 +9,115 @@ #ifndef AC01_PCIE_CORE_H_
#define AC01_PCIE_CORE_H_
-#define BUS_SHIFT 20
-#define DEV_SHIFT 15
+#define BUS_SHIFT 20
+#define DEV_SHIFT 15
-#define GET_LOW_8_BITS(x) ((x) & 0xFF)
-#define GET_HIGH_8_BITS(x) (((x) >> 8) & 0xFF)
-#define GET_LOW_16_BITS(x) ((x) & 0xFFFF)
-#define GET_HIGH_16_BITS(x) (((x) >> 16) & 0xFFFF)
-#define GET_CAPABILITY_PTR(x) (GET_LOW_16_BITS (x) >> 8)
-#define GET_EXT_CAPABILITY_PTR(x) (GET_HIGH_16_BITS (x) >> 4)
+#define GET_LOW_8_BITS(x) ((x) & 0xFF)
+#define GET_HIGH_8_BITS(x) (((x) >> 8) & 0xFF)
+#define GET_LOW_16_BITS(x) ((x) & 0xFFFF)
+#define GET_HIGH_16_BITS(x) (((x) >> 16) & 0xFFFF)
+#define GET_CAPABILITY_PTR(x) (GET_LOW_16_BITS (x) >> 8)
+#define GET_EXT_CAPABILITY_PTR(x) (GET_HIGH_16_BITS (x) >> 4)
-#define WORD_ALIGN_MASK 0x3
+#define WORD_ALIGN_MASK 0x3
-#define MAX_REINIT 3 // Number of soft reset retry
+#define MAX_REINIT 3 // Number of soft reset retry
-#define SLOT_POWER_LIMIT_75W 75 // Watt
+#define SLOT_POWER_LIMIT_75W 75 // Watt
-#define LINK_CHECK_SUCCESS 0
-#define LINK_CHECK_FAILED -1
-#define LINK_CHECK_WRONG_PARAMETER 1
+#define LINK_CHECK_SUCCESS 0
+#define LINK_CHECK_FAILED -1
+#define LINK_CHECK_WRONG_PARAMETER 1
-#define AMPERE_PCIE_VENDOR_ID 0x1DEF
-#define AC01_HOST_BRIDGE_DEVICE_ID_RCA 0xE100
-#define AC01_HOST_BRIDGE_DEVICE_ID_RCB 0xE110
-#define AC01_PCIE_BRIDGE_DEVICE_ID_RCA 0xE101
-#define AC01_PCIE_BRIDGE_DEVICE_ID_RCB 0xE111
+#define AMPERE_PCIE_VENDOR_ID 0x1DEF
+#define AC01_HOST_BRIDGE_DEVICE_ID_RCA 0xE100
+#define AC01_HOST_BRIDGE_DEVICE_ID_RCB 0xE110
+#define AC01_PCIE_BRIDGE_DEVICE_ID_RCA 0xE101
+#define AC01_PCIE_BRIDGE_DEVICE_ID_RCB 0xE111
-#define MEMRDY_TIMEOUT 10 // 10 us
-#define PIPE_CLOCK_TIMEOUT 20000 // 20,000 us
-#define LTSSM_TRANSITION_TIMEOUT 100000 // 100 ms in total
-#define EP_LINKUP_TIMEOUT (10 * 1000) // 10ms
-#define EP_LINKUP_EXTRA_TIMEOUT (500 * 1000) // 500ms
-#define LINK_WAIT_INTERVAL_US 50
+#define MEMRDY_TIMEOUT 10 // 10 us
+#define PIPE_CLOCK_TIMEOUT 20000 // 20,000 us
+#define LTSSM_TRANSITION_TIMEOUT 100000 // 100 ms in total
+#define EP_LINKUP_TIMEOUT (10 * 1000) // 10ms
+#define EP_LINKUP_EXTRA_TIMEOUT (500 * 1000) // 500ms
+#define LINK_WAIT_INTERVAL_US 50
-#define PFA_MODE_ENABLE 0
-#define PFA_MODE_CLEAR 1
-#define PFA_MODE_READ 2
+#define PFA_MODE_ENABLE 0
+#define PFA_MODE_CLEAR 1
+#define PFA_MODE_READ 2
-#define BIFURCATION_X000 0
-#define BIFURCATION_X0X0 1
-#define BIFURCATION_X0XX 2
-#define BIFURCATION_XXXX 3
+#define BIFURCATION_X000 0
+#define BIFURCATION_X0X0 1
+#define BIFURCATION_X0XX 2
+#define BIFURCATION_XXXX 3
//
// Host Bridge registers
//
-#define AC01_HOST_BRIDGE_RCA_DEV_MAP_REG 0x0
-#define AC01_HOST_BRIDGE_RCB_DEV_MAP_REG 0x4
-#define AC01_HOST_BRIDGE_VENDOR_DEVICE_ID_REG 0x10
+#define AC01_HOST_BRIDGE_RCA_DEV_MAP_REG 0x0
+#define AC01_HOST_BRIDGE_RCB_DEV_MAP_REG 0x4
+#define AC01_HOST_BRIDGE_VENDOR_DEVICE_ID_REG 0x10
// AC01_HOST_BRIDGE_RCA_DEV_MAP_REG
-#define RCA_DEV_MAP_SET(dst, src) (((dst) & ~0x7) | (((UINT32) (src)) & 0x7))
-#define RCA_DEV_MAP_GET(val) ((val) & 0x7)
+#define RCA_DEV_MAP_SET(dst, src) (((dst) & ~0x7) | (((UINT32) (src)) & 0x7))
+#define RCA_DEV_MAP_GET(val) ((val) & 0x7)
// AC01_HOST_BRIDGE_RCB_DEV_MAP_REG
-#define RCB_DEV_MAP_LOW_SET(dst, src) (((dst) & ~0x7) | (((UINT32) (src)) & 0x7))
-#define RCB_DEV_MAP_LOW_GET(val) ((val) & 0x7)
+#define RCB_DEV_MAP_LOW_SET(dst, src) (((dst) & ~0x7) | (((UINT32) (src)) & 0x7))
+#define RCB_DEV_MAP_LOW_GET(val) ((val) & 0x7)
-#define RCB_DEV_MAP_HIGH_SET(dst, src) (((dst) & ~0x70) | (((UINT32) (src) << 4) & 0x70))
-#define RCB_DEV_MAP_HIGH_GET(val) (((val) & 0x7) >> 4)
+#define RCB_DEV_MAP_HIGH_SET(dst, src) (((dst) & ~0x70) | (((UINT32) (src) << 4) & 0x70))
+#define RCB_DEV_MAP_HIGH_GET(val) (((val) & 0x7) >> 4)
// AC01_HOST_BRIDGE_VENDOR_DEVICE_ID_REG
-#define VENDOR_ID_SET(dst, src) (((dst) & ~0xFFFF) | (((UINT32) (src)) & 0xFFFF))
-#define VENDOR_ID_GET(val) ((val) & 0xFFFF)
+#define VENDOR_ID_SET(dst, src) (((dst) & ~0xFFFF) | (((UINT32) (src)) & 0xFFFF))
+#define VENDOR_ID_GET(val) ((val) & 0xFFFF)
-#define DEVICE_ID_SET(dst, src) (((dst) & ~0xFFFF0000) | (((UINT32) (src) << 16) & 0xFFFF0000))
-#define DEVICE_ID_GET(val) (((val) & 0xFFFF0000) >> 16)
+#define DEVICE_ID_SET(dst, src) (((dst) & ~0xFFFF0000) | (((UINT32) (src) << 16) & 0xFFFF0000))
+#define DEVICE_ID_GET(val) (((val) & 0xFFFF0000) >> 16)
//
// PCIe core registers
//
-#define AC01_PCIE_CORE_LINK_CTRL_REG 0x0
-#define AC01_PCIE_CORE_LINK_STAT_REG 0x4
-#define AC01_PCIE_CORE_IRQ_SEL_REG 0xC
-#define AC01_PCIE_CORE_HOT_PLUG_STAT_REG 0x28
-#define AC01_PCIE_CORE_IRQ_ENABLE_REG 0x30
-#define AC01_PCIE_CORE_IRQ_EVENT_STAT_REG 0x38
-#define AC01_PCIE_CORE_BLOCK_EVENT_STAT_REG 0x3C
-#define AC01_PCIE_CORE_BUS_CONTROL_REG 0x40
-#define AC01_PCIE_CORE_RESET_REG 0xC000
-#define AC01_PCIE_CORE_CLOCK_REG 0xC004
-#define AC01_PCIE_CORE_MEM_READY_REG 0xC104
-#define AC01_PCIE_CORE_RAM_SHUTDOWN_REG 0xC10C
+#define AC01_PCIE_CORE_LINK_CTRL_REG 0x0
+#define AC01_PCIE_CORE_LINK_STAT_REG 0x4
+#define AC01_PCIE_CORE_IRQ_SEL_REG 0xC
+#define AC01_PCIE_CORE_HOT_PLUG_STAT_REG 0x28
+#define AC01_PCIE_CORE_IRQ_ENABLE_REG 0x30
+#define AC01_PCIE_CORE_IRQ_EVENT_STAT_REG 0x38
+#define AC01_PCIE_CORE_BLOCK_EVENT_STAT_REG 0x3C
+#define AC01_PCIE_CORE_BUS_CONTROL_REG 0x40
+#define AC01_PCIE_CORE_RESET_REG 0xC000
+#define AC01_PCIE_CORE_CLOCK_REG 0xC004
+#define AC01_PCIE_CORE_MEM_READY_REG 0xC104
+#define AC01_PCIE_CORE_RAM_SHUTDOWN_REG 0xC10C
// AC01_PCIE_CORE_LINK_CTRL_REG
-#define LTSSMENB_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
-#define LTSSMENB_GET(dst) ((dst) & (BIT0))
-#define HOLD_LINK_TRAINING 0
-#define START_LINK_TRAINING 1
-#define DEVICETYPE_SET(dst, src) (((dst) & ~0xF0) | (((UINT32) (src) << 4) & 0xF0))
-#define DEVICETYPE_GET(val) (((val) & 0xF0) >> 4)
+#define LTSSMENB_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
+#define LTSSMENB_GET(dst) ((dst) & (BIT0))
+#define HOLD_LINK_TRAINING 0
+#define START_LINK_TRAINING 1
+#define DEVICETYPE_SET(dst, src) (((dst) & ~0xF0) | (((UINT32) (src) << 4) & 0xF0))
+#define DEVICETYPE_GET(val) (((val) & 0xF0) >> 4)
// AC01_PCIE_CORE_LINK_STAT_REG
-#define PHY_STATUS_MASK (1 << 2)
-#define SMLH_LTSSM_STATE_MASK 0x3F00
-#define SMLH_LTSSM_STATE_GET(val) ((val & SMLH_LTSSM_STATE_MASK) >> 8)
-#define LTSSM_STATE_L0 0x11
-#define RDLH_SMLH_LINKUP_STATUS_GET(val) (val & 0x3)
-#define PHY_STATUS_MASK_BIT 0x04
-#define SMLH_LINK_UP_MASK_BIT 0x02
-#define RDLH_LINK_UP_MASK_BIT 0x01
+#define PHY_STATUS_MASK (1 << 2)
+#define SMLH_LTSSM_STATE_MASK 0x3F00
+#define SMLH_LTSSM_STATE_GET(val) ((val & SMLH_LTSSM_STATE_MASK) >> 8)
+#define LTSSM_STATE_L0 0x11
+#define RDLH_SMLH_LINKUP_STATUS_GET(val) (val & 0x3)
+#define PHY_STATUS_MASK_BIT 0x04
+#define SMLH_LINK_UP_MASK_BIT 0x02
+#define RDLH_LINK_UP_MASK_BIT 0x01
// AC01_PCIE_CORE_IRQ_SEL_REG
-#define AER_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
-#define PME_SET(dst, src) (((dst) & ~0x2) | (((UINT32) (src) << 1) & 0x2))
-#define LINKAUTOBW_SET(dst, src) (((dst) & ~0x4) | (((UINT32) (src) << 2) & 0x4))
-#define BWMGMT_SET(dst, src) (((dst) & ~0x8) | (((UINT32) (src) << 3) & 0x8))
-#define EQRQST_SET(dst, src) (((dst) & ~0x10) | (((UINT32) (src) << 4) & 0x10))
-#define INTPIN_SET(dst, src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
-#define IRQ_INT_A 0x01
+#define AER_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
+#define PME_SET(dst, src) (((dst) & ~0x2) | (((UINT32) (src) << 1) & 0x2))
+#define LINKAUTOBW_SET(dst, src) (((dst) & ~0x4) | (((UINT32) (src) << 2) & 0x4))
+#define BWMGMT_SET(dst, src) (((dst) & ~0x8) | (((UINT32) (src) << 3) & 0x8))
+#define EQRQST_SET(dst, src) (((dst) & ~0x10) | (((UINT32) (src) << 4) & 0x10))
+#define INTPIN_SET(dst, src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
+#define IRQ_INT_A 0x01
// AC01_PCIE_CORE_HOT_PLUG_STAT_REG
#define PWR_IND_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
@@ -126,207 +126,207 @@ #define EML_CTRL_SET(dst, src) (((dst) & ~0x8) | (((UINT32) (src) << 3) & 0x8))
// AC01_PCIE_CORE_BLOCK_EVENT_STAT_REG
-#define LINKUP_MASK 0x1
+#define LINKUP_MASK 0x1
// AC01_PCIE_CORE_BUS_CONTROL_REG
-#define BUS_CTL_CFG_UR_MASK 0x8
+#define BUS_CTL_CFG_UR_MASK 0x8
// AC01_PCIE_CORE_RESET_REG
-#define DWC_PCIE_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
-#define RESET_MASK 0x1
-#define ASSERT_RESET 0x1
+#define DWC_PCIE_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
+#define RESET_MASK 0x1
+#define ASSERT_RESET 0x1
// AC01_PCIE_CORE_CLOCK_REG
-#define AXIPIPE_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
+#define AXIPIPE_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
// AC01_PCIE_CORE_MEM_READY_REG
-#define MEMORY_READY 0x1
+#define MEMORY_READY 0x1
// AC01_PCIE_CORE_RAM_SHUTDOWN_REG
-#define SD_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
+#define SD_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
//
// AC01 PCIe Type 1 configuration registers
//
-#define TYPE1_DEV_ID_VEND_ID_REG 0
-#define TYPE1_CLASS_CODE_REV_ID_REG 0x8
-#define TYPE1_CAP_PTR_REG 0x34
-#define SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG 0x18
-#define BRIDGE_CTRL_INT_PIN_INT_LINE_REG 0x3C
-#define PCIE_CAPABILITY_BASE 0x70
-#define EXT_CAPABILITY_START_BASE 0x100
-#define AER_CAPABILITY_BASE 0x100
+#define TYPE1_DEV_ID_VEND_ID_REG 0
+#define TYPE1_CLASS_CODE_REV_ID_REG 0x8
+#define TYPE1_CAP_PTR_REG 0x34
+#define SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG 0x18
+#define BRIDGE_CTRL_INT_PIN_INT_LINE_REG 0x3C
+#define PCIE_CAPABILITY_BASE 0x70
+#define EXT_CAPABILITY_START_BASE 0x100
+#define AER_CAPABILITY_BASE 0x100
// TYPE1_DEV_ID_VEND_ID_REG
-#define VENDOR_ID_SET(dst, src) (((dst) & ~0xFFFF) | (((UINT32) (src)) & 0xFFFF))
-#define DEVICE_ID_SET(dst, src) (((dst) & ~0xFFFF0000) | (((UINT32) (src) << 16) & 0xFFFF0000))
+#define VENDOR_ID_SET(dst, src) (((dst) & ~0xFFFF) | (((UINT32) (src)) & 0xFFFF))
+#define DEVICE_ID_SET(dst, src) (((dst) & ~0xFFFF0000) | (((UINT32) (src) << 16) & 0xFFFF0000))
// TYPE1_CLASS_CODE_REV_ID_REG
-#define BASE_CLASS_CODE_SET(dst, src) (((dst) & ~0xFF000000) | (((UINT32) (src) << 24) & 0xFF000000))
-#define DEFAULT_BASE_CLASS_CODE 6
-#define SUB_CLASS_CODE_SET(dst, src) (((dst) & ~0xFF0000) | (((UINT32) (src) << 16) & 0xFF0000))
-#define DEFAULT_SUB_CLASS_CODE 4
-#define PROGRAM_INTERFACE_SET(dst, src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
-#define REVISION_ID_SET(dst, src) (((dst) & ~0xFF) | (((UINT32) (src)) & 0xFF))
-#define DEFAULT_REVISION_ID 4
+#define BASE_CLASS_CODE_SET(dst, src) (((dst) & ~0xFF000000) | (((UINT32) (src) << 24) & 0xFF000000))
+#define DEFAULT_BASE_CLASS_CODE 6
+#define SUB_CLASS_CODE_SET(dst, src) (((dst) & ~0xFF0000) | (((UINT32) (src) << 16) & 0xFF0000))
+#define DEFAULT_SUB_CLASS_CODE 4
+#define PROGRAM_INTERFACE_SET(dst, src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
+#define REVISION_ID_SET(dst, src) (((dst) & ~0xFF) | (((UINT32) (src)) & 0xFF))
+#define DEFAULT_REVISION_ID 4
// SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG
-#define SUB_BUS_SET(dst, src) (((dst) & ~0xFF0000) | (((UINT32) (src) << 16) & 0xFF0000))
-#define DEFAULT_SUB_BUS 0xFF
-#define SEC_BUS_SET(dst, src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
-#define PRIM_BUS_SET(dst, src) (((dst) & ~0xFF) | (((UINT32) (src)) & 0xFF))
-#define DEFAULT_PRIM_BUS 0x00
+#define SUB_BUS_SET(dst, src) (((dst) & ~0xFF0000) | (((UINT32) (src) << 16) & 0xFF0000))
+#define DEFAULT_SUB_BUS 0xFF
+#define SEC_BUS_SET(dst, src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
+#define PRIM_BUS_SET(dst, src) (((dst) & ~0xFF) | (((UINT32) (src)) & 0xFF))
+#define DEFAULT_PRIM_BUS 0x00
// BRIDGE_CTRL_INT_PIN_INT_LINE_REG
-#define INT_PIN_SET(dst, src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
+#define INT_PIN_SET(dst, src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
//
// PCI Express Capability
//
-#define PCIE_CAPABILITY_ID 0x10
-#define LINK_CAPABILITIES_REG 0xC
-#define LINK_CONTROL_LINK_STATUS_REG 0x10
-#define SLOT_CAPABILITIES_REG 0x14
-#define DEVICE_CONTROL2_DEVICE_STATUS2_REG 0x28
-#define LINK_CAPABILITIES2_REG 0x2C
-#define LINK_CONTROL2_LINK_STATUS2_REG 0x30
+#define PCIE_CAPABILITY_ID 0x10
+#define LINK_CAPABILITIES_REG 0xC
+#define LINK_CONTROL_LINK_STATUS_REG 0x10
+#define SLOT_CAPABILITIES_REG 0x14
+#define DEVICE_CONTROL2_DEVICE_STATUS2_REG 0x28
+#define LINK_CAPABILITIES2_REG 0x2C
+#define LINK_CONTROL2_LINK_STATUS2_REG 0x30
// LINK_CAPABILITIES_REG
-#define CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SET(dst, src) (((dst) & ~0xC00) | (((UINT32)(src) << 10) & 0xC00))
-#define NO_ASPM_SUPPORTED 0x0
-#define L0S_SUPPORTED 0x1
-#define L1_SUPPORTED 0x2
-#define L0S_L1_SUPPORTED 0x3
-#define CAP_MAX_LINK_WIDTH_GET(val) ((val & 0x3F0) >> 4)
-#define CAP_MAX_LINK_WIDTH_SET(dst, src) (((dst) & ~0x3F0) | (((UINT32) (src) << 4) & 0x3F0))
-#define CAP_MAX_LINK_WIDTH_X1 0x1
-#define CAP_MAX_LINK_WIDTH_X2 0x2
-#define CAP_MAX_LINK_WIDTH_X4 0x4
-#define CAP_MAX_LINK_WIDTH_X8 0x8
-#define CAP_MAX_LINK_WIDTH_X16 0x10
-#define CAP_MAX_LINK_SPEED_GET(val) ((val & 0xF))
-#define CAP_MAX_LINK_SPEED_SET(dst, src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
-#define MAX_LINK_SPEED_25 0x1
-#define MAX_LINK_SPEED_50 0x2
-#define MAX_LINK_SPEED_80 0x3
-#define MAX_LINK_SPEED_160 0x4
-#define MAX_LINK_SPEED_320 0x5
+#define CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SET(dst, src) (((dst) & ~0xC00) | (((UINT32)(src) << 10) & 0xC00))
+#define NO_ASPM_SUPPORTED 0x0
+#define L0S_SUPPORTED 0x1
+#define L1_SUPPORTED 0x2
+#define L0S_L1_SUPPORTED 0x3
+#define CAP_MAX_LINK_WIDTH_GET(val) ((val & 0x3F0) >> 4)
+#define CAP_MAX_LINK_WIDTH_SET(dst, src) (((dst) & ~0x3F0) | (((UINT32) (src) << 4) & 0x3F0))
+#define CAP_MAX_LINK_WIDTH_X1 0x1
+#define CAP_MAX_LINK_WIDTH_X2 0x2
+#define CAP_MAX_LINK_WIDTH_X4 0x4
+#define CAP_MAX_LINK_WIDTH_X8 0x8
+#define CAP_MAX_LINK_WIDTH_X16 0x10
+#define CAP_MAX_LINK_SPEED_GET(val) ((val & 0xF))
+#define CAP_MAX_LINK_SPEED_SET(dst, src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
+#define MAX_LINK_SPEED_25 0x1
+#define MAX_LINK_SPEED_50 0x2
+#define MAX_LINK_SPEED_80 0x3
+#define MAX_LINK_SPEED_160 0x4
+#define MAX_LINK_SPEED_320 0x5
// LINK_CONTROL_LINK_STATUS_REG
-#define CAP_DLL_ACTIVE_GET(val) ((val & 0x20000000) >> 29)
-#define CAP_SLOT_CLK_CONFIG_SET(dst, src) (((dst) & ~0x10000000) | (((UINT32) (src) << 28) & 0x10000000))
-#define CAP_NEGO_LINK_WIDTH_GET(val) ((val & 0x3F00000) >> 20)
-#define CAP_LINK_SPEED_GET(val) ((val & 0xF0000) >> 16)
-#define CAP_LINK_SPEED_SET(dst, src) (((dst) & ~0xF0000) | (((UINT32) (src) << 16) & 0xF0000))
-#define CAP_LINK_SPEED_TO_VECTOR(val) (1 << ((val) - 1))
-#define CAP_EN_CLK_POWER_MAN_GET(val) ((val & 0x100) >> 8)
-#define CAP_EN_CLK_POWER_MAN_SET(dst, src) (((dst) & ~0x100) | (((UINT32) (src) << 8) & 0x100))
-#define CAP_COMMON_CLK_SET(dst, src) (((dst) & ~0x40) | (((UINT32) (src) << 6) & 0x40))
-#define CAP_RETRAIN_LINK_SET(dst, src) (((dst) & ~0x20) | (((UINT32) (src) << 5) & 0x20))
-#define CAP_LINK_TRAINING_GET(val) ((val & 0x8000000) >> 27)
-#define CAP_LINK_DISABLE_SET(dst, src) (((dst) & ~0x10) | (((UINT32)(src) << 4) & 0x10))
+#define CAP_DLL_ACTIVE_GET(val) ((val & 0x20000000) >> 29)
+#define CAP_SLOT_CLK_CONFIG_SET(dst, src) (((dst) & ~0x10000000) | (((UINT32) (src) << 28) & 0x10000000))
+#define CAP_NEGO_LINK_WIDTH_GET(val) ((val & 0x3F00000) >> 20)
+#define CAP_LINK_SPEED_GET(val) ((val & 0xF0000) >> 16)
+#define CAP_LINK_SPEED_SET(dst, src) (((dst) & ~0xF0000) | (((UINT32) (src) << 16) & 0xF0000))
+#define CAP_LINK_SPEED_TO_VECTOR(val) (1 << ((val) - 1))
+#define CAP_EN_CLK_POWER_MAN_GET(val) ((val & 0x100) >> 8)
+#define CAP_EN_CLK_POWER_MAN_SET(dst, src) (((dst) & ~0x100) | (((UINT32) (src) << 8) & 0x100))
+#define CAP_COMMON_CLK_SET(dst, src) (((dst) & ~0x40) | (((UINT32) (src) << 6) & 0x40))
+#define CAP_RETRAIN_LINK_SET(dst, src) (((dst) & ~0x20) | (((UINT32) (src) << 5) & 0x20))
+#define CAP_LINK_TRAINING_GET(val) ((val & 0x8000000) >> 27)
+#define CAP_LINK_DISABLE_SET(dst, src) (((dst) & ~0x10) | (((UINT32)(src) << 4) & 0x10))
// SLOT_CAPABILITIES_REG
-#define SLOT_HPC_SET(dst, src) (((dst) & ~0x40) | (((UINT32) (src) << 6) & 0x40))
+#define SLOT_HPC_SET(dst, src) (((dst) & ~0x40) | (((UINT32) (src) << 6) & 0x40))
#define SLOT_CAP_SLOT_POWER_LIMIT_VALUE_SET(dst, src) \
(((dst) & ~0x7F80) | (((UINT32)(src) << 7) & 0x7F80))
// DEVICE_CONTROL2_DEVICE_STATUS2_REG
-#define CAP_CPL_TIMEOUT_VALUE_SET(dst, src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
+#define CAP_CPL_TIMEOUT_VALUE_SET(dst, src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
// LINK_CONTROL2_LINK_STATUS2_REG
-#define CAP_TARGET_LINK_SPEED_SET(dst, src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
+#define CAP_TARGET_LINK_SPEED_SET(dst, src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
//
// Advanced Error Reporting Capability
//
-#define AER_CAPABILITY_ID 0x0001
-#define UNCORR_ERR_STATUS_OFF 0x04
-#define UNCORR_ERR_MASK_OFF 0x08
+#define AER_CAPABILITY_ID 0x0001
+#define UNCORR_ERR_STATUS_OFF 0x04
+#define UNCORR_ERR_MASK_OFF 0x08
// UNCORR_ERR_MASK_OFF
-#define CMPLT_TIMEOUT_ERR_MASK_SET(dst, src) (((dst) & ~0x4000) | (((UINT32) (src) << 14) & 0x4000))
-#define SDES_ERR_MASK_SET(dst, src) (((dst) & ~0x20) | (((UINT32)(src) << 5) & 0x20))
+#define CMPLT_TIMEOUT_ERR_MASK_SET(dst, src) (((dst) & ~0x4000) | (((UINT32) (src) << 14) & 0x4000))
+#define SDES_ERR_MASK_SET(dst, src) (((dst) & ~0x20) | (((UINT32)(src) << 5) & 0x20))
//
// Vendor specific RAS D.E.S Capability
//
-#define RAS_DES_CAPABILITY_ID 0x000B
-#define EVENT_COUNTER_CONTROL_REG 0x08
-#define EVENT_COUNTER_DATA_REG 0x0C
+#define RAS_DES_CAPABILITY_ID 0x000B
+#define EVENT_COUNTER_CONTROL_REG 0x08
+#define EVENT_COUNTER_DATA_REG 0x0C
// EVENT_COUNTER_CONTROL_REG
-#define ECCR_GROUP_EVENT_SEL_SET(dst, src) (((dst) & ~0xFFF0000) | (((UINT32)(src) << 16) & 0xFFF0000))
-#define ECCR_GROUP_SEL_SET(dst, src) (((dst) & ~0xF000000) | (((UINT32)(src) << 24) & 0xF000000))
-#define ECCR_EVENT_SEL_SET(dst, src) (((dst) & ~0xFF0000) | (((UINT32)(src) << 16) & 0xFF0000))
-#define ECCR_LANE_SEL_SET(dst, src) (((dst) & ~0xF00) | (((UINT32)(src) << 8) & 0xF00))
-#define ECCR_EVENT_COUNTER_ENABLE_SET(dst, src) (((dst) & ~0x1C) | (((UINT32)(src) << 2) & 0x1C))
-#define EVENT_COUNTER_ENABLE_NO_CHANGE 0x00
-#define EVENT_COUNTER_ENABLE_ALL_ON 0x07
+#define ECCR_GROUP_EVENT_SEL_SET(dst, src) (((dst) & ~0xFFF0000) | (((UINT32)(src) << 16) & 0xFFF0000))
+#define ECCR_GROUP_SEL_SET(dst, src) (((dst) & ~0xF000000) | (((UINT32)(src) << 24) & 0xF000000))
+#define ECCR_EVENT_SEL_SET(dst, src) (((dst) & ~0xFF0000) | (((UINT32)(src) << 16) & 0xFF0000))
+#define ECCR_LANE_SEL_SET(dst, src) (((dst) & ~0xF00) | (((UINT32)(src) << 8) & 0xF00))
+#define ECCR_EVENT_COUNTER_ENABLE_SET(dst, src) (((dst) & ~0x1C) | (((UINT32)(src) << 2) & 0x1C))
+#define EVENT_COUNTER_ENABLE_NO_CHANGE 0x00
+#define EVENT_COUNTER_ENABLE_ALL_ON 0x07
#define ECCR_EVENT_COUNTER_CLEAR_SET(dst, src) (((dst) & ~0x3) | (((UINT32)(src)) & 0x3))
-#define EVENT_COUNTER_CLEAR_NO_CHANGE 0x00
-#define EVENT_COUNTER_CLEAR_ALL_CLEAR 0x03
+#define EVENT_COUNTER_CLEAR_NO_CHANGE 0x00
+#define EVENT_COUNTER_CLEAR_ALL_CLEAR 0x03
//
// Secondary PCI Express Capability
//
-#define SPCIE_CAPABILITY_ID 0x0019
-#define SPCIE_CAP_OFF_0C_REG 0x0C
+#define SPCIE_CAPABILITY_ID 0x0019
+#define SPCIE_CAP_OFF_0C_REG 0x0C
// SPCIE_CAP_OFF_0C_REG
-#define DSP_TX_PRESET0_SET(dst,src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
-#define DSP_TX_PRESET1_SET(dst,src) (((dst) & ~0xF0000) | (((UINT32) (src) << 16) & 0xF0000))
-#define DEFAULT_GEN3_PRESET 0x05
+#define DSP_TX_PRESET0_SET(dst, src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
+#define DSP_TX_PRESET1_SET(dst, src) (((dst) & ~0xF0000) | (((UINT32) (src) << 16) & 0xF0000))
+#define DEFAULT_GEN3_PRESET 0x05
//
// Physical Layer 16.0 GT/s Extended Capability
//
-#define PL16G_CAPABILITY_ID 0x0026
-#define PL16G_STATUS_REG 0x0C
-#define PL16G_CAP_OFF_20H_REG 0x20
+#define PL16G_CAPABILITY_ID 0x0026
+#define PL16G_STATUS_REG 0x0C
+#define PL16G_CAP_OFF_20H_REG 0x20
// PL16G_STATUS_REG
-#define PL16G_STATUS_EQ_CPL_GET(val) (val & 0x1)
-#define PL16G_STATUS_EQ_CPL_P1_GET(val) ((val & 0x2) >> 1)
-#define PL16G_STATUS_EQ_CPL_P2_GET(val) ((val & 0x4) >> 2)
-#define PL16G_STATUS_EQ_CPL_P3_GET(val) ((val & 0x8) >> 3)
+#define PL16G_STATUS_EQ_CPL_GET(val) (val & 0x1)
+#define PL16G_STATUS_EQ_CPL_P1_GET(val) ((val & 0x2) >> 1)
+#define PL16G_STATUS_EQ_CPL_P2_GET(val) ((val & 0x4) >> 2)
+#define PL16G_STATUS_EQ_CPL_P3_GET(val) ((val & 0x8) >> 3)
// PL16G_CAP_OFF_20H_REG
-#define DSP_16G_TX_PRESET0_SET(dst,src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
-#define DSP_16G_TX_PRESET1_SET(dst,src) (((dst) & ~0xF00) | (((UINT32) (src) << 8) & 0xF00))
-#define DSP_16G_TX_PRESET2_SET(dst,src) (((dst) & ~0xF0000) | (((UINT32) (src) << 16) & 0xF0000))
-#define DSP_16G_TX_PRESET3_SET(dst,src) (((dst) & ~0xF000000) | (((UINT32) (src) << 24) & 0xF000000))
-#define DSP_16G_RXTX_PRESET0_SET(dst,src) (((dst) & ~0xFF) | (((UINT32) (src)) & 0xFF))
-#define DSP_16G_RXTX_PRESET1_SET(dst,src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
-#define DSP_16G_RXTX_PRESET2_SET(dst,src) (((dst) & ~0xFF0000) | (((UINT32) (src) << 16) & 0xFF0000))
-#define DSP_16G_RXTX_PRESET3_SET(dst,src) (((dst) & ~0xFF000000) | (((UINT32) (src) << 24) & 0xFF000000))
-#define DEFAULT_GEN4_PRESET 0x57
+#define DSP_16G_TX_PRESET0_SET(dst, src) (((dst) & ~0xF) | (((UINT32) (src)) & 0xF))
+#define DSP_16G_TX_PRESET1_SET(dst, src) (((dst) & ~0xF00) | (((UINT32) (src) << 8) & 0xF00))
+#define DSP_16G_TX_PRESET2_SET(dst, src) (((dst) & ~0xF0000) | (((UINT32) (src) << 16) & 0xF0000))
+#define DSP_16G_TX_PRESET3_SET(dst, src) (((dst) & ~0xF000000) | (((UINT32) (src) << 24) & 0xF000000))
+#define DSP_16G_RXTX_PRESET0_SET(dst, src) (((dst) & ~0xFF) | (((UINT32) (src)) & 0xFF))
+#define DSP_16G_RXTX_PRESET1_SET(dst, src) (((dst) & ~0xFF00) | (((UINT32) (src) << 8) & 0xFF00))
+#define DSP_16G_RXTX_PRESET2_SET(dst, src) (((dst) & ~0xFF0000) | (((UINT32) (src) << 16) & 0xFF0000))
+#define DSP_16G_RXTX_PRESET3_SET(dst, src) (((dst) & ~0xFF000000) | (((UINT32) (src) << 24) & 0xFF000000))
+#define DEFAULT_GEN4_PRESET 0x57
//
// Port Logic
//
-#define PORT_LINK_CTRL_OFF 0x710
-#define FILTER_MASK_2_OFF 0x720
-#define GEN2_CTRL_OFF 0x80C
-#define GEN3_RELATED_OFF 0x890
-#define GEN3_EQ_CONTROL_OFF 0x8A8
-#define MISC_CONTROL_1_OFF 0x8BC
-#define AMBA_ERROR_RESPONSE_DEFAULT_OFF 0x8D0
-#define AMBA_LINK_TIMEOUT_OFF 0x8D4
-#define AMBA_ORDERING_CTRL_OFF 0x8D8
-#define DTIM_CTRL0_OFF 0xAB0
-#define AUX_CLK_FREQ_OFF 0xB40
-#define CCIX_CTRL_OFF 0xC20
+#define PORT_LINK_CTRL_OFF 0x710
+#define FILTER_MASK_2_OFF 0x720
+#define GEN2_CTRL_OFF 0x80C
+#define GEN3_RELATED_OFF 0x890
+#define GEN3_EQ_CONTROL_OFF 0x8A8
+#define MISC_CONTROL_1_OFF 0x8BC
+#define AMBA_ERROR_RESPONSE_DEFAULT_OFF 0x8D0
+#define AMBA_LINK_TIMEOUT_OFF 0x8D4
+#define AMBA_ORDERING_CTRL_OFF 0x8D8
+#define DTIM_CTRL0_OFF 0xAB0
+#define AUX_CLK_FREQ_OFF 0xB40
+#define CCIX_CTRL_OFF 0xC20
// PORT_LINK_CTRL_OFF
-#define LINK_CAPABLE_SET(dst, src) (((dst) & ~0x3F0000) | (((UINT32) (src) << 16) & 0x3F0000))
-#define LINK_CAPABLE_X1 0x1
-#define LINK_CAPABLE_X2 0x3
-#define LINK_CAPABLE_X4 0x7
-#define LINK_CAPABLE_X8 0xF
-#define LINK_CAPABLE_X16 0x1F
-#define LINK_CAPABLE_X32 0x3F
-#define FAST_LINK_MODE_SET(dst, src) (((dst) & ~0x80) | (((UINT32) (src) << 7) & 0x80))
+#define LINK_CAPABLE_SET(dst, src) (((dst) & ~0x3F0000) | (((UINT32) (src) << 16) & 0x3F0000))
+#define LINK_CAPABLE_X1 0x1
+#define LINK_CAPABLE_X2 0x3
+#define LINK_CAPABLE_X4 0x7
+#define LINK_CAPABLE_X8 0xF
+#define LINK_CAPABLE_X16 0x1F
+#define LINK_CAPABLE_X32 0x3F
+#define FAST_LINK_MODE_SET(dst, src) (((dst) & ~0x80) | (((UINT32) (src) << 7) & 0x80))
// FILTER_MASK_2_OFF
#define CX_FLT_MASK_VENMSG0_DROP_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
@@ -334,50 +334,50 @@ #define CX_FLT_MASK_DABORT_4UCPL_SET(dst, src) (((dst) & ~0x4) | (((UINT32) (src) << 2) & 0x4))
// GEN2_CTRL_OFF
-#define NUM_OF_LANES_SET(dst, src) (((dst) & ~0x1F00) | (((UINT32) (src) << 8) & 0x1F00))
-#define NUM_OF_LANES_X2 0x2
-#define NUM_OF_LANES_X4 0x4
-#define NUM_OF_LANES_X8 0x8
-#define NUM_OF_LANES_X16 0x10
+#define NUM_OF_LANES_SET(dst, src) (((dst) & ~0x1F00) | (((UINT32) (src) << 8) & 0x1F00))
+#define NUM_OF_LANES_X2 0x2
+#define NUM_OF_LANES_X4 0x4
+#define NUM_OF_LANES_X8 0x8
+#define NUM_OF_LANES_X16 0x10
// GEN3_RELATED_OFF
-#define RATE_SHADOW_SEL_SET(dst, src) (((dst) & ~0x3000000) | (((UINT32) (src) << 24) & 0x3000000))
-#define GEN3_DATA_RATE 0x00
-#define GEN4_DATA_RATE 0x01
-#define EQ_PHASE_2_3_SET(dst, src) (((dst) & ~0x200) | (((UINT32) (src) << 9) & 0x200))
-#define ENABLE_EQ_PHASE_2_3 0x00
-#define DISABLE_EQ_PHASE_2_3 0x01
-#define RXEQ_REGRDLESS_SET(dst, src) (((dst) & ~0x2000) | (((UINT32) (src) << 13) & 0x2000))
-#define ASSERT_RXEQ 0x01
+#define RATE_SHADOW_SEL_SET(dst, src) (((dst) & ~0x3000000) | (((UINT32) (src) << 24) & 0x3000000))
+#define GEN3_DATA_RATE 0x00
+#define GEN4_DATA_RATE 0x01
+#define EQ_PHASE_2_3_SET(dst, src) (((dst) & ~0x200) | (((UINT32) (src) << 9) & 0x200))
+#define ENABLE_EQ_PHASE_2_3 0x00
+#define DISABLE_EQ_PHASE_2_3 0x01
+#define RXEQ_REGRDLESS_SET(dst, src) (((dst) & ~0x2000) | (((UINT32) (src) << 13) & 0x2000))
+#define ASSERT_RXEQ 0x01
// GEN3_EQ_CONTROL_OFF
-#define GEN3_EQ_FB_MODE(dst, src) (((dst) & ~0xF) | ((UINT32) (src) & 0xF))
-#define FOM_METHOD 0x01
-#define GEN3_EQ_PRESET_VEC(dst, src) (((dst) & 0xFF0000FF) | (((UINT32) (src) << 8) & 0xFFFF00))
-#define EQ_DEFAULT_PRESET_VECTOR 0x370
-#define GEN3_EQ_INIT_EVAL(dst,src) (((dst) & ~0x1000000) | (((UINT32) (src) << 24) & 0x1000000))
-#define INCLUDE_INIT_FOM 0x01
+#define GEN3_EQ_FB_MODE(dst, src) (((dst) & ~0xF) | ((UINT32) (src) & 0xF))
+#define FOM_METHOD 0x01
+#define GEN3_EQ_PRESET_VEC(dst, src) (((dst) & 0xFF0000FF) | (((UINT32) (src) << 8) & 0xFFFF00))
+#define EQ_DEFAULT_PRESET_VECTOR 0x370
+#define GEN3_EQ_INIT_EVAL(dst, src) (((dst) & ~0x1000000) | (((UINT32) (src) << 24) & 0x1000000))
+#define INCLUDE_INIT_FOM 0x01
// MISC_CONTROL_1_OFF
-#define DBI_RO_WR_EN_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
-#define ENABLE_WR 0x01
-#define DISABLE_WR 0x00
+#define DBI_RO_WR_EN_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
+#define ENABLE_WR 0x01
+#define DISABLE_WR 0x00
// AMBA_ERROR_RESPONSE_DEFAULT_OFF
-#define AMBA_ERROR_RESPONSE_CRS_SET(dst, src) (((dst) & ~0x18) | (((UINT32) (src) << 3) & 0x18))
-#define AMBA_ERROR_RESPONSE_GLOBAL_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
+#define AMBA_ERROR_RESPONSE_CRS_SET(dst, src) (((dst) & ~0x18) | (((UINT32) (src) << 3) & 0x18))
+#define AMBA_ERROR_RESPONSE_GLOBAL_SET(dst, src) (((dst) & ~0x1) | (((UINT32) (src)) & 0x1))
// AMBA_LINK_TIMEOUT_OFF
-#define LINK_TIMEOUT_PERIOD_DEFAULT_SET(dst, src) (((dst) & ~0xFF) | (((UINT32) (src)) & 0xFF))
+#define LINK_TIMEOUT_PERIOD_DEFAULT_SET(dst, src) (((dst) & ~0xFF) | (((UINT32) (src)) & 0xFF))
// AMBA_ORDERING_CTRL_OFF
-#define AX_MSTR_ZEROLREAD_FW_SET(dst, src) (((dst) & ~0x80) | (((UINT32) (src) << 7) & 0x80))
+#define AX_MSTR_ZEROLREAD_FW_SET(dst, src) (((dst) & ~0x80) | (((UINT32) (src) << 7) & 0x80))
// DTIM_CTRL0_OFF
-#define DTIM_CTRL0_ROOT_PORT_ID_SET(dst, src) (((dst) & ~0xFFFF) | (((UINT32) (src)) & 0xFFFF))
+#define DTIM_CTRL0_ROOT_PORT_ID_SET(dst, src) (((dst) & ~0xFFFF) | (((UINT32) (src)) & 0xFFFF))
// AUX_CLK_FREQ_OFF
-#define AUX_CLK_FREQ_SET(dst, src) (((dst) & ~0x1FF) | (((UINT32) (src)) & 0x1FF))
-#define AUX_CLK_500MHZ 500
+#define AUX_CLK_FREQ_SET(dst, src) (((dst) & ~0x1FF) | (((UINT32) (src)) & 0x1FF))
+#define AUX_CLK_500MHZ 500
#endif /* AC01_PCIE_CORE_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.c index f6d9c5e279..c06939a981 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLib.c @@ -14,7 +14,7 @@ #include <Library/DebugLib.h>
#include <Library/HobLib.h>
-VOID *mPlatformInfoHob = NULL;
+VOID *mPlatformInfoHob = NULL;
/**
Get the platform HOB data.
@@ -36,7 +36,7 @@ GetPlatformHob ( DEBUG ((DEBUG_ERROR, "%a: Failed to get gPlatformInfoHobGuid!\n", __func__));
return NULL;
}
- }
+ }
return ((PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (mPlatformInfoHob));
}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLibCommon.c b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLibCommon.c index d140d6ec43..a30bb98661 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLibCommon.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/AmpereCpuLibCommon.c @@ -19,105 +19,105 @@ #include <NVParamDef.h>
#include <Platform/Ac01.h>
-UINT32 Ac01CoreOrderMonolithic[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
- 36, 37, 40, 41, 52, 53, 56, 57, 32, 33,
- 44, 45, 48, 49, 60, 61, 20, 21, 24, 25,
- 68, 69, 72, 73, 16, 17, 28, 29, 64, 65,
- 76, 77, 4, 5, 8, 9, 0, 1, 12, 13,
- 38, 39, 42, 43, 54, 55, 58, 59, 34, 35,
- 46, 47, 50, 51, 62, 63, 22, 23, 26, 27,
- 70, 71, 74, 75, 18, 19, 30, 31, 66, 67,
- 78, 79, 6, 7, 10, 11, 2, 3, 14, 15,
- 80, 81, 82, 83, 84, 85, 86, 87,
- 88, 89, 90, 91, 92, 93, 94, 95,
- 96, 97, 98, 99, 100, 101, 102, 103,
+UINT32 Ac01CoreOrderMonolithic[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
+ 36, 37, 40, 41, 52, 53, 56, 57, 32, 33,
+ 44, 45, 48, 49, 60, 61, 20, 21, 24, 25,
+ 68, 69, 72, 73, 16, 17, 28, 29, 64, 65,
+ 76, 77, 4, 5, 8, 9, 0, 1, 12, 13,
+ 38, 39, 42, 43, 54, 55, 58, 59, 34, 35,
+ 46, 47, 50, 51, 62, 63, 22, 23, 26, 27,
+ 70, 71, 74, 75, 18, 19, 30, 31, 66, 67,
+ 78, 79, 6, 7, 10, 11, 2, 3, 14, 15,
+ 80, 81, 82, 83, 84, 85, 86, 87,
+ 88, 89, 90, 91, 92, 93, 94, 95,
+ 96, 97, 98, 99, 100, 101, 102, 103,
104, 105, 106, 107, 108, 109, 110, 111,
112, 113, 114, 115, 116, 117, 118, 119,
120, 121, 122, 123, 124, 125, 126, 127,
};
-UINT32 Ac01CoreOrderHemisphere[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
- 32, 33, 48, 49, 16, 17, 64, 65, 36, 37,
- 52, 53, 0, 1, 20, 21, 68, 69, 4, 5,
- 34, 35, 50, 51, 18, 19, 66, 67, 38, 39,
- 54, 55, 2, 3, 22, 23, 70, 71, 6, 7,
- 44, 45, 60, 61, 28, 29, 76, 77, 40, 41,
- 56, 57, 12, 13, 24, 25, 72, 73, 8, 9,
- 46, 47, 62, 63, 30, 31, 78, 79, 42, 43,
- 58, 59, 14, 15, 26, 27, 74, 75, 10, 11,
- 80, 81, 82, 83, 84, 85, 86, 87,
- 88, 89, 90, 91, 92, 93, 94, 95,
- 96, 97, 98, 99, 100, 101, 102, 103,
+UINT32 Ac01CoreOrderHemisphere[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
+ 32, 33, 48, 49, 16, 17, 64, 65, 36, 37,
+ 52, 53, 0, 1, 20, 21, 68, 69, 4, 5,
+ 34, 35, 50, 51, 18, 19, 66, 67, 38, 39,
+ 54, 55, 2, 3, 22, 23, 70, 71, 6, 7,
+ 44, 45, 60, 61, 28, 29, 76, 77, 40, 41,
+ 56, 57, 12, 13, 24, 25, 72, 73, 8, 9,
+ 46, 47, 62, 63, 30, 31, 78, 79, 42, 43,
+ 58, 59, 14, 15, 26, 27, 74, 75, 10, 11,
+ 80, 81, 82, 83, 84, 85, 86, 87,
+ 88, 89, 90, 91, 92, 93, 94, 95,
+ 96, 97, 98, 99, 100, 101, 102, 103,
104, 105, 106, 107, 108, 109, 110, 111,
112, 113, 114, 115, 116, 117, 118, 119,
120, 121, 122, 123, 124, 125, 126, 127,
};
-UINT32 Ac01CoreOrderQuadrant[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
- 16, 17, 32, 33, 0, 1, 20, 21, 4, 5,
- 18, 19, 34, 35, 2, 3, 22, 23, 6, 7,
- 48, 49, 64, 65, 52, 53, 68, 69, 36, 37,
- 50, 51, 66, 67, 54, 55, 70, 71, 38, 39,
- 28, 29, 44, 45, 12, 13, 24, 25, 8, 9,
- 30, 31, 46, 47, 14, 15, 26, 27, 10, 11,
- 60, 61, 76, 77, 56, 57, 72, 73, 40, 41,
- 62, 63, 78, 79, 58, 59, 74, 75, 42, 43,
- 80, 81, 82, 83, 84, 85, 86, 87,
- 88, 89, 90, 91, 92, 93, 94, 95,
- 96, 97, 98, 99, 100, 101, 102, 103,
+UINT32 Ac01CoreOrderQuadrant[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
+ 16, 17, 32, 33, 0, 1, 20, 21, 4, 5,
+ 18, 19, 34, 35, 2, 3, 22, 23, 6, 7,
+ 48, 49, 64, 65, 52, 53, 68, 69, 36, 37,
+ 50, 51, 66, 67, 54, 55, 70, 71, 38, 39,
+ 28, 29, 44, 45, 12, 13, 24, 25, 8, 9,
+ 30, 31, 46, 47, 14, 15, 26, 27, 10, 11,
+ 60, 61, 76, 77, 56, 57, 72, 73, 40, 41,
+ 62, 63, 78, 79, 58, 59, 74, 75, 42, 43,
+ 80, 81, 82, 83, 84, 85, 86, 87,
+ 88, 89, 90, 91, 92, 93, 94, 95,
+ 96, 97, 98, 99, 100, 101, 102, 103,
104, 105, 106, 107, 108, 109, 110, 111,
112, 113, 114, 115, 116, 117, 118, 119,
120, 121, 122, 123, 124, 125, 126, 127,
};
-UINT32 Ac02CoreOrderMonolithic[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
- 36, 37, 40, 41, 52, 53, 56, 57, 32, 33,
- 44, 45, 48, 49, 60, 61, 20, 21, 24, 25,
- 68, 69, 72, 73, 16, 17, 28, 29, 64, 65,
- 76, 77, 4, 5, 8, 9, 84, 85, 88, 89,
- 0, 1, 12, 13, 80, 81, 92, 93, 100, 101,
- 104, 105, 96, 97, 108, 109, 116, 117, 120, 121,
- 112, 113, 124, 125, 38, 39, 42, 43, 54, 55,
- 58, 59, 34, 35, 46, 47, 50, 51, 62, 63,
- 22, 23, 26, 27, 70, 71, 74, 75, 18, 19,
- 30, 31, 66, 67, 78, 79, 6, 7, 10, 11,
- 86, 87, 90, 91, 2, 3, 14, 15, 82, 83,
- 94, 95, 102, 103, 106, 107, 98, 99, 110, 111,
+UINT32 Ac02CoreOrderMonolithic[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
+ 36, 37, 40, 41, 52, 53, 56, 57, 32, 33,
+ 44, 45, 48, 49, 60, 61, 20, 21, 24, 25,
+ 68, 69, 72, 73, 16, 17, 28, 29, 64, 65,
+ 76, 77, 4, 5, 8, 9, 84, 85, 88, 89,
+ 0, 1, 12, 13, 80, 81, 92, 93, 100, 101,
+ 104, 105, 96, 97, 108, 109, 116, 117, 120, 121,
+ 112, 113, 124, 125, 38, 39, 42, 43, 54, 55,
+ 58, 59, 34, 35, 46, 47, 50, 51, 62, 63,
+ 22, 23, 26, 27, 70, 71, 74, 75, 18, 19,
+ 30, 31, 66, 67, 78, 79, 6, 7, 10, 11,
+ 86, 87, 90, 91, 2, 3, 14, 15, 82, 83,
+ 94, 95, 102, 103, 106, 107, 98, 99, 110, 111,
118, 119, 122, 123, 114, 115, 126, 127,
};
-UINT32 Ac02CoreOrderHemisphere[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
- 32, 33, 48, 49, 16, 17, 64, 65, 36, 37,
- 52, 53, 0, 1, 20, 21, 68, 69, 80, 81,
- 4, 5, 84, 85, 96, 97, 100, 101, 112, 113,
- 116, 117, 34, 35, 50, 51, 18, 19, 66, 67,
- 38, 39, 54, 55, 2, 3, 22, 23, 70, 71,
- 82, 83, 6, 7, 86, 87, 98, 99, 102, 103,
- 114, 115, 118, 119, 44, 45, 60, 61, 28, 29,
- 76, 77, 40, 41, 56, 57, 12, 13, 24, 25,
- 72, 73, 92, 93, 8, 9, 88, 89, 108, 109,
- 104, 105, 124, 125, 120, 121, 46, 47, 62, 63,
- 30, 31, 78, 79, 42, 43, 58, 59, 14, 15,
- 26, 27, 74, 75, 94, 95, 10, 11, 90, 91,
+UINT32 Ac02CoreOrderHemisphere[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
+ 32, 33, 48, 49, 16, 17, 64, 65, 36, 37,
+ 52, 53, 0, 1, 20, 21, 68, 69, 80, 81,
+ 4, 5, 84, 85, 96, 97, 100, 101, 112, 113,
+ 116, 117, 34, 35, 50, 51, 18, 19, 66, 67,
+ 38, 39, 54, 55, 2, 3, 22, 23, 70, 71,
+ 82, 83, 6, 7, 86, 87, 98, 99, 102, 103,
+ 114, 115, 118, 119, 44, 45, 60, 61, 28, 29,
+ 76, 77, 40, 41, 56, 57, 12, 13, 24, 25,
+ 72, 73, 92, 93, 8, 9, 88, 89, 108, 109,
+ 104, 105, 124, 125, 120, 121, 46, 47, 62, 63,
+ 30, 31, 78, 79, 42, 43, 58, 59, 14, 15,
+ 26, 27, 74, 75, 94, 95, 10, 11, 90, 91,
110, 111, 106, 107, 126, 127, 122, 123,
};
-UINT32 Ac02CoreOrderQuadrant[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
- 16, 17, 32, 33, 0, 1, 20, 21,
- 36, 37, 4, 5, 84, 85, 96, 97,
- 18, 19, 34, 35, 2, 3, 22, 23,
- 38, 39, 6, 7, 86, 87, 98, 99,
- 48, 49, 64, 65, 52, 53, 68, 69,
+UINT32 Ac02CoreOrderQuadrant[PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM] = {
+ 16, 17, 32, 33, 0, 1, 20, 21,
+ 36, 37, 4, 5, 84, 85, 96, 97,
+ 18, 19, 34, 35, 2, 3, 22, 23,
+ 38, 39, 6, 7, 86, 87, 98, 99,
+ 48, 49, 64, 65, 52, 53, 68, 69,
80, 81, 100, 101, 112, 113, 116, 117,
- 50, 51, 66, 67, 54, 55, 70, 71,
+ 50, 51, 66, 67, 54, 55, 70, 71,
82, 83, 102, 103, 114, 115, 118, 119,
- 28, 29, 44, 45, 12, 13, 24, 25,
- 40, 41, 8, 9, 88, 89, 108, 109,
- 30, 31, 46, 47, 14, 15, 26, 27,
- 42, 43, 10, 11, 90, 91, 110, 111,
- 60, 61, 76, 77, 56, 57, 72, 73,
+ 28, 29, 44, 45, 12, 13, 24, 25,
+ 40, 41, 8, 9, 88, 89, 108, 109,
+ 30, 31, 46, 47, 14, 15, 26, 27,
+ 42, 43, 10, 11, 90, 91, 110, 111,
+ 60, 61, 76, 77, 56, 57, 72, 73,
92, 93, 104, 105, 124, 125, 120, 121,
- 62, 63, 78, 79, 58, 59, 74, 75,
+ 62, 63, 78, 79, 58, 59, 74, 75,
94, 95, 106, 107, 126, 127, 122, 123,
};
@@ -136,7 +136,7 @@ GetPlatformHob ( UINTN
EFIAPI
CpuGetCurrentFreq (
- UINT8 Socket
+ UINT8 Socket
)
{
PLATFORM_INFO_HOB *PlatformHob;
@@ -157,7 +157,7 @@ CpuGetCurrentFreq ( UINTN
EFIAPI
CpuGetMaxFreq (
- UINT8 Socket
+ UINT8 Socket
)
{
PLATFORM_INFO_HOB *PlatformHob;
@@ -182,7 +182,7 @@ CpuGetMaxFreq ( UINT8
EFIAPI
CpuGetVoltage (
- UINT8 Socket
+ UINT8 Socket
)
{
PLATFORM_INFO_HOB *PlatformHob;
@@ -206,8 +206,8 @@ CpuGetVoltage ( VOID
EFIAPI
CpuGetEcid (
- UINT8 SocketId,
- UINT32 **Ecid
+ UINT8 SocketId,
+ UINT32 **Ecid
)
{
PLATFORM_INFO_HOB *PlatformHob;
@@ -228,7 +228,7 @@ CpuGetEcid ( UINT8
EFIAPI
GetSkuMaxCore (
- UINT8 SocketId
+ UINT8 SocketId
)
{
PLATFORM_INFO_HOB *PlatformHob;
@@ -251,7 +251,7 @@ GetSkuMaxCore ( UINT8
EFIAPI
GetSkuMaxTurbo (
- UINT8 SocketId
+ UINT8 SocketId
)
{
PLATFORM_INFO_HOB *PlatformHob;
@@ -275,26 +275,26 @@ CpuGetCoreOrder ( VOID
)
{
- UINT32 *CoreOrder;
- UINT8 SubNumaMode;
- BOOLEAN IsAc01;
+ UINT32 *CoreOrder;
+ UINT8 SubNumaMode;
+ BOOLEAN IsAc01;
SubNumaMode = CpuGetSubNumaMode ();
- IsAc01 = IsAc01Processor ();
+ IsAc01 = IsAc01Processor ();
switch (SubNumaMode) {
- case SUBNUMA_MODE_MONOLITHIC:
- default:
- CoreOrder = IsAc01 ? Ac01CoreOrderMonolithic : Ac02CoreOrderMonolithic;
- break;
-
- case SUBNUMA_MODE_HEMISPHERE:
- CoreOrder = IsAc01 ? Ac01CoreOrderHemisphere : Ac02CoreOrderHemisphere;
- break;
-
- case SUBNUMA_MODE_QUADRANT:
- CoreOrder = IsAc01 ? Ac01CoreOrderQuadrant : Ac02CoreOrderQuadrant;
- break;
+ case SUBNUMA_MODE_MONOLITHIC:
+ default:
+ CoreOrder = IsAc01 ? Ac01CoreOrderMonolithic : Ac02CoreOrderMonolithic;
+ break;
+
+ case SUBNUMA_MODE_HEMISPHERE:
+ CoreOrder = IsAc01 ? Ac01CoreOrderHemisphere : Ac02CoreOrderHemisphere;
+ break;
+
+ case SUBNUMA_MODE_QUADRANT:
+ CoreOrder = IsAc01 ? Ac01CoreOrderQuadrant : Ac02CoreOrderQuadrant;
+ break;
}
return CoreOrder;
@@ -334,30 +334,30 @@ CpuGetNumberOfSubNumaRegion ( VOID
)
{
- UINT8 SubNumaMode;
- UINT8 NumberOfSubNumaRegion;
+ UINT8 SubNumaMode;
+ UINT8 NumberOfSubNumaRegion;
SubNumaMode = CpuGetSubNumaMode ();
ASSERT (SubNumaMode <= SUBNUMA_MODE_QUADRANT);
switch (SubNumaMode) {
- case SUBNUMA_MODE_MONOLITHIC:
- NumberOfSubNumaRegion = MONOLITIC_NUM_OF_REGION;
- break;
-
- case SUBNUMA_MODE_HEMISPHERE:
- NumberOfSubNumaRegion = HEMISPHERE_NUM_OF_REGION;
- break;
-
- case SUBNUMA_MODE_QUADRANT:
- NumberOfSubNumaRegion = QUADRANT_NUM_OF_REGION;
- break;
-
- default:
- // Should never reach there.
- NumberOfSubNumaRegion = 0;
- ASSERT (FALSE);
- break;
+ case SUBNUMA_MODE_MONOLITHIC:
+ NumberOfSubNumaRegion = MONOLITIC_NUM_OF_REGION;
+ break;
+
+ case SUBNUMA_MODE_HEMISPHERE:
+ NumberOfSubNumaRegion = HEMISPHERE_NUM_OF_REGION;
+ break;
+
+ case SUBNUMA_MODE_QUADRANT:
+ NumberOfSubNumaRegion = QUADRANT_NUM_OF_REGION;
+ break;
+
+ default:
+ // Should never reach there.
+ NumberOfSubNumaRegion = 0;
+ ASSERT (FALSE);
+ break;
}
return NumberOfSubNumaRegion;
@@ -366,14 +366,14 @@ CpuGetNumberOfSubNumaRegion ( STATIC
UINT8
CpuGetLogicCoreId (
- UINT32 PhyCoreId
+ UINT32 PhyCoreId
)
{
- UINT32 *CoreOrder;
- UINT8 LogicCoreId;
- UINT8 SktMaxCoreNum ;
+ UINT32 *CoreOrder;
+ UINT8 LogicCoreId;
+ UINT8 SktMaxCoreNum;
- CoreOrder = CpuGetCoreOrder();
+ CoreOrder = CpuGetCoreOrder ();
SktMaxCoreNum = PLATFORM_CPU_MAX_CPM * PLATFORM_CPU_NUM_CORES_PER_CPM;
for (LogicCoreId = 0; LogicCoreId < SktMaxCoreNum; LogicCoreId++) {
@@ -388,44 +388,46 @@ CpuGetLogicCoreId ( UINT8
EFIAPI
CpuGetSubNumNode (
- UINT8 SocketId,
- UINT16 Cpm
+ UINT8 SocketId,
+ UINT16 Cpm
)
{
- UINT8 LogicCoreId;
- UINT8 MaxFamliyCore;
- UINT8 MaxNumCorePerNode;
- UINT8 SubNumaNode;
+ UINT8 LogicCoreId;
+ UINT8 MaxFamliyCore;
+ UINT8 MaxNumCorePerNode;
+ UINT8 SubNumaNode;
- LogicCoreId = CpuGetLogicCoreId (Cpm * PLATFORM_CPU_NUM_CORES_PER_CPM);
+ LogicCoreId = CpuGetLogicCoreId (Cpm * PLATFORM_CPU_NUM_CORES_PER_CPM);
MaxFamliyCore = IsAc01Processor () ? MAX_AMPERE_ALTRA_CORES : MAX_AMPERE_ALTRA_MAX_CORES;
switch (CpuGetSubNumaMode ()) {
- case SUBNUMA_MODE_MONOLITHIC:
- SubNumaNode = (SocketId == 0) ? 0 : 1;
- break;
-
- case SUBNUMA_MODE_HEMISPHERE:
- MaxNumCorePerNode = MaxFamliyCore / HEMISPHERE_NUM_OF_REGION;
- SubNumaNode = LogicCoreId / MaxNumCorePerNode;
- if (SocketId == 1) {
- SubNumaNode += HEMISPHERE_NUM_OF_REGION;
- }
- break;
+ case SUBNUMA_MODE_MONOLITHIC:
+ SubNumaNode = (SocketId == 0) ? 0 : 1;
+ break;
- case SUBNUMA_MODE_QUADRANT:
- MaxNumCorePerNode = MaxFamliyCore / QUADRANT_NUM_OF_REGION;
- SubNumaNode = LogicCoreId / MaxNumCorePerNode;
- if (SocketId == 1) {
- SubNumaNode += QUADRANT_NUM_OF_REGION;
- }
- break;
+ case SUBNUMA_MODE_HEMISPHERE:
+ MaxNumCorePerNode = MaxFamliyCore / HEMISPHERE_NUM_OF_REGION;
+ SubNumaNode = LogicCoreId / MaxNumCorePerNode;
+ if (SocketId == 1) {
+ SubNumaNode += HEMISPHERE_NUM_OF_REGION;
+ }
- default:
- // Should never reach there.
- SubNumaNode = (SocketId == 0) ? 0 : 1;
- ASSERT (FALSE);
- break;
+ break;
+
+ case SUBNUMA_MODE_QUADRANT:
+ MaxNumCorePerNode = MaxFamliyCore / QUADRANT_NUM_OF_REGION;
+ SubNumaNode = LogicCoreId / MaxNumCorePerNode;
+ if (SocketId == 1) {
+ SubNumaNode += QUADRANT_NUM_OF_REGION;
+ }
+
+ break;
+
+ default:
+ // Should never reach there.
+ SubNumaNode = (SocketId == 0) ? 0 : 1;
+ ASSERT (FALSE);
+ break;
}
return SubNumaNode;
@@ -468,9 +470,9 @@ GetNumberOfActiveSockets ( VOID
)
{
- UINT8 NumberOfActiveSockets, Count, Index, Index1;
- PLATFORM_CLUSTER_EN *Socket;
- PLATFORM_INFO_HOB *PlatformHob;
+ UINT8 NumberOfActiveSockets, Count, Index, Index1;
+ PLATFORM_CLUSTER_EN *Socket;
+ PLATFORM_INFO_HOB *PlatformHob;
PlatformHob = GetPlatformHob ();
if (PlatformHob == NULL) {
@@ -484,7 +486,7 @@ GetNumberOfActiveSockets ( for (Index = 0; Index < GetNumberOfSupportedSockets (); Index++) {
Socket = &PlatformHob->ClusterEn[Index];
- Count = ARRAY_SIZE (Socket->EnableMask);
+ Count = ARRAY_SIZE (Socket->EnableMask);
for (Index1 = 0; Index1 < Count; Index1++) {
if (Socket->EnableMask[Index1] != 0) {
NumberOfActiveSockets++;
@@ -506,13 +508,13 @@ GetNumberOfActiveSockets ( UINT16
EFIAPI
GetNumberOfActiveCPMsPerSocket (
- UINT8 SocketId
+ UINT8 SocketId
)
{
- UINT16 NumberOfCPMs, Count, Index;
- UINT32 Val32;
- PLATFORM_CLUSTER_EN *Socket;
- PLATFORM_INFO_HOB *PlatformHob;
+ UINT16 NumberOfCPMs, Count, Index;
+ UINT32 Val32;
+ PLATFORM_CLUSTER_EN *Socket;
+ PLATFORM_INFO_HOB *PlatformHob;
PlatformHob = GetPlatformHob ();
if (PlatformHob == NULL) {
@@ -524,14 +526,15 @@ GetNumberOfActiveCPMsPerSocket ( }
NumberOfCPMs = 0;
- Socket = &PlatformHob->ClusterEn[SocketId];
- Count = ARRAY_SIZE (Socket->EnableMask);
+ Socket = &PlatformHob->ClusterEn[SocketId];
+ Count = ARRAY_SIZE (Socket->EnableMask);
for (Index = 0; Index < Count; Index++) {
Val32 = Socket->EnableMask[Index];
while (Val32 > 0) {
if ((Val32 & 0x1) != 0) {
NumberOfCPMs++;
}
+
Val32 >>= 1;
}
}
@@ -550,17 +553,17 @@ GetNumberOfActiveCPMsPerSocket ( UINT16
EFIAPI
GetNumberOfConfiguredCPMs (
- UINT8 SocketId
+ UINT8 SocketId
)
{
- EFI_STATUS Status;
- UINT32 Value;
- UINT32 Param, ParamStart, ParamEnd;
- UINT16 Count;
+ EFI_STATUS Status;
+ UINT32 Value;
+ UINT32 Param, ParamStart, ParamEnd;
+ UINT16 Count;
- Count = 0;
+ Count = 0;
ParamStart = NV_SI_S0_PCP_ACTIVECPM_0_31 + SocketId * NV_PARAM_ENTRYSIZE * (PLATFORM_CPU_MAX_CPM / 32);
- ParamEnd = ParamStart + NV_PARAM_ENTRYSIZE * (PLATFORM_CPU_MAX_CPM / 32);
+ ParamEnd = ParamStart + NV_PARAM_ENTRYSIZE * (PLATFORM_CPU_MAX_CPM / 32);
for (Param = ParamStart; Param < ParamEnd; Param += NV_PARAM_ENTRYSIZE) {
Status = NVParamGet (
Param,
@@ -570,10 +573,12 @@ GetNumberOfConfiguredCPMs ( if (EFI_ERROR (Status)) {
break;
}
+
while (Value != 0) {
if ((Value & 0x01) != 0) {
Count++;
}
+
Value >>= 1;
}
}
@@ -589,10 +594,10 @@ GetNumberOfConfiguredCPMs ( VOID
EFIAPI
GetScpVersion (
- UINT8 **ScpVer
+ UINT8 **ScpVer
)
{
- PLATFORM_INFO_HOB *PlatformHob;
+ PLATFORM_INFO_HOB *PlatformHob;
PlatformHob = GetPlatformHob ();
if (PlatformHob != NULL) {
@@ -610,10 +615,10 @@ GetScpVersion ( VOID
EFIAPI
GetScpBuild (
- UINT8 **ScpBuild
+ UINT8 **ScpBuild
)
{
- PLATFORM_INFO_HOB *PlatformHob;
+ PLATFORM_INFO_HOB *PlatformHob;
PlatformHob = GetPlatformHob ();
if (PlatformHob != NULL) {
@@ -631,10 +636,10 @@ GetScpBuild ( VOID
EFIAPI
GetDimmList (
- PLATFORM_DIMM_LIST **DimmList
+ PLATFORM_DIMM_LIST **DimmList
)
{
- PLATFORM_INFO_HOB *PlatformHob;
+ PLATFORM_INFO_HOB *PlatformHob;
PlatformHob = GetPlatformHob ();
if (PlatformHob != NULL) {
@@ -652,10 +657,10 @@ GetDimmList ( VOID
EFIAPI
GetDramInfo (
- PLATFORM_DRAM_INFO **DramInfo
+ PLATFORM_DRAM_INFO **DramInfo
)
{
- PLATFORM_INFO_HOB *PlatformHob;
+ PLATFORM_INFO_HOB *PlatformHob;
PlatformHob = GetPlatformHob ();
if (PlatformHob != NULL) {
@@ -677,14 +682,14 @@ GetDramInfo ( EFI_STATUS
EFIAPI
SetNumberOfConfiguredCPMs (
- UINT8 SocketId,
- UINT16 NumberOfCPMs
+ UINT8 SocketId,
+ UINT16 NumberOfCPMs
)
{
- EFI_STATUS Status;
- UINT32 Value;
- UINT32 Param, ParamStart, ParamEnd;
- BOOLEAN IsClear;
+ EFI_STATUS Status;
+ UINT32 Value;
+ UINT32 Param, ParamStart, ParamEnd;
+ BOOLEAN IsClear;
IsClear = FALSE;
if (NumberOfCPMs == 0) {
@@ -694,10 +699,10 @@ SetNumberOfConfiguredCPMs ( Status = EFI_SUCCESS;
ParamStart = NV_SI_S0_PCP_ACTIVECPM_0_31 + SocketId * NV_PARAM_ENTRYSIZE * (PLATFORM_CPU_MAX_CPM / 32);
- ParamEnd = ParamStart + NV_PARAM_ENTRYSIZE * (PLATFORM_CPU_MAX_CPM / 32);
+ ParamEnd = ParamStart + NV_PARAM_ENTRYSIZE * (PLATFORM_CPU_MAX_CPM / 32);
for (Param = ParamStart; Param < ParamEnd; Param += NV_PARAM_ENTRYSIZE) {
if (NumberOfCPMs >= 32) {
- Value = 0xffffffff;
+ Value = 0xffffffff;
NumberOfCPMs -= 32;
} else {
Value = 0;
@@ -705,6 +710,7 @@ SetNumberOfConfiguredCPMs ( Value |= (1 << (--NumberOfCPMs));
}
}
+
if (IsClear) {
/* Clear this param */
Status = NVParamClr (
@@ -756,7 +762,7 @@ GetMaximumNumberOfCores ( UINT16
EFIAPI
GetNumberOfActiveCoresPerSocket (
- UINT8 SocketId
+ UINT8 SocketId
)
{
return GetNumberOfActiveCPMsPerSocket (SocketId) * PLATFORM_CPU_NUM_CORES_PER_CPM;
@@ -774,8 +780,8 @@ GetNumberOfActiveCores ( VOID
)
{
- UINT16 NumberOfActiveCores;
- UINT8 Index;
+ UINT16 NumberOfActiveCores;
+ UINT8 Index;
NumberOfActiveCores = 0;
@@ -797,15 +803,15 @@ GetNumberOfActiveCores ( BOOLEAN
EFIAPI
IsCpuEnabled (
- UINT16 CpuId
+ UINT16 CpuId
)
{
- PLATFORM_CLUSTER_EN *Socket;
- PLATFORM_INFO_HOB *PlatformHob;
- UINT8 SocketId;
- UINT16 ClusterId;
+ PLATFORM_CLUSTER_EN *Socket;
+ PLATFORM_INFO_HOB *PlatformHob;
+ UINT8 SocketId;
+ UINT16 ClusterId;
- SocketId = SOCKET_ID (CpuId);
+ SocketId = SOCKET_ID (CpuId);
ClusterId = CLUSTER_ID (CpuId);
PlatformHob = GetPlatformHob ();
@@ -838,7 +844,7 @@ IsSlaveSocketAvailable ( VOID
)
{
- UINT32 Value;
+ UINT32 Value;
Value = MmioRead32 (SMPRO_EFUSE_SHADOW0 + CFG2P_OFFSET);
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/RuntimeAmpereCpuLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/RuntimeAmpereCpuLib.c index b2eca9e583..7ea34dc3f9 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/RuntimeAmpereCpuLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/AmpereCpuLib/RuntimeAmpereCpuLib.c @@ -18,8 +18,8 @@ #include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeLib.h>
-EFI_EVENT mRuntimeAmpereCpuLibVirtualNotifyEvent = NULL;
-VOID *mPlatformInfoHob = NULL;
+EFI_EVENT mRuntimeAmpereCpuLibVirtualNotifyEvent = NULL;
+VOID *mPlatformInfoHob = NULL;
/**
Get the platform HOB data.
@@ -50,7 +50,7 @@ RuntimeAmpereCpuLibVirtualNotify ( IN VOID *Context
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
//
// Convert the platform HOB address to a virtual address.
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c index 721d473a0c..72bb6fb17e 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLib.c @@ -24,7 +24,7 @@ #include <Ppi/ArmMpCoreInfo.h>
#include <Ppi/TemporaryRamSupport.h>
-ARM_CORE_INFO mArmPlatformMpCoreInfoTable[PLATFORM_CPU_MAX_NUM_CORES];
+ARM_CORE_INFO mArmPlatformMpCoreInfoTable[PLATFORM_CPU_MAX_NUM_CORES];
/**
Return the current Boot Mode
@@ -51,25 +51,25 @@ ArmPlatformGetBootMode ( **/
EFI_STATUS
ArmPlatformInitialize (
- IN UINTN MpId
+ IN UINTN MpId
)
{
- RETURN_STATUS Status;
- UINT64 BaudRate;
- UINT32 ReceiveFifoDepth;
- EFI_PARITY_TYPE Parity;
- UINT8 DataBits;
- EFI_STOP_BITS_TYPE StopBits;
+ RETURN_STATUS Status;
+ UINT64 BaudRate;
+ UINT32 ReceiveFifoDepth;
+ EFI_PARITY_TYPE Parity;
+ UINT8 DataBits;
+ EFI_STOP_BITS_TYPE StopBits;
Status = EFI_SUCCESS;
if (FixedPcdGet64 (PcdSerialDbgRegisterBase) != 0) {
/* Debug port should use the same parameters with console */
- BaudRate = FixedPcdGet64 (PcdSerialDbgUartBaudRate);
+ BaudRate = FixedPcdGet64 (PcdSerialDbgUartBaudRate);
ReceiveFifoDepth = FixedPcdGet32 (PcdUartDefaultReceiveFifoDepth);
- Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
- DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
- StopBits = (EFI_STOP_BITS_TYPE)FixedPcdGet8 (PcdUartDefaultStopBits);
+ Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
+ DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
+ StopBits = (EFI_STOP_BITS_TYPE)FixedPcdGet8 (PcdUartDefaultStopBits);
/* Initialize uart debug port */
Status = PL011UartInitializePort (
@@ -88,34 +88,35 @@ ArmPlatformInitialize ( EFI_STATUS
PrePeiCoreGetMpCoreInfo (
- OUT UINTN *CoreCount,
- OUT ARM_CORE_INFO **ArmCoreTable
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
)
{
- UINTN mArmPlatformCoreCount;
- UINTN ClusterId;
- UINTN SocketId;
- UINTN Index;
+ UINTN mArmPlatformCoreCount;
+ UINTN ClusterId;
+ UINTN SocketId;
+ UINTN Index;
ASSERT (CoreCount != NULL);
ASSERT (ArmCoreTable != NULL);
ASSERT (*ArmCoreTable != NULL);
mArmPlatformCoreCount = 0;
- for (Index = 0; Index < PLATFORM_CPU_MAX_NUM_CORES; Index++) {
+ for (Index = 0; Index < PLATFORM_CPU_MAX_NUM_CORES; Index++) {
if (!IsCpuEnabled (Index)) {
continue;
}
- SocketId = SOCKET_ID (Index);
+
+ SocketId = SOCKET_ID (Index);
ClusterId = CLUSTER_ID (Index);
mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].Mpidr =
AC01_GET_MPIDR ((UINT64)SocketId, ClusterId, (Index % PLATFORM_CPU_NUM_CORES_PER_CPM));
mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxClearAddress = 0;
- mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxClearValue = 0;
- mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxGetAddress = 0;
- mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxSetAddress = 0;
+ mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxClearValue = 0;
+ mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxGetAddress = 0;
+ mArmPlatformMpCoreInfoTable[mArmPlatformCoreCount].MailboxSetAddress = 0;
mArmPlatformCoreCount++;
}
@@ -127,9 +128,9 @@ PrePeiCoreGetMpCoreInfo ( return EFI_SUCCESS;
}
-ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
-EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
{
EFI_PEI_PPI_DESCRIPTOR_PPI,
&gArmMpCoreInfoPpiGuid,
@@ -149,8 +150,8 @@ EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = { **/
VOID
ArmPlatformGetPlatformPpiList (
- OUT UINTN *PpiListSize,
- OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
)
{
ASSERT (PpiListSize != NULL);
@@ -158,9 +159,9 @@ ArmPlatformGetPlatformPpiList ( if (ArmIsMpCore ()) {
*PpiListSize = sizeof (gPlatformPpiTable);
- *PpiList = gPlatformPpiTable;
+ *PpiList = gPlatformPpiTable;
} else {
*PpiListSize = 0;
- *PpiList = NULL;
+ *PpiList = NULL;
}
}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLibMemory.c b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLibMemory.c index 20c5927502..1eaaae0df7 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLibMemory.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/ArmPlatformLibMemory.c @@ -19,11 +19,11 @@ #include "PlatformMemoryMap.h"
/* Number of Virtual Memory Map Descriptors */
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 50
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 50
/* DDR attributes */
-#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
-#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
/**
Return the Virtual Memory Map of your platform
@@ -37,15 +37,15 @@ **/
VOID
ArmPlatformGetVirtualMemoryMap (
- OUT ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
+ OUT ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryMap
)
{
- UINTN Index = 0;
- ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
- UINT32 NumRegion;
- UINTN Count;
- VOID *Hob;
- PLATFORM_INFO_HOB *PlatformHob;
+ UINTN Index = 0;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+ UINT32 NumRegion;
+ UINTN Count;
+ VOID *Hob;
+ PLATFORM_INFO_HOB *PlatformHob;
Hob = GetFirstGuidHob (&gPlatformInfoHobGuid);
ASSERT (Hob != NULL);
@@ -73,182 +73,184 @@ ArmPlatformGetVirtualMemoryMap ( /* For Address space 0x5000_0000_0000 to 0x5001_00FF_FFFF
* - Device memory
*/
- if (IsSlaveSocketActive ())
- {
+ if (IsSlaveSocketActive ()) {
VirtualMemoryTable[++Index].PhysicalBase = AC01_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].Length = AC01_DEVICE_MEMORY_S1_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_DEVICE_MEMORY_S1_BASE;
+ VirtualMemoryTable[Index].Length = AC01_DEVICE_MEMORY_S1_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
}
/*
* - PCIe RCA0 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCA0_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCA0_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCA0_DEVICE_MEMORY_S0_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCA0_DEVICE_MEMORY_S0_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCA0_DEVICE_MEMORY_S0_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - PCIe RCA1 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCA1_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCA1_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCA1_DEVICE_MEMORY_S0_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCA1_DEVICE_MEMORY_S0_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCA1_DEVICE_MEMORY_S0_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - PCIe RCA2 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCA2_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCA2_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCA2_DEVICE_MEMORY_S0_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCA2_DEVICE_MEMORY_S0_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCA2_DEVICE_MEMORY_S0_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - PCIe RCA3 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCA3_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCA3_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCA3_DEVICE_MEMORY_S0_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCA3_DEVICE_MEMORY_S0_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCA3_DEVICE_MEMORY_S0_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - PCIe RCB0 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCB0_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCB0_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCB0_DEVICE_MEMORY_S0_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCB0_DEVICE_MEMORY_S0_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCB0_DEVICE_MEMORY_S0_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - PCIe RCB1 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCB1_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCB1_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCB1_DEVICE_MEMORY_S0_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCB1_DEVICE_MEMORY_S0_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCB1_DEVICE_MEMORY_S0_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - PCIe RCB2 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCB2_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCB2_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCB2_DEVICE_MEMORY_S0_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCB2_DEVICE_MEMORY_S0_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCB2_DEVICE_MEMORY_S0_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - PCIe RCB3 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCB3_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCB3_DEVICE_MEMORY_S0_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCB3_DEVICE_MEMORY_S0_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCB3_DEVICE_MEMORY_S0_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCB3_DEVICE_MEMORY_S0_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
if (IsSlaveSocketActive ()) {
// Slave socket exist
+
/*
* - PCIe RCA0 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCA0_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCA0_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCA0_DEVICE_MEMORY_S1_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCA0_DEVICE_MEMORY_S1_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCA0_DEVICE_MEMORY_S1_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - PCIe RCA1 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCA1_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCA1_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCA1_DEVICE_MEMORY_S1_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCA1_DEVICE_MEMORY_S1_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCA1_DEVICE_MEMORY_S1_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - PCIe RCA2 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCA2_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCA2_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCA2_DEVICE_MEMORY_S1_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCA2_DEVICE_MEMORY_S1_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCA2_DEVICE_MEMORY_S1_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - PCIe RCA3 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCA3_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCA3_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCA3_DEVICE_MEMORY_S1_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCA3_DEVICE_MEMORY_S1_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCA3_DEVICE_MEMORY_S1_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - PCIe RCB0 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCB0_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCB0_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCB0_DEVICE_MEMORY_S1_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCB0_DEVICE_MEMORY_S1_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCB0_DEVICE_MEMORY_S1_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - PCIe RCB1 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCB1_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCB1_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCB1_DEVICE_MEMORY_S1_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCB1_DEVICE_MEMORY_S1_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCB1_DEVICE_MEMORY_S1_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - PCIe RCB2 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCB2_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCB2_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCB2_DEVICE_MEMORY_S1_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCB2_DEVICE_MEMORY_S1_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCB2_DEVICE_MEMORY_S1_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - PCIe RCB3 Device memory
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_RCB3_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_RCB3_DEVICE_MEMORY_S1_BASE;
- VirtualMemoryTable[Index].Length = AC01_RCB3_DEVICE_MEMORY_S1_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_RCB3_DEVICE_MEMORY_S1_BASE;
+ VirtualMemoryTable[Index].Length = AC01_RCB3_DEVICE_MEMORY_S1_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
}
/*
* - BERT memory region
*/
VirtualMemoryTable[++Index].PhysicalBase = AC01_BERT_MEMORY_BASE;
- VirtualMemoryTable[Index].VirtualBase = AC01_BERT_MEMORY_BASE;
- VirtualMemoryTable[Index].Length = AC01_BERT_MEMORY_SIZE;
- VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ VirtualMemoryTable[Index].VirtualBase = AC01_BERT_MEMORY_BASE;
+ VirtualMemoryTable[Index].Length = AC01_BERT_MEMORY_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
/*
* - DDR memory region
*/
NumRegion = PlatformHob->DramInfo.NumRegion;
- Count = 0;
+ Count = 0;
while (NumRegion-- > 0) {
- if (PlatformHob->DramInfo.NvdRegion[Count]) { /* Skip NVDIMM Region */
+ if (PlatformHob->DramInfo.NvdRegion[Count]) {
+ /* Skip NVDIMM Region */
Count++;
continue;
}
VirtualMemoryTable[++Index].PhysicalBase = PlatformHob->DramInfo.Base[Count];
- VirtualMemoryTable[Index].VirtualBase = PlatformHob->DramInfo.Base[Count];
- VirtualMemoryTable[Index].Length = PlatformHob->DramInfo.Size[Count];
- VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
+ VirtualMemoryTable[Index].VirtualBase = PlatformHob->DramInfo.Base[Count];
+ VirtualMemoryTable[Index].Length = PlatformHob->DramInfo.Size[Count];
+ VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
if (PlatformHob->DramInfo.Base[Count] == PcdGet64 (PcdMmBufferBase)) {
//
// Set uncached attribute for MM region
//
- VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_UNCACHED;
+ VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_UNCACHED;
}
+
Count++;
}
/* End of Table */
VirtualMemoryTable[++Index].PhysicalBase = 0;
- VirtualMemoryTable[Index].VirtualBase = 0;
- VirtualMemoryTable[Index].Length = 0;
- VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
ASSERT ((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/PlatformMemoryMap.h b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/PlatformMemoryMap.h index 23b52653f3..11cba0dfb4 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/PlatformMemoryMap.h +++ b/Silicon/Ampere/AmpereAltraPkg/Library/ArmPlatformLib/PlatformMemoryMap.h @@ -9,127 +9,127 @@ #ifndef PLATFORM_MEMORY_MAP_H_
#define PLATFORM_MEMORY_MAP_H_
-//*******************************************************************
+// *******************************************************************
// Platform Memory Map
-//*******************************************************************
+// *******************************************************************
//
// Device Memory (Socket 0)
//
-#define AC01_DEVICE_MEMORY_S0_BASE 0x100000000000ULL
-#define AC01_DEVICE_MEMORY_S0_SIZE 0x102000000ULL
+#define AC01_DEVICE_MEMORY_S0_BASE 0x100000000000ULL
+#define AC01_DEVICE_MEMORY_S0_SIZE 0x102000000ULL
//
// Device Memory (Socket 1)
//
-#define AC01_DEVICE_MEMORY_S1_BASE 0x500000000000ULL
-#define AC01_DEVICE_MEMORY_S1_SIZE 0x101000000ULL
+#define AC01_DEVICE_MEMORY_S1_BASE 0x500000000000ULL
+#define AC01_DEVICE_MEMORY_S1_SIZE 0x101000000ULL
//
// BERT memory
//
-#define AC01_BERT_MEMORY_BASE 0x88230000ULL
-#define AC01_BERT_MEMORY_SIZE 0x50000ULL
+#define AC01_BERT_MEMORY_BASE 0x88230000ULL
+#define AC01_BERT_MEMORY_SIZE 0x50000ULL
-//*******************************************************************
+// *******************************************************************
// Socket 0 PCIe Device Memory
-//*******************************************************************
+// *******************************************************************
//
// PCIe RCA0 Device memory
//
-#define AC01_RCA0_DEVICE_MEMORY_S0_BASE 0x33FFE0000000ULL
-#define AC01_RCA0_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
+#define AC01_RCA0_DEVICE_MEMORY_S0_BASE 0x33FFE0000000ULL
+#define AC01_RCA0_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
//
// PCIe RCA1 Device memory
//
-#define AC01_RCA1_DEVICE_MEMORY_S0_BASE 0x37FFE0000000ULL
-#define AC01_RCA1_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
+#define AC01_RCA1_DEVICE_MEMORY_S0_BASE 0x37FFE0000000ULL
+#define AC01_RCA1_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
//
// PCIe RCA2 Device memory
//
-#define AC01_RCA2_DEVICE_MEMORY_S0_BASE 0x3BFFE0000000ULL
-#define AC01_RCA2_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
+#define AC01_RCA2_DEVICE_MEMORY_S0_BASE 0x3BFFE0000000ULL
+#define AC01_RCA2_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
//
// PCIe RCA3 Device memory
//
-#define AC01_RCA3_DEVICE_MEMORY_S0_BASE 0x3FFFE0000000ULL
-#define AC01_RCA3_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
+#define AC01_RCA3_DEVICE_MEMORY_S0_BASE 0x3FFFE0000000ULL
+#define AC01_RCA3_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
//
// PCIe RCB0 Device memory
//
-#define AC01_RCB0_DEVICE_MEMORY_S0_BASE 0x23FFE0000000ULL
-#define AC01_RCB0_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
+#define AC01_RCB0_DEVICE_MEMORY_S0_BASE 0x23FFE0000000ULL
+#define AC01_RCB0_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
//
// PCIe RCB1 Device memory
//
-#define AC01_RCB1_DEVICE_MEMORY_S0_BASE 0x27FFE0000000ULL
-#define AC01_RCB1_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
+#define AC01_RCB1_DEVICE_MEMORY_S0_BASE 0x27FFE0000000ULL
+#define AC01_RCB1_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
//
// PCIe RCB2 Device memory
//
-#define AC01_RCB2_DEVICE_MEMORY_S0_BASE 0x2BFFE0000000ULL
-#define AC01_RCB2_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
+#define AC01_RCB2_DEVICE_MEMORY_S0_BASE 0x2BFFE0000000ULL
+#define AC01_RCB2_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
//
// PCIe RCB3 Device memory
//
-#define AC01_RCB3_DEVICE_MEMORY_S0_BASE 0x2FFFE0000000ULL
-#define AC01_RCB3_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
+#define AC01_RCB3_DEVICE_MEMORY_S0_BASE 0x2FFFE0000000ULL
+#define AC01_RCB3_DEVICE_MEMORY_S0_SIZE 0x000020000000ULL
-//*******************************************************************
+// *******************************************************************
// Socket 1 PCIe Device Memory
-//*******************************************************************
+// *******************************************************************
//
// PCIe RCA0 Device memory
//
-#define AC01_RCA0_DEVICE_MEMORY_S1_BASE 0x73FFE0000000ULL
-#define AC01_RCA0_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
+#define AC01_RCA0_DEVICE_MEMORY_S1_BASE 0x73FFE0000000ULL
+#define AC01_RCA0_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
//
// PCIe RCA1 Device memory
//
-#define AC01_RCA1_DEVICE_MEMORY_S1_BASE 0x77FFE0000000ULL
-#define AC01_RCA1_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
+#define AC01_RCA1_DEVICE_MEMORY_S1_BASE 0x77FFE0000000ULL
+#define AC01_RCA1_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
//
// PCIe RCA2 Device memory
//
-#define AC01_RCA2_DEVICE_MEMORY_S1_BASE 0x7BFFE0000000ULL
-#define AC01_RCA2_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
+#define AC01_RCA2_DEVICE_MEMORY_S1_BASE 0x7BFFE0000000ULL
+#define AC01_RCA2_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
//
// PCIe RCA3 Device memory
//
-#define AC01_RCA3_DEVICE_MEMORY_S1_BASE 0x7FFFE0000000ULL
-#define AC01_RCA3_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
+#define AC01_RCA3_DEVICE_MEMORY_S1_BASE 0x7FFFE0000000ULL
+#define AC01_RCA3_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
//
// PCIe RCB0 Device memory
//
-#define AC01_RCB0_DEVICE_MEMORY_S1_BASE 0x63FFE0000000ULL
-#define AC01_RCB0_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
+#define AC01_RCB0_DEVICE_MEMORY_S1_BASE 0x63FFE0000000ULL
+#define AC01_RCB0_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
//
// PCIe RCB1 Device memory
//
-#define AC01_RCB1_DEVICE_MEMORY_S1_BASE 0x67FFE0000000ULL
-#define AC01_RCB1_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
+#define AC01_RCB1_DEVICE_MEMORY_S1_BASE 0x67FFE0000000ULL
+#define AC01_RCB1_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
//
// PCIe RCB2 Device memory
//
-#define AC01_RCB2_DEVICE_MEMORY_S1_BASE 0x6BFFE0000000ULL
-#define AC01_RCB2_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
+#define AC01_RCB2_DEVICE_MEMORY_S1_BASE 0x6BFFE0000000ULL
+#define AC01_RCB2_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
//
// PCIe RCB3 Device memory
//
-#define AC01_RCB3_DEVICE_MEMORY_S1_BASE 0x6FFFE0000000ULL
-#define AC01_RCB3_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
+#define AC01_RCB3_DEVICE_MEMORY_S1_BASE 0x6FFFE0000000ULL
+#define AC01_RCB3_DEVICE_MEMORY_S1_SIZE 0x000020000000ULL
#endif /* PLATFORM_MEMORY_MAP_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/BoardPcieLibNull/BoardPcieLibNull.c b/Silicon/Ampere/AmpereAltraPkg/Library/BoardPcieLibNull/BoardPcieLibNull.c index 0916adb775..3ecdfbd86f 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/BoardPcieLibNull/BoardPcieLibNull.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/BoardPcieLibNull/BoardPcieLibNull.c @@ -22,9 +22,9 @@ RETURN_STATUS
EFIAPI
BoardPcieAssertPerst (
- IN AC01_ROOT_COMPLEX *RootComplex,
- IN UINT8 PcieIndex,
- IN BOOLEAN IsPullToHigh
+ IN AC01_ROOT_COMPLEX *RootComplex,
+ IN UINT8 PcieIndex,
+ IN BOOLEAN IsPullToHigh
)
{
return RETURN_SUCCESS;
@@ -40,7 +40,7 @@ BoardPcieAssertPerst ( **/
UINT16
BoardPcieGetSegmentNumber (
- IN AC01_ROOT_COMPLEX *RootComplex
+ IN AC01_ROOT_COMPLEX *RootComplex
)
{
return 0x0F;
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/DwGpioLib/DwGpioLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/DwGpioLib/DwGpioLib.c index 319ce43ba7..44064ce7e4 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/DwGpioLib/DwGpioLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/DwGpioLib/DwGpioLib.c @@ -19,32 +19,32 @@ #include <Platform/Ac01.h>
/* Runtime needs to be 64K alignment */
-#define RUNTIME_ADDRESS_MASK (~(SIZE_64KB - 1))
-#define RUNTIME_ADDRESS_LENGTH SIZE_64KB
+#define RUNTIME_ADDRESS_MASK (~(SIZE_64KB - 1))
+#define RUNTIME_ADDRESS_LENGTH SIZE_64KB
-#define GPIO_MUX_VAL(Gpio) (0x00000001 << (Gpio))
-#define GPIO_IN 0
-#define GPIO_OUT 1
+#define GPIO_MUX_VAL(Gpio) (0x00000001 << (Gpio))
+#define GPIO_IN 0
+#define GPIO_OUT 1
/* Address GPIO_REG Registers */
-#define GPIO_SWPORTA_DR_ADDR 0x00000000
-#define GPIO_SWPORTA_DDR_ADDR 0x00000004
-#define GPIO_EXT_PORTA_ADDR 0x00000050
+#define GPIO_SWPORTA_DR_ADDR 0x00000000
+#define GPIO_SWPORTA_DDR_ADDR 0x00000004
+#define GPIO_EXT_PORTA_ADDR 0x00000050
-STATIC UINT64 GpioBaseAddr[] = { AC01_GPIO_BASE_ADDRESS_LIST };
-STATIC UINT64 GpiBaseAddr[] = { AC01_GPI_BASE_ADDRESS_LIST };
-STATIC BOOLEAN GpioRuntimeEnableArray[sizeof (GpioBaseAddr) / sizeof (GpioBaseAddr[0])] = { FALSE };
-STATIC EFI_EVENT mVirtualAddressChangeEvent = NULL;
+STATIC UINT64 GpioBaseAddr[] = { AC01_GPIO_BASE_ADDRESS_LIST };
+STATIC UINT64 GpiBaseAddr[] = { AC01_GPI_BASE_ADDRESS_LIST };
+STATIC BOOLEAN GpioRuntimeEnableArray[sizeof (GpioBaseAddr) / sizeof (GpioBaseAddr[0])] = { FALSE };
+STATIC EFI_EVENT mVirtualAddressChangeEvent = NULL;
UINT64
GetBaseAddr (
- IN UINT32 Pin
+ IN UINT32 Pin
)
{
- UINT32 NumberOfControllers = sizeof (GpioBaseAddr) / sizeof (GpioBaseAddr[0]);
- UINT32 TotalPins = AC01_GPIO_PINS_PER_CONTROLLER * NumberOfControllers;
+ UINT32 NumberOfControllers = sizeof (GpioBaseAddr) / sizeof (GpioBaseAddr[0]);
+ UINT32 TotalPins = AC01_GPIO_PINS_PER_CONTROLLER * NumberOfControllers;
- if (NumberOfControllers == 0 || Pin >= TotalPins) {
+ if ((NumberOfControllers == 0) || (Pin >= TotalPins)) {
return 0;
}
@@ -53,8 +53,8 @@ GetBaseAddr ( VOID
GpioWrite (
- IN UINT64 Base,
- IN UINT32 Val
+ IN UINT64 Base,
+ IN UINT32 Val
)
{
MmioWrite32 ((UINTN)Base, Val);
@@ -62,8 +62,8 @@ GpioWrite ( VOID
GpioRead (
- IN UINT64 Base,
- OUT UINT32 *Val
+ IN UINT64 Base,
+ OUT UINT32 *Val
)
{
ASSERT (Val != NULL);
@@ -73,13 +73,13 @@ GpioRead ( VOID
EFIAPI
GpioWriteBit (
- IN UINT32 Pin,
- IN UINT32 Val
+ IN UINT32 Pin,
+ IN UINT32 Val
)
{
- UINT64 Reg;
- UINT32 GpioPin;
- UINT32 ReadVal;
+ UINT64 Reg;
+ UINT32 GpioPin;
+ UINT32 ReadVal;
Reg = GetBaseAddr (Pin);
if (Reg == 0) {
@@ -101,14 +101,14 @@ GpioWriteBit ( UINTN
EFIAPI
GpioReadBit (
- IN UINT32 Pin
+ IN UINT32 Pin
)
{
- UINT64 Reg;
- UINT32 Val;
- UINT32 GpioPin;
- UINT8 Index;
- UINT32 MaxIndex;
+ UINT64 Reg;
+ UINT32 Val;
+ UINT32 GpioPin;
+ UINT8 Index;
+ UINT32 MaxIndex;
Reg = GetBaseAddr (Pin);
if (Reg == 0) {
@@ -124,6 +124,7 @@ GpioReadBit ( break;
}
}
+
if (Index == MaxIndex) {
/* Only GPIO has GPIO_EXT_PORTA register, not for GPI */
Reg += GPIO_EXT_PORTA_ADDR;
@@ -136,13 +137,13 @@ GpioReadBit ( EFI_STATUS
GpioConfig (
- IN UINT32 Pin,
- IN UINT32 InOut
+ IN UINT32 Pin,
+ IN UINT32 InOut
)
{
- INTN GpioPin;
- UINT32 Val;
- UINT64 Reg;
+ INTN GpioPin;
+ UINT32 Val;
+ UINT64 Reg;
/*
* Caculate GPIO Pin Number for Direction Register
@@ -155,7 +156,7 @@ GpioConfig ( return EFI_UNSUPPORTED;
}
- Reg += GPIO_SWPORTA_DDR_ADDR;
+ Reg += GPIO_SWPORTA_DDR_ADDR;
GpioPin = Pin % AC01_GPIO_PINS_PER_CONTROLLER;
GpioRead (Reg, &Val);
@@ -164,6 +165,7 @@ GpioConfig ( } else {
Val &= ~GPIO_MUX_VAL (GpioPin);
}
+
GpioWrite (Reg, Val);
return EFI_SUCCESS;
@@ -172,58 +174,58 @@ GpioConfig ( EFI_STATUS
EFIAPI
GpioModeConfig (
- UINT8 Pin,
- GPIO_CONFIG_MODE Mode
+ UINT8 Pin,
+ GPIO_CONFIG_MODE Mode
)
{
- UINT32 NumberOfControllers = sizeof (GpioBaseAddr) / sizeof (UINT64);
- UINT32 NumersOfPins = NumberOfControllers * AC01_GPIO_PINS_PER_CONTROLLER;
- UINT32 Delay = 10;
-
- if (Mode < GpioConfigOutLow
- || Mode >= MaxGpioConfigMode
- || Pin > NumersOfPins - 1
- || Pin < 0)
+ UINT32 NumberOfControllers = sizeof (GpioBaseAddr) / sizeof (UINT64);
+ UINT32 NumersOfPins = NumberOfControllers * AC01_GPIO_PINS_PER_CONTROLLER;
+ UINT32 Delay = 10;
+
+ if ( (Mode < GpioConfigOutLow)
+ || (Mode >= MaxGpioConfigMode)
+ || (Pin > NumersOfPins - 1)
+ || (Pin < 0))
{
return EFI_INVALID_PARAMETER;
}
switch (Mode) {
- case GpioConfigOutLow:
- GpioConfig (Pin, GPIO_OUT);
- GpioWriteBit (Pin, 0);
- DEBUG ((DEBUG_INFO, "GPIO pin %d configured as output low\n", Pin));
- break;
-
- case GpioConfigOutHigh:
- GpioConfig (Pin, GPIO_OUT);
- GpioWriteBit (Pin, 1);
- DEBUG ((DEBUG_INFO, "GPIO pin %d configured as output high\n", Pin));
- break;
-
- case GpioConfigOutLowToHigh:
- GpioConfig (Pin, GPIO_OUT);
- GpioWriteBit (Pin, 0);
- MicroSecondDelay (1000 * Delay);
- GpioWriteBit (Pin, 1);
- DEBUG ((DEBUG_INFO, "GPIO pin %d configured as output low->high\n", Pin));
- break;
-
- case GpioConfigOutHightToLow:
- GpioConfig (Pin, GPIO_OUT);
- GpioWriteBit (Pin, 1);
- MicroSecondDelay (1000 * Delay);
- GpioWriteBit (Pin, 0);
- DEBUG ((DEBUG_INFO, "GPIO pin %d configured as output high->low\n", Pin));
- break;
-
- case GpioConfigIn:
- GpioConfig (Pin, GPIO_IN);
- DEBUG ((DEBUG_INFO, "GPIO pin %d configured as input\n", Pin));
- break;
-
- default:
- break;
+ case GpioConfigOutLow:
+ GpioConfig (Pin, GPIO_OUT);
+ GpioWriteBit (Pin, 0);
+ DEBUG ((DEBUG_INFO, "GPIO pin %d configured as output low\n", Pin));
+ break;
+
+ case GpioConfigOutHigh:
+ GpioConfig (Pin, GPIO_OUT);
+ GpioWriteBit (Pin, 1);
+ DEBUG ((DEBUG_INFO, "GPIO pin %d configured as output high\n", Pin));
+ break;
+
+ case GpioConfigOutLowToHigh:
+ GpioConfig (Pin, GPIO_OUT);
+ GpioWriteBit (Pin, 0);
+ MicroSecondDelay (1000 * Delay);
+ GpioWriteBit (Pin, 1);
+ DEBUG ((DEBUG_INFO, "GPIO pin %d configured as output low->high\n", Pin));
+ break;
+
+ case GpioConfigOutHightToLow:
+ GpioConfig (Pin, GPIO_OUT);
+ GpioWriteBit (Pin, 1);
+ MicroSecondDelay (1000 * Delay);
+ GpioWriteBit (Pin, 0);
+ DEBUG ((DEBUG_INFO, "GPIO pin %d configured as output high->low\n", Pin));
+ break;
+
+ case GpioConfigIn:
+ GpioConfig (Pin, GPIO_IN);
+ DEBUG ((DEBUG_INFO, "GPIO pin %d configured as input\n", Pin));
+ break;
+
+ default:
+ break;
}
return EFI_SUCCESS;
@@ -241,17 +243,18 @@ GpioModeConfig ( VOID
EFIAPI
GpioVirtualAddressChangeEvent (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- UINTN Count;
+ UINTN Count;
EfiConvertPointer (0x0, (VOID **)&GpioBaseAddr);
for (Count = 0; Count < sizeof (GpioBaseAddr) / sizeof (GpioBaseAddr[0]); Count++) {
if (!GpioRuntimeEnableArray[Count]) {
continue;
}
+
EfiConvertPointer (0x0, (VOID **)&GpioBaseAddr[Count]);
}
}
@@ -266,11 +269,11 @@ GpioVirtualAddressChangeEvent ( EFI_STATUS
EFIAPI
GpioSetupRuntime (
- IN UINT32 Pin
+ IN UINT32 Pin
)
{
- EFI_STATUS Status;
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
+ EFI_STATUS Status;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
if (GetBaseAddr (Pin) == 0) {
return EFI_INVALID_PARAMETER;
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/DwI2cLib/DwI2cLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/DwI2cLib/DwI2cLib.c index 2bdd60b12f..389389cd6e 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/DwI2cLib/DwI2cLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/DwI2cLib/DwI2cLib.c @@ -19,13 +19,13 @@ #include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeLib.h>
-#define I2cSync() { asm volatile ("dmb ish" : : : "memory"); }
+#define I2cSync() { asm volatile ("dmb ish" : : : "memory"); }
//
// Runtime needs to be 64K alignment
//
-#define RUNTIME_ADDRESS_MASK (~(SIZE_64KB - 1))
-#define RUNTIME_ADDRESS_LENGTH SIZE_64KB
+#define RUNTIME_ADDRESS_MASK (~(SIZE_64KB - 1))
+#define RUNTIME_ADDRESS_LENGTH SIZE_64KB
//
// Private I2C bus data
@@ -49,7 +49,7 @@ typedef enum { I2cSpeedModeFast,
} I2C_SPEED_MODE;
-#define DW_I2C_MAXIMUM_SPEED_HZ 400000
+#define DW_I2C_MAXIMUM_SPEED_HZ 400000
typedef enum {
I2cSclSpkLen = 0,
@@ -57,91 +57,91 @@ typedef enum { I2cSclLcnt,
} I2C_SCL_PARAM;
-STATIC UINT32 I2cSclParam[][3] = {
+STATIC UINT32 I2cSclParam[][3] = {
/* SPK_LEN, HCNT, LCNT */
- [I2cSpeedModeStandard] = { 10, 0x3E2, 0x47D }, // SS (Standard Speed)
- [I2cSpeedModeFast] = { 10, 0xA4, 0x13F }, // FS (Fast Speed)
+ [I2cSpeedModeStandard] = { 10, 0x3E2, 0x47D }, // SS (Standard Speed)
+ [I2cSpeedModeFast] = { 10, 0xA4, 0x13F }, // FS (Fast Speed)
};
-STATIC BOOLEAN mI2cRuntimeEnableArray[AC01_I2C_MAX_BUS_NUM] = {FALSE};
-STATIC UINTN mI2cBaseArray[AC01_I2C_MAX_BUS_NUM] = {AC01_I2C_BASE_ADDRESS_LIST};
-STATIC DW_I2C_CONTEXT_T mI2cBusList[AC01_I2C_MAX_BUS_NUM];
-STATIC UINTN mI2cClock = 0;
-STATIC EFI_EVENT mVirtualAddressChangeEvent = NULL;
+STATIC BOOLEAN mI2cRuntimeEnableArray[AC01_I2C_MAX_BUS_NUM] = { FALSE };
+STATIC UINTN mI2cBaseArray[AC01_I2C_MAX_BUS_NUM] = { AC01_I2C_BASE_ADDRESS_LIST };
+STATIC DW_I2C_CONTEXT_T mI2cBusList[AC01_I2C_MAX_BUS_NUM];
+STATIC UINTN mI2cClock = 0;
+STATIC EFI_EVENT mVirtualAddressChangeEvent = NULL;
//
// Registers
//
-#define DW_IC_CON 0x0
-#define DW_IC_CON_MASTER BIT0
-#define DW_IC_CON_SPEED_STD BIT1
-#define DW_IC_CON_SPEED_FAST BIT2
-#define DW_IC_CON_10BITADDR_MASTER BIT4
-#define DW_IC_CON_RESTART_EN BIT5
-#define DW_IC_CON_SLAVE_DISABLE BIT6
-#define DW_IC_TAR 0x4
-#define DW_IC_TAR_10BITS BIT12
-#define DW_IC_SAR 0x8
-#define DW_IC_DATA_CMD 0x10
-#define DW_IC_DATA_CMD_RESTART BIT10
-#define DW_IC_DATA_CMD_STOP BIT9
-#define DW_IC_DATA_CMD_CMD BIT8
-#define DW_IC_DATA_CMD_DAT_MASK 0xFF
-#define DW_IC_SS_SCL_HCNT 0x14
-#define DW_IC_SS_SCL_LCNT 0x18
-#define DW_IC_FS_SCL_HCNT 0x1c
-#define DW_IC_FS_SCL_LCNT 0x20
-#define DW_IC_HS_SCL_HCNT 0x24
-#define DW_IC_HS_SCL_LCNT 0x28
-#define DW_IC_INTR_STAT 0x2c
-#define DW_IC_INTR_MASK 0x30
-#define DW_IC_INTR_RX_UNDER BIT0
-#define DW_IC_INTR_RX_OVER BIT1
-#define DW_IC_INTR_RX_FULL BIT2
-#define DW_IC_INTR_TX_EMPTY BIT4
-#define DW_IC_INTR_TX_ABRT BIT6
-#define DW_IC_INTR_ACTIVITY BIT8
-#define DW_IC_INTR_STOP_DET BIT9
-#define DW_IC_INTR_START_DET BIT10
+#define DW_IC_CON 0x0
+#define DW_IC_CON_MASTER BIT0
+#define DW_IC_CON_SPEED_STD BIT1
+#define DW_IC_CON_SPEED_FAST BIT2
+#define DW_IC_CON_10BITADDR_MASTER BIT4
+#define DW_IC_CON_RESTART_EN BIT5
+#define DW_IC_CON_SLAVE_DISABLE BIT6
+#define DW_IC_TAR 0x4
+#define DW_IC_TAR_10BITS BIT12
+#define DW_IC_SAR 0x8
+#define DW_IC_DATA_CMD 0x10
+#define DW_IC_DATA_CMD_RESTART BIT10
+#define DW_IC_DATA_CMD_STOP BIT9
+#define DW_IC_DATA_CMD_CMD BIT8
+#define DW_IC_DATA_CMD_DAT_MASK 0xFF
+#define DW_IC_SS_SCL_HCNT 0x14
+#define DW_IC_SS_SCL_LCNT 0x18
+#define DW_IC_FS_SCL_HCNT 0x1c
+#define DW_IC_FS_SCL_LCNT 0x20
+#define DW_IC_HS_SCL_HCNT 0x24
+#define DW_IC_HS_SCL_LCNT 0x28
+#define DW_IC_INTR_STAT 0x2c
+#define DW_IC_INTR_MASK 0x30
+#define DW_IC_INTR_RX_UNDER BIT0
+#define DW_IC_INTR_RX_OVER BIT1
+#define DW_IC_INTR_RX_FULL BIT2
+#define DW_IC_INTR_TX_EMPTY BIT4
+#define DW_IC_INTR_TX_ABRT BIT6
+#define DW_IC_INTR_ACTIVITY BIT8
+#define DW_IC_INTR_STOP_DET BIT9
+#define DW_IC_INTR_START_DET BIT10
#define DW_IC_ERR_CONDITION \
(DW_IC_INTR_RX_UNDER | DW_IC_INTR_RX_OVER | DW_IC_INTR_TX_ABRT)
-#define DW_IC_RAW_INTR_STAT 0x34
-#define DW_IC_CLR_INTR 0x40
-#define DW_IC_CLR_RX_UNDER 0x44
-#define DW_IC_CLR_RX_OVER 0x48
-#define DW_IC_CLR_TX_ABRT 0x54
-#define DW_IC_CLR_ACTIVITY 0x5c
-#define DW_IC_CLR_STOP_DET 0x60
-#define DW_IC_CLR_START_DET 0x64
-#define DW_IC_ENABLE 0x6c
-#define DW_IC_STATUS 0x70
-#define DW_IC_STATUS_ACTIVITY BIT0
-#define DW_IC_STATUS_TFE BIT2
-#define DW_IC_STATUS_RFNE BIT3
-#define DW_IC_STATUS_MST_ACTIVITY BIT5
-#define DW_IC_TXFLR 0x74
-#define DW_IC_RXFLR 0x78
-#define DW_IC_SDA_HOLD 0x7c
-#define DW_IC_TX_ABRT_SOURCE 0x80
-#define DW_IC_ENABLE_STATUS 0x9c
-#define DW_IC_COMP_PARAM_1 0xf4
+#define DW_IC_RAW_INTR_STAT 0x34
+#define DW_IC_CLR_INTR 0x40
+#define DW_IC_CLR_RX_UNDER 0x44
+#define DW_IC_CLR_RX_OVER 0x48
+#define DW_IC_CLR_TX_ABRT 0x54
+#define DW_IC_CLR_ACTIVITY 0x5c
+#define DW_IC_CLR_STOP_DET 0x60
+#define DW_IC_CLR_START_DET 0x64
+#define DW_IC_ENABLE 0x6c
+#define DW_IC_STATUS 0x70
+#define DW_IC_STATUS_ACTIVITY BIT0
+#define DW_IC_STATUS_TFE BIT2
+#define DW_IC_STATUS_RFNE BIT3
+#define DW_IC_STATUS_MST_ACTIVITY BIT5
+#define DW_IC_TXFLR 0x74
+#define DW_IC_RXFLR 0x78
+#define DW_IC_SDA_HOLD 0x7c
+#define DW_IC_TX_ABRT_SOURCE 0x80
+#define DW_IC_ENABLE_STATUS 0x9c
+#define DW_IC_COMP_PARAM_1 0xf4
#define DW_IC_COMP_PARAM_1_RX_BUFFER_DEPTH(x) \
((((x) >> 8) & 0xFF) + 1)
#define DW_IC_COMP_PARAM_1_TX_BUFFER_DEPTH(x) \
((((x) >> 16) & 0xFF) + 1)
-#define DW_IC_COMP_TYPE 0xfc
-#define SB_DW_IC_CON 0xa8
-#define SB_DW_IC_SCL_TMO_CNT 0xac
-#define SB_DW_IC_RX_PEC 0xb0
-#define SB_DW_IC_ACK 0xb4
-#define SB_DW_IC_FLG 0xb8
-#define SB_DW_IC_FLG_CLR 0xbc
-#define SB_DW_IC_INTR_STAT 0xc0
-#define SB_DW_IC_INTR_STAT_MASK 0xc4
-#define SB_DW_IC_DEBUG_SEL 0xec
-#define SB_DW_IC_ACK_DEBUG 0xf0
-#define DW_IC_FS_SPKLEN 0xa0
-#define DW_IC_HS_SPKLEN 0xa4
+#define DW_IC_COMP_TYPE 0xfc
+#define SB_DW_IC_CON 0xa8
+#define SB_DW_IC_SCL_TMO_CNT 0xac
+#define SB_DW_IC_RX_PEC 0xb0
+#define SB_DW_IC_ACK 0xb4
+#define SB_DW_IC_FLG 0xb8
+#define SB_DW_IC_FLG_CLR 0xbc
+#define SB_DW_IC_INTR_STAT 0xc0
+#define SB_DW_IC_INTR_STAT_MASK 0xc4
+#define SB_DW_IC_DEBUG_SEL 0xec
+#define SB_DW_IC_ACK_DEBUG 0xf0
+#define DW_IC_FS_SPKLEN 0xa0
+#define DW_IC_HS_SPKLEN 0xa4
//
// Timeout interval
@@ -149,37 +149,39 @@ STATIC EFI_EVENT mVirtualAddressChangeEvent = NULL; // The interval is equal to the 10 times the signaling period
// for the highest I2C transfer speed used in the system.
//
-#define DW_POLL_INTERVAL_US(x) (10 * (1000000 / (x)))
+#define DW_POLL_INTERVAL_US(x) (10 * (1000000 / (x)))
//
// Maximum timeout count
//
-#define DW_MAX_TRANSFER_POLL_COUNT 100000 // Maximum timeout: 10s
-#define DW_MAX_STATUS_POLL_COUNT 100
+#define DW_MAX_TRANSFER_POLL_COUNT 100000// Maximum timeout: 10s
+#define DW_MAX_STATUS_POLL_COUNT 100
-#define DW_POLL_MST_ACTIVITY_INTERVAL_US 1000 // 1ms
-#define DW_MAX_MST_ACTIVITY_POLL_COUNT 20
+#define DW_POLL_MST_ACTIVITY_INTERVAL_US 1000// 1ms
+#define DW_MAX_MST_ACTIVITY_POLL_COUNT 20
/**
Initialize I2C Bus
**/
VOID
I2cHWInit (
- UINT32 Bus
+ UINT32 Bus
)
{
- UINT32 Param;
+ UINT32 Param;
mI2cBusList[Bus].Base = mI2cBaseArray[Bus];
Param = MmioRead32 (mI2cBusList[Bus].Base + DW_IC_COMP_PARAM_1);
mI2cBusList[Bus].PollingTime = DW_POLL_INTERVAL_US (mI2cBusList[Bus].BusSpeed);
- mI2cBusList[Bus].RxFifo = DW_IC_COMP_PARAM_1_RX_BUFFER_DEPTH (Param);
- mI2cBusList[Bus].TxFifo = DW_IC_COMP_PARAM_1_TX_BUFFER_DEPTH (Param);
- mI2cBusList[Bus].Enabled = 0;
+ mI2cBusList[Bus].RxFifo = DW_IC_COMP_PARAM_1_RX_BUFFER_DEPTH (Param);
+ mI2cBusList[Bus].TxFifo = DW_IC_COMP_PARAM_1_TX_BUFFER_DEPTH (Param);
+ mI2cBusList[Bus].Enabled = 0;
- DEBUG ((DEBUG_VERBOSE, "%a: Bus %d, Rx_Buffer %d, Tx_Buffer %d\n",
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a: Bus %d, Rx_Buffer %d, Tx_Buffer %d\n",
__func__,
Bus,
mI2cBusList[Bus].RxFifo,
@@ -192,15 +194,15 @@ I2cHWInit ( */
VOID
I2cEnable (
- UINT32 Bus,
- UINT32 Enable
+ UINT32 Bus,
+ UINT32 Enable
)
{
- UINT32 I2cStatusCnt;
- UINTN Base;
+ UINT32 I2cStatusCnt;
+ UINTN Base;
- Base = mI2cBusList[Bus].Base;
- I2cStatusCnt = DW_MAX_STATUS_POLL_COUNT;
+ Base = mI2cBusList[Bus].Base;
+ I2cStatusCnt = DW_MAX_STATUS_POLL_COUNT;
mI2cBusList[Bus].Enabled = Enable;
MmioWrite32 (Base + DW_IC_ENABLE, Enable);
@@ -209,6 +211,7 @@ I2cEnable ( if ((MmioRead32 (Base + DW_IC_ENABLE_STATUS) & 0x01) == Enable) {
break;
}
+
MicroSecondDelay (mI2cBusList[Bus].PollingTime);
} while (I2cStatusCnt-- != 0);
@@ -228,14 +231,14 @@ I2cEnable ( **/
VOID
I2cSetSlaveAddr (
- UINT32 Bus,
- UINT32 SlaveAddr
+ UINT32 Bus,
+ UINT32 SlaveAddr
)
{
- UINTN Base;
- UINT32 OldEnableStatus;
+ UINTN Base;
+ UINT32 OldEnableStatus;
- Base = mI2cBusList[Bus].Base;
+ Base = mI2cBusList[Bus].Base;
OldEnableStatus = mI2cBusList[Bus].Enabled;
I2cEnable (Bus, 0);
@@ -250,18 +253,20 @@ I2cSetSlaveAddr ( **/
UINT32
I2cCheckErrors (
- UINT32 Bus
+ UINT32 Bus
)
{
- UINTN Base;
- UINT32 ErrorStatus;
+ UINTN Base;
+ UINT32 ErrorStatus;
Base = mI2cBusList[Bus].Base;
ErrorStatus = MmioRead32 (Base + DW_IC_RAW_INTR_STAT) & DW_IC_ERR_CONDITION;
if ((ErrorStatus & DW_IC_INTR_RX_UNDER) != 0) {
- DEBUG ((DEBUG_ERROR, "%a: RX_UNDER error on i2c bus %d error status %08x\n",
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: RX_UNDER error on i2c bus %d error status %08x\n",
__func__,
Bus,
ErrorStatus
@@ -270,7 +275,9 @@ I2cCheckErrors ( }
if ((ErrorStatus & DW_IC_INTR_RX_OVER) != 0) {
- DEBUG ((DEBUG_ERROR, "%a: RX_OVER error on i2c bus %d error status %08x\n",
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: RX_OVER error on i2c bus %d error status %08x\n",
__func__,
Bus,
ErrorStatus
@@ -279,7 +286,9 @@ I2cCheckErrors ( }
if ((ErrorStatus & DW_IC_INTR_TX_ABRT) != 0) {
- DEBUG ((DEBUG_VERBOSE, "%a: TX_ABORT at source %08x\n",
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a: TX_ABORT at source %08x\n",
__func__,
MmioRead32 (Base + DW_IC_TX_ABRT_SOURCE)
));
@@ -294,13 +303,13 @@ I2cCheckErrors ( **/
BOOLEAN
I2cWaitBusNotBusy (
- UINT32 Bus
+ UINT32 Bus
)
{
- UINTN Base;
- UINTN PollCount;
+ UINTN Base;
+ UINTN PollCount;
- Base = mI2cBusList[Bus].Base;
+ Base = mI2cBusList[Bus].Base;
PollCount = DW_MAX_MST_ACTIVITY_POLL_COUNT;
while ((MmioRead32 (Base + DW_IC_STATUS) & DW_IC_STATUS_MST_ACTIVITY) != 0) {
@@ -308,7 +317,9 @@ I2cWaitBusNotBusy ( DEBUG ((DEBUG_VERBOSE, "%a: Timeout while waiting for bus ready\n", __func__));
return FALSE;
}
+
PollCount--;
+
/*
* A delay isn't absolutely necessary.
* But to ensure that we don't hammer the bus constantly,
@@ -325,13 +336,13 @@ I2cWaitBusNotBusy ( **/
EFI_STATUS
I2cWaitTxData (
- UINT32 Bus
+ UINT32 Bus
)
{
- UINTN Base;
- UINTN PollCount;
+ UINTN Base;
+ UINTN PollCount;
- Base = mI2cBusList[Bus].Base;
+ Base = mI2cBusList[Bus].Base;
PollCount = 0;
while (MmioRead32 (Base + DW_IC_TXFLR) == mI2cBusList[Bus].TxFifo) {
@@ -355,13 +366,13 @@ I2cWaitTxData ( **/
EFI_STATUS
I2cWaitRxData (
- UINT32 Bus
+ UINT32 Bus
)
{
- UINTN Base;
- UINTN PollCount;
+ UINTN Base;
+ UINTN PollCount;
- Base = mI2cBusList[Bus].Base;
+ Base = mI2cBusList[Bus].Base;
PollCount = 0;
while ((MmioRead32 (Base + DW_IC_STATUS) & DW_IC_STATUS_RFNE) == 0) {
@@ -387,19 +398,21 @@ I2cWaitRxData ( **/
VOID
I2cSclInit (
- UINT32 Bus,
- UINT32 I2cClkFreq,
- UINT32 I2cSpeed
+ UINT32 Bus,
+ UINT32 I2cClkFreq,
+ UINT32 I2cSpeed
)
{
- UINT16 IcCon;
- UINTN Base;
- UINT32 I2cSpeedKhz;
+ UINT16 IcCon;
+ UINTN Base;
+ UINT32 I2cSpeedKhz;
- Base = mI2cBusList[Bus].Base;
+ Base = mI2cBusList[Bus].Base;
I2cSpeedKhz = I2cSpeed / 1000;
- DEBUG ((DEBUG_VERBOSE, "%a: Bus %d I2cClkFreq %d I2cSpeed %d\n",
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a: Bus %d I2cClkFreq %d I2cSpeed %d\n",
__func__,
Bus,
I2cClkFreq,
@@ -414,13 +427,14 @@ I2cSclInit ( MmioWrite32 (Base + DW_IC_FS_SPKLEN, I2cSclParam[I2cSpeedModeStandard][I2cSclSpkLen]);
MmioWrite32 (Base + DW_IC_SS_SCL_HCNT, I2cSclParam[I2cSpeedModeStandard][I2cSclHcnt]);
MmioWrite32 (Base + DW_IC_SS_SCL_LCNT, I2cSclParam[I2cSpeedModeStandard][I2cSclLcnt]);
- } else if (I2cSpeedKhz > 100 && I2cSpeedKhz <= 400) {
+ } else if ((I2cSpeedKhz > 100) && (I2cSpeedKhz <= 400)) {
IcCon |= DW_IC_CON_SPEED_FAST;
// Fast speed mode
MmioWrite32 (Base + DW_IC_FS_SPKLEN, I2cSclParam[I2cSpeedModeFast][I2cSclSpkLen]);
MmioWrite32 (Base + DW_IC_FS_SCL_HCNT, I2cSclParam[I2cSpeedModeFast][I2cSclHcnt]);
MmioWrite32 (Base + DW_IC_FS_SCL_LCNT, I2cSclParam[I2cSpeedModeFast][I2cSclLcnt]);
}
+
MmioWrite32 (Base + DW_IC_CON, IcCon);
}
@@ -429,11 +443,11 @@ I2cSclInit ( **/
EFI_STATUS
I2cInit (
- UINT32 Bus,
- UINTN BusSpeed
+ UINT32 Bus,
+ UINTN BusSpeed
)
{
- UINTN Base;
+ UINTN Base;
ASSERT (mI2cClock != 0);
@@ -458,13 +472,13 @@ I2cInit ( **/
EFI_STATUS
I2cFinish (
- UINT32 Bus
+ UINT32 Bus
)
{
- UINTN Base;
- UINTN PollCount;
+ UINTN Base;
+ UINTN PollCount;
- Base = mI2cBusList[Bus].Base;
+ Base = mI2cBusList[Bus].Base;
PollCount = 0;
/* Wait for TX FIFO empty */
@@ -472,6 +486,7 @@ I2cFinish ( if ((MmioRead32 (Base + DW_IC_STATUS) & DW_IC_STATUS_TFE) != 0) {
break;
}
+
MicroSecondDelay (mI2cBusList[Bus].PollingTime);
} while (PollCount++ < DW_MAX_TRANSFER_POLL_COUNT);
@@ -487,6 +502,7 @@ I2cFinish ( MmioRead32 (Base + DW_IC_CLR_STOP_DET);
return EFI_SUCCESS;
}
+
MicroSecondDelay (mI2cBusList[Bus].PollingTime);
} while (PollCount++ < DW_MAX_TRANSFER_POLL_COUNT);
@@ -496,19 +512,21 @@ I2cFinish ( EFI_STATUS
InternalI2cWrite (
- UINT32 Bus,
- UINT8 *Buf,
- UINT32 *Length
+ UINT32 Bus,
+ UINT8 *Buf,
+ UINT32 *Length
)
{
- EFI_STATUS Status;
- UINTN WriteCount;
- UINTN Base;
+ EFI_STATUS Status;
+ UINTN WriteCount;
+ UINTN Base;
Status = EFI_SUCCESS;
- Base = mI2cBusList[Bus].Base;
+ Base = mI2cBusList[Bus].Base;
- DEBUG ((DEBUG_VERBOSE, "%a: Write Bus %d Buf %p Length %d\n",
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a: Write Bus %d Buf %p Length %d\n",
__func__,
Bus,
Buf,
@@ -536,6 +554,7 @@ InternalI2cWrite ( Buf[WriteCount] & DW_IC_DATA_CMD_DAT_MASK
);
}
+
I2cSync ();
WriteCount++;
}
@@ -567,9 +586,9 @@ InternalSmbusReadDataLength ( UINT32 *Length
)
{
- EFI_STATUS Status;
- UINTN Base;
- UINT32 CmdSend;
+ EFI_STATUS Status;
+ UINTN Base;
+ UINT32 CmdSend;
Base = mI2cBusList[Bus].Base;
@@ -591,7 +610,8 @@ InternalSmbusReadDataLength ( // the RX FIFO is not ready for reading. Thus, the following message
// serves more as verbose alert rather than an error.
//
- DEBUG ((DEBUG_VERBOSE,
+ DEBUG ((
+ DEBUG_VERBOSE,
"%a: Reading Smbus data length failed to wait data\n",
__func__
));
@@ -618,28 +638,30 @@ InternalSmbusReadDataLength ( EFI_STATUS
InternalI2cRead (
UINT32 Bus,
- UINT8 *BufCmd,
- UINT32 CmdLength,
- UINT8 *Buf,
- UINT32 *Length
+ UINT8 *BufCmd,
+ UINT32 CmdLength,
+ UINT8 *Buf,
+ UINT32 *Length
)
{
- EFI_STATUS Status;
- UINTN Base;
- UINT32 CmdSend;
- UINT32 TxLimit, RxLimit;
- UINTN Idx;
- UINTN Count;
- UINTN ReadCount;
- UINTN WriteCount;
- UINT32 ResponseLen;
-
- Status = EFI_SUCCESS;
- Base = mI2cBusList[Bus].Base;
- Count = 0;
+ EFI_STATUS Status;
+ UINTN Base;
+ UINT32 CmdSend;
+ UINT32 TxLimit, RxLimit;
+ UINTN Idx;
+ UINTN Count;
+ UINTN ReadCount;
+ UINTN WriteCount;
+ UINT32 ResponseLen;
+
+ Status = EFI_SUCCESS;
+ Base = mI2cBusList[Bus].Base;
+ Count = 0;
ReadCount = 0;
- DEBUG ((DEBUG_VERBOSE, "%a: Read Bus %d Buf %p Length:%d\n",
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a: Read Bus %d Buf %p Length:%d\n",
__func__,
Bus,
Buf,
@@ -652,7 +674,7 @@ InternalI2cRead ( WriteCount = 0;
while (CmdLength != 0) {
TxLimit = mI2cBusList[Bus].TxFifo - MmioRead32 (Base + DW_IC_TXFLR);
- Count = CmdLength > TxLimit ? TxLimit : CmdLength;
+ Count = CmdLength > TxLimit ? TxLimit : CmdLength;
for (Idx = 0; Idx < Count; Idx++ ) {
CmdSend = BufCmd[WriteCount++] & DW_IC_DATA_CMD_DAT_MASK;
@@ -663,6 +685,7 @@ InternalI2cRead ( Status = EFI_CRC_ERROR;
goto Exit;
}
+
CmdLength--;
}
@@ -691,7 +714,7 @@ InternalI2cRead ( // Abort the transaction when the requested length is shorter than the actual response data
// or if there is no response data when PEC disabled.
//
- if ((*Length < (ResponseLen + 2)) || (!mI2cBusList[Bus].PecCheck && ResponseLen == 0)) {
+ if ((*Length < (ResponseLen + 2)) || (!mI2cBusList[Bus].PecCheck && (ResponseLen == 0))) {
MmioWrite32 (Base + DW_IC_DATA_CMD, DW_IC_DATA_CMD_CMD | DW_IC_DATA_CMD_STOP);
I2cSync ();
Status = EFI_INVALID_PARAMETER;
@@ -707,21 +730,23 @@ InternalI2cRead ( while ((*Length - ReadCount) != 0) {
TxLimit = mI2cBusList[Bus].TxFifo - MmioRead32 (Base + DW_IC_TXFLR);
RxLimit = mI2cBusList[Bus].RxFifo - MmioRead32 (Base + DW_IC_RXFLR);
- Count = *Length - ReadCount;
- Count = Count > RxLimit ? RxLimit : Count;
- Count = Count > TxLimit ? TxLimit : Count;
+ Count = *Length - ReadCount;
+ Count = Count > RxLimit ? RxLimit : Count;
+ Count = Count > TxLimit ? TxLimit : Count;
for (Idx = 0; Idx < Count; Idx++ ) {
CmdSend = DW_IC_DATA_CMD_CMD;
if (WriteCount == *Length - 1) {
CmdSend |= DW_IC_DATA_CMD_STOP;
}
+
MmioWrite32 (Base + DW_IC_DATA_CMD, CmdSend);
I2cSync ();
WriteCount++;
if (I2cCheckErrors (Bus) != 0) {
- DEBUG ((DEBUG_VERBOSE,
+ DEBUG ((
+ DEBUG_VERBOSE,
"%a: Sending reading command remaining length %d CRC error\n",
__func__,
*Length
@@ -734,7 +759,8 @@ InternalI2cRead ( for (Idx = 0; Idx < Count; Idx++ ) {
Status = I2cWaitRxData (Bus);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_VERBOSE,
+ DEBUG ((
+ DEBUG_VERBOSE,
"%a: Reading remaining length %d failed to wait data\n",
__func__,
*Length
@@ -752,7 +778,9 @@ InternalI2cRead ( I2cSync ();
if (I2cCheckErrors (Bus) != 0) {
- DEBUG ((DEBUG_VERBOSE, "%a: Reading remaining length %d CRC error\n",
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a: Reading remaining length %d CRC error\n",
__func__,
*Length
));
@@ -789,15 +817,15 @@ Exit: EFI_STATUS
EFIAPI
I2cWrite (
- IN UINT32 Bus,
- IN UINT32 SlaveAddr,
- IN OUT UINT8 *Buf,
- IN OUT UINT32 *WriteLength
+ IN UINT32 Bus,
+ IN UINT32 SlaveAddr,
+ IN OUT UINT8 *Buf,
+ IN OUT UINT32 *WriteLength
)
{
- if (Bus >= AC01_I2C_MAX_BUS_NUM
- || Buf == NULL
- || WriteLength == NULL)
+ if ( (Bus >= AC01_I2C_MAX_BUS_NUM)
+ || (Buf == NULL)
+ || (WriteLength == NULL))
{
return EFI_INVALID_PARAMETER;
}
@@ -828,17 +856,17 @@ I2cWrite ( EFI_STATUS
EFIAPI
I2cRead (
- IN UINT32 Bus,
- IN UINT32 SlaveAddr,
- IN UINT8 *BufCmd,
- IN UINT32 CmdLength,
- IN OUT UINT8 *Buf,
- IN OUT UINT32 *ReadLength
+ IN UINT32 Bus,
+ IN UINT32 SlaveAddr,
+ IN UINT8 *BufCmd,
+ IN UINT32 CmdLength,
+ IN OUT UINT8 *Buf,
+ IN OUT UINT32 *ReadLength
)
{
- if (Bus >= AC01_I2C_MAX_BUS_NUM
- || Buf == NULL
- || ReadLength == NULL)
+ if ( (Bus >= AC01_I2C_MAX_BUS_NUM)
+ || (Buf == NULL)
+ || (ReadLength == NULL))
{
return EFI_INVALID_PARAMETER;
}
@@ -870,8 +898,8 @@ I2cProbe ( IN BOOLEAN PecCheck
)
{
- if (Bus >= AC01_I2C_MAX_BUS_NUM
- || BusSpeed > DW_I2C_MAXIMUM_SPEED_HZ)
+ if ( (Bus >= AC01_I2C_MAX_BUS_NUM)
+ || (BusSpeed > DW_I2C_MAXIMUM_SPEED_HZ))
{
return EFI_INVALID_PARAMETER;
}
@@ -894,11 +922,11 @@ I2cProbe ( VOID
EFIAPI
I2cVirtualAddressChangeEvent (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- UINTN Count;
+ UINTN Count;
EfiConvertPointer (0x0, (VOID **)&mI2cBusList);
EfiConvertPointer (0x0, (VOID **)&mI2cBaseArray);
@@ -907,6 +935,7 @@ I2cVirtualAddressChangeEvent ( if (!mI2cRuntimeEnableArray[Count]) {
continue;
}
+
EfiConvertPointer (0x0, (VOID **)&mI2cBaseArray[Count]);
EfiConvertPointer (0x0, (VOID **)&mI2cBusList[Count].Base);
}
@@ -924,11 +953,11 @@ I2cVirtualAddressChangeEvent ( EFI_STATUS
EFIAPI
I2cSetupRuntime (
- IN UINT32 Bus
+ IN UINT32 Bus
)
{
- EFI_STATUS Status;
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
+ EFI_STATUS Status;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
if (Bus >= AC01_I2C_MAX_BUS_NUM) {
return EFI_INVALID_PARAMETER;
@@ -985,8 +1014,9 @@ I2cLibConstructor ( if (Hob == NULL) {
return EFI_NOT_FOUND;
}
+
PlatformHob = (PLATFORM_INFO_HOB *)GET_GUID_HOB_DATA (Hob);
- mI2cClock = PlatformHob->AhbClk;
+ mI2cClock = PlatformHob->AhbClk;
ASSERT (mI2cClock != 0);
return EFI_SUCCESS;
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLib.c index 6c8a79699c..7b92edbb48 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLib.c @@ -27,7 +27,7 @@ FlashLibConstructor ( )
{
gFlashLibPhysicalBuffer = AllocateZeroPool (EFI_MM_MAX_TMP_BUF_SIZE);
- gFlashLibVirtualBuffer = gFlashLibPhysicalBuffer;
+ gFlashLibVirtualBuffer = gFlashLibPhysicalBuffer;
ASSERT (gFlashLibPhysicalBuffer != NULL);
return EFI_SUCCESS;
@@ -48,18 +48,19 @@ FlashLibConstructor ( **/
EFI_STATUS
FlashMmCommunicate (
- IN VOID *Request,
- IN UINT32 RequestDataSize,
- OUT VOID *Response,
- IN UINT32 ResponseDataSize
+ IN VOID *Request,
+ IN UINT32 RequestDataSize,
+ OUT VOID *Response,
+ IN UINT32 ResponseDataSize
)
{
- EFI_MM_COMMUNICATE_REQUEST CommBuffer;
- EFI_STATUS Status;
+ EFI_MM_COMMUNICATE_REQUEST CommBuffer;
+ EFI_STATUS Status;
- if (Request == NULL || RequestDataSize == 0
- || RequestDataSize > EFI_MM_MAX_PAYLOAD_SIZE
- || (ResponseDataSize == 0 && Response == NULL)) {
+ if ( (Request == NULL) || (RequestDataSize == 0)
+ || (RequestDataSize > EFI_MM_MAX_PAYLOAD_SIZE)
+ || ((ResponseDataSize == 0) && (Response == NULL)))
+ {
return EFI_INVALID_PARAMETER;
}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLibCommon.c b/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLibCommon.c index 4dd9d07bf7..4873424e56 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLibCommon.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLibCommon.c @@ -15,8 +15,8 @@ #include "FlashLibCommon.h"
-UINT8 *gFlashLibPhysicalBuffer;
-UINT8 *gFlashLibVirtualBuffer;
+UINT8 *gFlashLibPhysicalBuffer;
+UINT8 *gFlashLibVirtualBuffer;
/**
Convert Virtual Address to Physical Address at Runtime.
@@ -29,8 +29,8 @@ UINT8 *gFlashLibVirtualBuffer; STATIC
UINT8 *
ConvertToPhysicalBuffer (
- IN UINT8 *VirtualPtr,
- IN UINT32 Size
+ IN UINT8 *VirtualPtr,
+ IN UINT32 Size
)
{
ASSERT (VirtualPtr != NULL);
@@ -51,15 +51,15 @@ ConvertToPhysicalBuffer ( EFI_STATUS
EFIAPI
FlashGetFailSafeInfo (
- OUT UINTN *FailSafeBase,
- OUT UINT32 *FailSafeSize
+ OUT UINTN *FailSafeBase,
+ OUT UINT32 *FailSafeSize
)
{
- EFI_MM_COMMUNICATE_FAILSAFE_INFO_RESPONSE FailSafeInfo;
- EFI_STATUS Status;
- UINT64 MmData[5];
+ EFI_MM_COMMUNICATE_FAILSAFE_INFO_RESPONSE FailSafeInfo;
+ EFI_STATUS Status;
+ UINT64 MmData[5];
- if (FailSafeBase == NULL || FailSafeSize == NULL ) {
+ if ((FailSafeBase == NULL) || (FailSafeSize == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -104,15 +104,15 @@ FlashGetFailSafeInfo ( EFI_STATUS
EFIAPI
FlashGetNvRamInfo (
- OUT UINTN *NvRamBase,
- OUT UINT32 *NvRamSize
+ OUT UINTN *NvRamBase,
+ OUT UINT32 *NvRamSize
)
{
- EFI_MM_COMMUNICATE_NVRAM_INFO_RESPONSE NvRamInfo;
- EFI_STATUS Status;
- UINT64 MmData[5];
+ EFI_MM_COMMUNICATE_NVRAM_INFO_RESPONSE NvRamInfo;
+ EFI_STATUS Status;
+ UINT64 MmData[5];
- if (NvRamBase == NULL || NvRamSize == NULL) {
+ if ((NvRamBase == NULL) || (NvRamSize == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -156,15 +156,15 @@ FlashGetNvRamInfo ( EFI_STATUS
EFIAPI
FlashGetNvRam2Info (
- OUT UINTN *NvRam2Base,
- OUT UINT32 *NvRam2Size
+ OUT UINTN *NvRam2Base,
+ OUT UINT32 *NvRam2Size
)
{
- EFI_MM_COMMUNICATE_NVRAM_INFO_RESPONSE NvRam2Info;
- EFI_STATUS Status;
- UINT64 MmData[5];
+ EFI_MM_COMMUNICATE_NVRAM_INFO_RESPONSE NvRam2Info;
+ EFI_STATUS Status;
+ UINT64 MmData[5];
- if (NvRam2Base == NULL || NvRam2Size == NULL) {
+ if ((NvRam2Base == NULL) || (NvRam2Size == NULL)) {
return EFI_INVALID_PARAMETER;
}
@@ -208,13 +208,13 @@ FlashGetNvRam2Info ( EFI_STATUS
EFIAPI
FlashEraseCommand (
- IN UINTN ByteAddress,
- IN UINT32 Length
+ IN UINTN ByteAddress,
+ IN UINT32 Length
)
{
- EFI_MM_COMMUNICATE_SPINOR_RESPONSE MmSpiNorRes;
- EFI_STATUS Status;
- UINT64 MmData[5];
+ EFI_MM_COMMUNICATE_SPINOR_RESPONSE MmSpiNorRes;
+ EFI_STATUS Status;
+ UINT64 MmData[5];
if (Length == 0) {
return EFI_INVALID_PARAMETER;
@@ -256,18 +256,18 @@ FlashEraseCommand ( EFI_STATUS
EFIAPI
FlashWriteCommand (
- IN UINTN ByteAddress,
- IN VOID *Buffer,
- IN UINT32 Length
+ IN UINTN ByteAddress,
+ IN VOID *Buffer,
+ IN UINT32 Length
)
{
- EFI_MM_COMMUNICATE_SPINOR_RESPONSE MmSpiNorRes;
- EFI_STATUS Status;
- UINT64 MmData[5];
- UINTN Remain, NumWrite;
- UINTN Count = 0;
+ EFI_MM_COMMUNICATE_SPINOR_RESPONSE MmSpiNorRes;
+ EFI_STATUS Status;
+ UINT64 MmData[5];
+ UINTN Remain, NumWrite;
+ UINTN Count = 0;
- if (Buffer == NULL || Length == 0) {
+ if ((Buffer == NULL) || (Length == 0)) {
return EFI_INVALID_PARAMETER;
}
@@ -281,11 +281,11 @@ FlashWriteCommand ( MmData[3] = (UINT64)ConvertToPhysicalBuffer (Buffer + Count, NumWrite);
Status = FlashMmCommunicate (
- MmData,
- sizeof (MmData),
- &MmSpiNorRes,
- sizeof (MmSpiNorRes)
- );
+ MmData,
+ sizeof (MmData),
+ &MmSpiNorRes,
+ sizeof (MmSpiNorRes)
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -296,7 +296,7 @@ FlashWriteCommand ( }
Remain -= NumWrite;
- Count += NumWrite;
+ Count += NumWrite;
}
return EFI_SUCCESS;
@@ -316,18 +316,18 @@ FlashWriteCommand ( EFI_STATUS
EFIAPI
FlashReadCommand (
- IN UINTN ByteAddress,
- OUT VOID *Buffer,
- IN UINT32 Length
+ IN UINTN ByteAddress,
+ OUT VOID *Buffer,
+ IN UINT32 Length
)
{
- EFI_MM_COMMUNICATE_SPINOR_RESPONSE MmSpiNorRes;
- EFI_STATUS Status;
- UINT64 MmData[5];
- UINTN Remain, NumRead;
- UINTN Count = 0;
+ EFI_MM_COMMUNICATE_SPINOR_RESPONSE MmSpiNorRes;
+ EFI_STATUS Status;
+ UINT64 MmData[5];
+ UINTN Remain, NumRead;
+ UINTN Count = 0;
- if (Buffer == NULL || Length == 0) {
+ if ((Buffer == NULL) || (Length == 0)) {
return EFI_INVALID_PARAMETER;
}
@@ -341,11 +341,11 @@ FlashReadCommand ( MmData[3] = (UINT64)gFlashLibPhysicalBuffer; // Read data into the temp buffer with specified virtual address
Status = FlashMmCommunicate (
- MmData,
- sizeof (MmData),
- &MmSpiNorRes,
- sizeof (MmSpiNorRes)
- );
+ MmData,
+ sizeof (MmData),
+ &MmSpiNorRes,
+ sizeof (MmSpiNorRes)
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -360,7 +360,7 @@ FlashReadCommand ( //
CopyMem ((VOID *)(Buffer + Count), (VOID *)gFlashLibVirtualBuffer, NumRead);
Remain -= NumRead;
- Count += NumRead;
+ Count += NumRead;
}
return EFI_SUCCESS;
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLibCommon.h b/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLibCommon.h index 327429a8f9..e655287d51 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLibCommon.h +++ b/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/FlashLibCommon.h @@ -9,8 +9,8 @@ #ifndef FLASH_LIB_COMMON_H_
#define FLASH_LIB_COMMON_H_
-#define EFI_MM_MAX_TMP_BUF_SIZE 0x1000
-#define EFI_MM_MAX_PAYLOAD_SIZE 0x50
+#define EFI_MM_MAX_TMP_BUF_SIZE 0x1000
+#define EFI_MM_MAX_PAYLOAD_SIZE 0x50
#define MM_SPINOR_FUNC_GET_INFO 0x00
#define MM_SPINOR_FUNC_READ 0x01
@@ -20,8 +20,8 @@ #define MM_SPINOR_FUNC_GET_NVRAM2_INFO 0x05
#define MM_SPINOR_FUNC_GET_FAILSAFE_INFO 0x06
-#define MM_SPINOR_RES_SUCCESS 0xAABBCC00
-#define MM_SPINOR_RES_FAIL 0xAABBCCFF
+#define MM_SPINOR_RES_SUCCESS 0xAABBCC00
+#define MM_SPINOR_RES_FAIL 0xAABBCCFF
#pragma pack(1)
@@ -29,44 +29,44 @@ typedef struct { //
// Allows for disambiguation of the message format.
//
- EFI_GUID HeaderGuid;
+ EFI_GUID HeaderGuid;
//
// Describes the size of Data (in bytes) and does not include the size of the header.
//
- UINTN MessageLength;
+ UINTN MessageLength;
//
// Designates an array of bytes that is MessageLength in size.
//
- UINT8 Data[EFI_MM_MAX_PAYLOAD_SIZE];
+ UINT8 Data[EFI_MM_MAX_PAYLOAD_SIZE];
} EFI_MM_COMMUNICATE_REQUEST;
typedef struct {
- UINT64 Status;
- UINT64 DeviceBase;
- UINT64 PageSize;
- UINT64 SectorSize;
- UINT64 DeviceSize;
+ UINT64 Status;
+ UINT64 DeviceBase;
+ UINT64 PageSize;
+ UINT64 SectorSize;
+ UINT64 DeviceSize;
} EFI_MM_COMMUNICATE_SPINOR_RESPONSE;
typedef struct {
- UINT64 Status;
- UINT64 FailSafeBase;
- UINT64 FailSafeSize;
+ UINT64 Status;
+ UINT64 FailSafeBase;
+ UINT64 FailSafeSize;
} EFI_MM_COMMUNICATE_FAILSAFE_INFO_RESPONSE;
typedef struct {
- UINT64 Status;
- UINT64 NvRamBase;
- UINT64 NvRamSize;
+ UINT64 Status;
+ UINT64 NvRamBase;
+ UINT64 NvRamSize;
} EFI_MM_COMMUNICATE_NVRAM_INFO_RESPONSE;
#pragma pack()
-extern BOOLEAN gFlashLibRuntime;
-extern UINT8 *gFlashLibPhysicalBuffer;
-extern UINT8 *gFlashLibVirtualBuffer;
+extern BOOLEAN gFlashLibRuntime;
+extern UINT8 *gFlashLibPhysicalBuffer;
+extern UINT8 *gFlashLibVirtualBuffer;
/**
Provides an interface to access the Flash services via MM interface.
@@ -83,10 +83,10 @@ extern UINT8 *gFlashLibVirtualBuffer; **/
EFI_STATUS
FlashMmCommunicate (
- IN VOID *Request,
- IN UINT32 RequestDataSize,
- OUT VOID *Response,
- IN UINT32 ResponseDataSize
+ IN VOID *Request,
+ IN UINT32 RequestDataSize,
+ OUT VOID *Response,
+ IN UINT32 ResponseDataSize
);
#endif /* FLASH_LIB_COMMON_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/RuntimeFlashLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/RuntimeFlashLib.c index 14cef8e17e..35b916de33 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/RuntimeFlashLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/FlashLib/RuntimeFlashLib.c @@ -17,7 +17,7 @@ #include "FlashLibCommon.h"
-STATIC EFI_MM_COMMUNICATION2_PROTOCOL *mMmCommunicationProtocol = NULL;
+STATIC EFI_MM_COMMUNICATION2_PROTOCOL *mMmCommunicationProtocol = NULL;
/**
This is a notification function registered on EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE
@@ -29,8 +29,8 @@ STATIC EFI_MM_COMMUNICATION2_PROTOCOL *mMmCommunicationProtocol = NULL; VOID
EFIAPI
FlashLibAddressChangeEvent (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
gRT->ConvertPointer (0x0, (VOID **)&gFlashLibVirtualBuffer);
@@ -49,15 +49,15 @@ FlashLibAddressChangeEvent ( EFI_STATUS
EFIAPI
FlashLibConstructor (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_EVENT VirtualAddressChangeEvent = NULL;
- EFI_STATUS Status;
+ EFI_EVENT VirtualAddressChangeEvent = NULL;
+ EFI_STATUS Status;
gFlashLibPhysicalBuffer = AllocateRuntimeZeroPool (EFI_MM_MAX_TMP_BUF_SIZE);
- gFlashLibVirtualBuffer = gFlashLibPhysicalBuffer;
+ gFlashLibVirtualBuffer = gFlashLibPhysicalBuffer;
ASSERT (gFlashLibPhysicalBuffer != NULL);
Status = gBS->LocateProtocol (
@@ -94,18 +94,19 @@ FlashLibConstructor ( **/
EFI_STATUS
FlashMmCommunicate (
- IN VOID *Request,
- IN UINT32 RequestDataSize,
- OUT VOID *Response,
- IN UINT32 ResponseDataSize
+ IN VOID *Request,
+ IN UINT32 RequestDataSize,
+ OUT VOID *Response,
+ IN UINT32 ResponseDataSize
)
{
- EFI_MM_COMMUNICATE_REQUEST CommBuffer;
- EFI_STATUS Status;
+ EFI_MM_COMMUNICATE_REQUEST CommBuffer;
+ EFI_STATUS Status;
- if (Request == NULL || RequestDataSize == 0
- || RequestDataSize > EFI_MM_MAX_PAYLOAD_SIZE
- || (ResponseDataSize == 0 && Response == NULL)) {
+ if ( (Request == NULL) || (RequestDataSize == 0)
+ || (RequestDataSize > EFI_MM_MAX_PAYLOAD_SIZE)
+ || ((ResponseDataSize == 0) && (Response == NULL)))
+ {
return EFI_INVALID_PARAMETER;
}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/MailboxInterfaceLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/MailboxInterfaceLib.c index 0f16d37978..018e179262 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/MailboxInterfaceLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/MailboxInterfaceLib/MailboxInterfaceLib.c @@ -21,23 +21,23 @@ //
// Hardware Doorbells
//
-#define SMPRO_DB0_IRQ_OFST 40
-#define SMPRO_DB0_BASE_ADDRESS (FixedPcdGet64 (PcdSmproDbBaseReg))
+#define SMPRO_DB0_IRQ_OFST 40
+#define SMPRO_DB0_BASE_ADDRESS (FixedPcdGet64 (PcdSmproDbBaseReg))
-#define PMPRO_DB0_IRQ_OFST 56
-#define PMPRO_DB0_BASE_ADDRESS (FixedPcdGet64 (PcdPmproDbBaseReg))
+#define PMPRO_DB0_IRQ_OFST 56
+#define PMPRO_DB0_BASE_ADDRESS (FixedPcdGet64 (PcdPmproDbBaseReg))
//
// The base SPI interrupt number of the Slave socket
//
-#define SLAVE_SOCKET_SPI_INTERRUPT 352
+#define SLAVE_SOCKET_SPI_INTERRUPT 352
-#define SLAVE_SOCKET_DOORBELL_INTERRUPT_BASE(Socket) ((Socket) * SLAVE_SOCKET_SPI_INTERRUPT - 32)
+#define SLAVE_SOCKET_DOORBELL_INTERRUPT_BASE(Socket) ((Socket) * SLAVE_SOCKET_SPI_INTERRUPT - 32)
//
// Doorbell base register stride size
//
-#define DB_BASE_REG_STRIDE 0x00001000
+#define DB_BASE_REG_STRIDE 0x00001000
#define SMPRO_DBx_ADDRESS(socket, db) \
((socket) * SLAVE_SOCKET_BASE_ADDRESS_OFFSET + SMPRO_DB0_BASE_ADDRESS + DB_BASE_REG_STRIDE * (db))
@@ -48,10 +48,12 @@ //
// Doorbell Status Bits
//
-#define DB_STATUS_AVAIL_BIT BIT16
-#define DB_STATUS_ACK_BIT BIT0
+#define DB_STATUS_AVAIL_BIT BIT16
+#define DB_STATUS_ACK_BIT BIT0
-UINTN gDoorbellBaseAddress[PLATFORM_CPU_MAX_SOCKET][NUMBER_OF_DOORBELLS_PER_SOCKET] = {{0}};
+UINTN gDoorbellBaseAddress[PLATFORM_CPU_MAX_SOCKET][NUMBER_OF_DOORBELLS_PER_SOCKET] = {
+ { 0 }
+};
/**
Get the base address of a doorbell.
@@ -66,15 +68,15 @@ UINTN gDoorbellBaseAddress[PLATFORM_CPU_MAX_SOCKET][NUMBER_OF_DOORBELLS_PER_SOCK UINTN
EFIAPI
MailboxGetDoorbellAddress (
- IN UINT8 Socket,
- IN DOORBELL_CHANNELS Doorbell
+ IN UINT8 Socket,
+ IN DOORBELL_CHANNELS Doorbell
)
{
- UINTN SocketId;
- UINTN DoorbellId;
+ UINTN SocketId;
+ UINTN DoorbellId;
- if (Socket >= GetNumberOfActiveSockets ()
- || Doorbell >= NUMBER_OF_DOORBELLS_PER_SOCKET)
+ if ( (Socket >= GetNumberOfActiveSockets ())
+ || (Doorbell >= NUMBER_OF_DOORBELLS_PER_SOCKET))
{
return 0;
}
@@ -110,14 +112,14 @@ MailboxGetDoorbellAddress ( UINT32
EFIAPI
MailboxGetDoorbellInterruptNumber (
- IN UINT8 Socket,
- IN DOORBELL_CHANNELS Doorbell
+ IN UINT8 Socket,
+ IN DOORBELL_CHANNELS Doorbell
)
{
- UINT32 DoorbellInterruptNumber;
+ UINT32 DoorbellInterruptNumber;
- if (Socket >= GetNumberOfActiveSockets ()
- || Doorbell >= NUMBER_OF_DOORBELLS_PER_SOCKET)
+ if ( (Socket >= GetNumberOfActiveSockets ())
+ || (Doorbell >= NUMBER_OF_DOORBELLS_PER_SOCKET))
{
return 0;
}
@@ -151,17 +153,17 @@ MailboxGetDoorbellInterruptNumber ( EFI_STATUS
EFIAPI
MailboxRead (
- IN UINT8 Socket,
- IN DOORBELL_CHANNELS Doorbell,
- OUT MAILBOX_MESSAGE_DATA *Message
+ IN UINT8 Socket,
+ IN DOORBELL_CHANNELS Doorbell,
+ OUT MAILBOX_MESSAGE_DATA *Message
)
{
- UINTN TimeoutCount;
- UINTN DoorbellAddress;
+ UINTN TimeoutCount;
+ UINTN DoorbellAddress;
- if (Socket >= GetNumberOfActiveSockets ()
- || Doorbell >= NUMBER_OF_DOORBELLS_PER_SOCKET
- || Message == NULL)
+ if ( (Socket >= GetNumberOfActiveSockets ())
+ || (Doorbell >= NUMBER_OF_DOORBELLS_PER_SOCKET)
+ || (Message == NULL))
{
return EFI_INVALID_PARAMETER;
}
@@ -183,7 +185,7 @@ MailboxRead ( Message->ExtendedData[0] = MmioRead32 (DoorbellAddress + DB_DIN0_REG_OFST);
Message->ExtendedData[1] = MmioRead32 (DoorbellAddress + DB_DIN1_REG_OFST);
- Message->Data = MmioRead32 (DoorbellAddress + DB_IN_REG_OFST);
+ Message->Data = MmioRead32 (DoorbellAddress + DB_IN_REG_OFST);
//
// Write 1 to clear the AVAIL status
@@ -207,17 +209,17 @@ MailboxRead ( EFI_STATUS
EFIAPI
MailboxWrite (
- IN UINT8 Socket,
- IN DOORBELL_CHANNELS Doorbell,
- IN MAILBOX_MESSAGE_DATA *Message
+ IN UINT8 Socket,
+ IN DOORBELL_CHANNELS Doorbell,
+ IN MAILBOX_MESSAGE_DATA *Message
)
{
- UINTN TimeoutCount;
- UINTN DoorbellAddress;
+ UINTN TimeoutCount;
+ UINTN DoorbellAddress;
- if (Socket >= GetNumberOfActiveSockets ()
- || Doorbell >= NUMBER_OF_DOORBELLS_PER_SOCKET
- || Message == NULL)
+ if ( (Socket >= GetNumberOfActiveSockets ())
+ || (Doorbell >= NUMBER_OF_DOORBELLS_PER_SOCKET)
+ || (Message == NULL))
{
return EFI_INVALID_PARAMETER;
}
@@ -272,14 +274,14 @@ MailboxWrite ( EFI_STATUS
EFIAPI
MailboxUnmaskInterrupt (
- IN UINT8 Socket,
- IN UINT16 Doorbell
+ IN UINT8 Socket,
+ IN UINT16 Doorbell
)
{
- UINTN DoorbellAddress;
+ UINTN DoorbellAddress;
- if (Socket >= GetNumberOfActiveSockets ()
- || Doorbell >= NUMBER_OF_DOORBELLS_PER_SOCKET)
+ if ( (Socket >= GetNumberOfActiveSockets ())
+ || (Doorbell >= NUMBER_OF_DOORBELLS_PER_SOCKET))
{
return EFI_INVALID_PARAMETER;
}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.c index cdefa521da..5e0201f182 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/MemoryInitPeiLib/MemoryInitPeiLib.c @@ -23,12 +23,12 @@ BuildMemoryTypeInformationHob ( STATIC
VOID
InitMmu (
- IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
+ IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable
)
{
- VOID *TranslationTableBase;
- UINTN TranslationTableSize;
- RETURN_STATUS Status;
+ VOID *TranslationTableBase;
+ UINTN TranslationTableSize;
+ RETURN_STATUS Status;
// Note: Because we called PeiServicesInstallPeiMemory() before to call InitMmu()
// the MMU Page Table resides in DRAM (even at the top of DRAM as it is the first
@@ -49,12 +49,12 @@ InitMmu ( EFI_STATUS
EFIAPI
MemoryPeim (
- IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
- IN UINT64 UefiMemorySize
+ IN EFI_PHYSICAL_ADDRESS UefiMemoryBase,
+ IN UINT64 UefiMemorySize
)
{
- ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
- UINTN Index;
+ ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable;
+ UINTN Index;
/* Get Virtual Memory Map from the Platform Library */
ArmPlatformGetVirtualMemoryMap (&MemoryTable);
@@ -83,6 +83,7 @@ MemoryPeim ( MemoryTable[Index].Length
);
}
+
Index++;
}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.c index 453bee414f..60b4f52f99 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/MmCommunicationLib/MmCommunicationLib.c @@ -19,7 +19,7 @@ // Address, Length of the pre-allocated buffer for communication with the secure
// world.
//
-STATIC ARM_MEMORY_REGION_DESCRIPTOR mNsCommBuffMemRegion;
+STATIC ARM_MEMORY_REGION_DESCRIPTOR mNsCommBuffMemRegion;
EFI_STATUS
EFIAPI
@@ -30,7 +30,7 @@ MmCommunicationLibConstructor ( mNsCommBuffMemRegion.PhysicalBase = PcdGet64 (PcdMmBufferBase);
// During UEFI boot, virtual and physical address are the same
mNsCommBuffMemRegion.VirtualBase = mNsCommBuffMemRegion.PhysicalBase;
- mNsCommBuffMemRegion.Length = PcdGet64 (PcdMmBufferSize);
+ mNsCommBuffMemRegion.Length = PcdGet64 (PcdMmBufferSize);
return EFI_SUCCESS;
}
@@ -63,16 +63,16 @@ MmCommunicationLibConstructor ( EFI_STATUS
EFIAPI
MmCommunicationCommunicate (
- IN OUT VOID *CommBuffer,
- IN OUT UINTN *CommSize OPTIONAL
+ IN OUT VOID *CommBuffer,
+ IN OUT UINTN *CommSize OPTIONAL
)
{
- EFI_MM_COMMUNICATE_HEADER *CommunicateHeader;
- ARM_SMC_ARGS CommunicateSmcArgs;
- EFI_STATUS Status;
- UINTN BufferSize;
+ EFI_MM_COMMUNICATE_HEADER *CommunicateHeader;
+ ARM_SMC_ARGS CommunicateSmcArgs;
+ EFI_STATUS Status;
+ UINTN BufferSize;
- Status = EFI_ACCESS_DENIED;
+ Status = EFI_ACCESS_DENIED;
BufferSize = 0;
ZeroMem (&CommunicateSmcArgs, sizeof (ARM_SMC_ARGS));
@@ -103,6 +103,7 @@ MmCommunicationCommunicate ( *CommSize = mNsCommBuffMemRegion.Length;
return EFI_BAD_BUFFER_SIZE;
}
+
//
// CommSize must match MessageLength + sizeof (EFI_MM_COMMUNICATE_HEADER);
//
@@ -143,41 +144,41 @@ MmCommunicationCommunicate ( ArmCallSmc (&CommunicateSmcArgs);
switch (CommunicateSmcArgs.Arg0) {
- case ARM_SMC_MM_RET_SUCCESS:
- ZeroMem (CommBuffer, BufferSize);
- // On successful return, the size of data being returned is inferred from
- // MessageLength + Header.
- CommunicateHeader = (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegion.VirtualBase;
- BufferSize = CommunicateHeader->MessageLength +
- sizeof (CommunicateHeader->HeaderGuid) +
- sizeof (CommunicateHeader->MessageLength);
-
- CopyMem (
- CommBuffer,
- (VOID *)mNsCommBuffMemRegion.VirtualBase,
- BufferSize
- );
- Status = EFI_SUCCESS;
- break;
-
- case ARM_SMC_MM_RET_INVALID_PARAMS:
- Status = EFI_INVALID_PARAMETER;
- break;
-
- case ARM_SMC_MM_RET_DENIED:
- Status = EFI_ACCESS_DENIED;
- break;
-
- case ARM_SMC_MM_RET_NO_MEMORY:
- // Unexpected error since the CommSize was checked for zero length
- // prior to issuing the SMC
- Status = EFI_OUT_OF_RESOURCES;
- ASSERT (0);
- break;
-
- default:
- Status = EFI_ACCESS_DENIED;
- ASSERT (0);
+ case ARM_SMC_MM_RET_SUCCESS:
+ ZeroMem (CommBuffer, BufferSize);
+ // On successful return, the size of data being returned is inferred from
+ // MessageLength + Header.
+ CommunicateHeader = (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegion.VirtualBase;
+ BufferSize = CommunicateHeader->MessageLength +
+ sizeof (CommunicateHeader->HeaderGuid) +
+ sizeof (CommunicateHeader->MessageLength);
+
+ CopyMem (
+ CommBuffer,
+ (VOID *)mNsCommBuffMemRegion.VirtualBase,
+ BufferSize
+ );
+ Status = EFI_SUCCESS;
+ break;
+
+ case ARM_SMC_MM_RET_INVALID_PARAMS:
+ Status = EFI_INVALID_PARAMETER;
+ break;
+
+ case ARM_SMC_MM_RET_DENIED:
+ Status = EFI_ACCESS_DENIED;
+ break;
+
+ case ARM_SMC_MM_RET_NO_MEMORY:
+ // Unexpected error since the CommSize was checked for zero length
+ // prior to issuing the SMC
+ Status = EFI_OUT_OF_RESOURCES;
+ ASSERT (0);
+ break;
+
+ default:
+ Status = EFI_ACCESS_DENIED;
+ ASSERT (0);
}
return Status;
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.c index d0bc719361..0d0a90c764 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLib.c @@ -29,18 +29,19 @@ **/
EFI_STATUS
NVParamMmCommunicate (
- IN VOID *Request,
- IN UINT32 RequestDataSize,
- OUT VOID *Response,
- IN UINT32 ResponseDataSize
+ IN VOID *Request,
+ IN UINT32 RequestDataSize,
+ OUT VOID *Response,
+ IN UINT32 ResponseDataSize
)
{
- EFI_MM_COMMUNICATE_REQUEST CommBuffer;
- EFI_STATUS Status;
+ EFI_MM_COMMUNICATE_REQUEST CommBuffer;
+ EFI_STATUS Status;
- if (Request == NULL || RequestDataSize == 0
- || RequestDataSize > EFI_MM_MAX_PAYLOAD_SIZE
- || (ResponseDataSize == 0 && Response == NULL)) {
+ if ( (Request == NULL) || (RequestDataSize == 0)
+ || (RequestDataSize > EFI_MM_MAX_PAYLOAD_SIZE)
+ || ((ResponseDataSize == 0) && (Response == NULL)))
+ {
return EFI_INVALID_PARAMETER;
}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLibCommon.c b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLibCommon.c index 496d523455..c7a8905d12 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLibCommon.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLibCommon.c @@ -33,14 +33,14 @@ **/
EFI_STATUS
NVParamGet (
- IN UINT32 Param,
- IN UINT16 ACLRd,
- OUT UINT32 *Val
+ IN UINT32 Param,
+ IN UINT16 ACLRd,
+ OUT UINT32 *Val
)
{
- EFI_MM_COMMUNICATE_NVPARAM_RESPONSE MmNVParamRes;
- EFI_STATUS Status;
- UINT64 MmData[5];
+ EFI_MM_COMMUNICATE_NVPARAM_RESPONSE MmNVParamRes;
+ EFI_STATUS Status;
+ UINT64 MmData[5];
if (Val == NULL) {
return EFI_INVALID_PARAMETER;
@@ -61,21 +61,21 @@ NVParamGet ( }
switch (MmNVParamRes.Status) {
- case MM_NVPARAM_RES_SUCCESS:
- *Val = (UINT32)MmNVParamRes.Value;
- return EFI_SUCCESS;
+ case MM_NVPARAM_RES_SUCCESS:
+ *Val = (UINT32)MmNVParamRes.Value;
+ return EFI_SUCCESS;
- case MM_NVPARAM_RES_NOT_SET:
- return EFI_NOT_FOUND;
+ case MM_NVPARAM_RES_NOT_SET:
+ return EFI_NOT_FOUND;
- case MM_NVPARAM_RES_NO_PERM:
- return EFI_ACCESS_DENIED;
+ case MM_NVPARAM_RES_NO_PERM:
+ return EFI_ACCESS_DENIED;
- case MM_NVPARAM_RES_FAIL:
- return EFI_DEVICE_ERROR;
+ case MM_NVPARAM_RES_FAIL:
+ return EFI_DEVICE_ERROR;
- default:
- return EFI_INVALID_PARAMETER;
+ default:
+ return EFI_INVALID_PARAMETER;
}
}
@@ -99,15 +99,15 @@ NVParamGet ( **/
EFI_STATUS
NVParamSet (
- IN UINT32 Param,
- IN UINT16 ACLRd,
- IN UINT16 ACLWr,
- IN UINT32 Val
+ IN UINT32 Param,
+ IN UINT16 ACLRd,
+ IN UINT16 ACLWr,
+ IN UINT32 Val
)
{
- EFI_MM_COMMUNICATE_NVPARAM_RESPONSE MmNVParamRes;
- EFI_STATUS Status;
- UINT64 MmData[5];
+ EFI_MM_COMMUNICATE_NVPARAM_RESPONSE MmNVParamRes;
+ EFI_STATUS Status;
+ UINT64 MmData[5];
MmData[0] = MM_NVPARAM_FUNC_WRITE;
MmData[1] = Param;
@@ -126,17 +126,17 @@ NVParamSet ( }
switch (MmNVParamRes.Status) {
- case MM_NVPARAM_RES_SUCCESS:
- return EFI_SUCCESS;
+ case MM_NVPARAM_RES_SUCCESS:
+ return EFI_SUCCESS;
- case MM_NVPARAM_RES_NO_PERM:
- return EFI_ACCESS_DENIED;
+ case MM_NVPARAM_RES_NO_PERM:
+ return EFI_ACCESS_DENIED;
- case MM_NVPARAM_RES_FAIL:
- return EFI_DEVICE_ERROR;
+ case MM_NVPARAM_RES_FAIL:
+ return EFI_DEVICE_ERROR;
- default:
- return EFI_INVALID_PARAMETER;
+ default:
+ return EFI_INVALID_PARAMETER;
}
}
@@ -156,13 +156,13 @@ NVParamSet ( **/
EFI_STATUS
NVParamClr (
- IN UINT32 Param,
- IN UINT16 ACLWr
+ IN UINT32 Param,
+ IN UINT16 ACLWr
)
{
- EFI_MM_COMMUNICATE_NVPARAM_RESPONSE MmNVParamRes;
- EFI_STATUS Status;
- UINT64 MmData[5];
+ EFI_MM_COMMUNICATE_NVPARAM_RESPONSE MmNVParamRes;
+ EFI_STATUS Status;
+ UINT64 MmData[5];
MmData[0] = MM_NVPARAM_FUNC_CLEAR;
MmData[1] = Param;
@@ -180,17 +180,17 @@ NVParamClr ( }
switch (MmNVParamRes.Status) {
- case MM_NVPARAM_RES_SUCCESS:
- return EFI_SUCCESS;
+ case MM_NVPARAM_RES_SUCCESS:
+ return EFI_SUCCESS;
- case MM_NVPARAM_RES_NO_PERM:
- return EFI_ACCESS_DENIED;
+ case MM_NVPARAM_RES_NO_PERM:
+ return EFI_ACCESS_DENIED;
- case MM_NVPARAM_RES_FAIL:
- return EFI_DEVICE_ERROR;
+ case MM_NVPARAM_RES_FAIL:
+ return EFI_DEVICE_ERROR;
- default:
- return EFI_INVALID_PARAMETER;
+ default:
+ return EFI_INVALID_PARAMETER;
}
}
@@ -206,9 +206,9 @@ NVParamClrAll ( VOID
)
{
- EFI_MM_COMMUNICATE_NVPARAM_RESPONSE MmNVParamRes;
- EFI_STATUS Status;
- UINT64 MmData[5];
+ EFI_MM_COMMUNICATE_NVPARAM_RESPONSE MmNVParamRes;
+ EFI_STATUS Status;
+ UINT64 MmData[5];
MmData[0] = MM_NVPARAM_FUNC_CLEAR_ALL;
@@ -223,13 +223,13 @@ NVParamClrAll ( }
switch (MmNVParamRes.Status) {
- case MM_NVPARAM_RES_SUCCESS:
- return EFI_SUCCESS;
+ case MM_NVPARAM_RES_SUCCESS:
+ return EFI_SUCCESS;
- case MM_NVPARAM_RES_FAIL:
- return EFI_DEVICE_ERROR;
+ case MM_NVPARAM_RES_FAIL:
+ return EFI_DEVICE_ERROR;
- default:
- return EFI_INVALID_PARAMETER;
+ default:
+ return EFI_INVALID_PARAMETER;
}
}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLibCommon.h b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLibCommon.h index 57b6cccda7..a4dcae886c 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLibCommon.h +++ b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/NVParamLibCommon.h @@ -9,17 +9,17 @@ #ifndef NV_PARAM_LIB_COMMON_H_
#define NV_PARAM_LIB_COMMON_H_
-#define EFI_MM_MAX_PAYLOAD_SIZE 0x50
+#define EFI_MM_MAX_PAYLOAD_SIZE 0x50
-#define MM_NVPARAM_FUNC_READ 0x01
-#define MM_NVPARAM_FUNC_WRITE 0x02
-#define MM_NVPARAM_FUNC_CLEAR 0x03
-#define MM_NVPARAM_FUNC_CLEAR_ALL 0x04
+#define MM_NVPARAM_FUNC_READ 0x01
+#define MM_NVPARAM_FUNC_WRITE 0x02
+#define MM_NVPARAM_FUNC_CLEAR 0x03
+#define MM_NVPARAM_FUNC_CLEAR_ALL 0x04
-#define MM_NVPARAM_RES_SUCCESS 0xAABBCC00
-#define MM_NVPARAM_RES_NOT_SET 0xAABBCC01
-#define MM_NVPARAM_RES_NO_PERM 0xAABBCC02
-#define MM_NVPARAM_RES_FAIL 0xAABBCCFF
+#define MM_NVPARAM_RES_SUCCESS 0xAABBCC00
+#define MM_NVPARAM_RES_NOT_SET 0xAABBCC01
+#define MM_NVPARAM_RES_NO_PERM 0xAABBCC02
+#define MM_NVPARAM_RES_FAIL 0xAABBCCFF
#pragma pack (1)
@@ -27,22 +27,22 @@ typedef struct { //
// Allows for disambiguation of the message format.
//
- EFI_GUID HeaderGuid;
+ EFI_GUID HeaderGuid;
//
// Describes the size of Data (in bytes) and does not include the size of the header.
//
- UINTN MessageLength;
+ UINTN MessageLength;
//
// Designates an array of bytes that is MessageLength in size.
//
- UINT8 Data[EFI_MM_MAX_PAYLOAD_SIZE];
+ UINT8 Data[EFI_MM_MAX_PAYLOAD_SIZE];
} EFI_MM_COMMUNICATE_REQUEST;
typedef struct {
- UINT64 Status;
- UINT64 Value;
+ UINT64 Status;
+ UINT64 Value;
} EFI_MM_COMMUNICATE_NVPARAM_RESPONSE;
#pragma pack ()
@@ -62,9 +62,10 @@ typedef struct { **/
EFI_STATUS
NVParamMmCommunicate (
- IN VOID *Request,
- IN UINT32 RequestDataSize,
- OUT VOID *Response,
- IN UINT32 ResponseDataSize
+ IN VOID *Request,
+ IN UINT32 RequestDataSize,
+ OUT VOID *Response,
+ IN UINT32 ResponseDataSize
);
+
#endif /* NV_PARAM_LIB_COMMON_H_ */
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/RuntimeNVParamLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/RuntimeNVParamLib.c index f34e5c5c42..9f79f8d5d6 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/RuntimeNVParamLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/NVParamLib/RuntimeNVParamLib.c @@ -17,7 +17,7 @@ #include "NVParamLibCommon.h"
-STATIC EFI_MM_COMMUNICATION2_PROTOCOL *mMmCommunicationProtocol = NULL;
+STATIC EFI_MM_COMMUNICATION2_PROTOCOL *mMmCommunicationProtocol = NULL;
/**
This is a notification function registered on EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE
@@ -29,8 +29,8 @@ STATIC EFI_MM_COMMUNICATION2_PROTOCOL *mMmCommunicationProtocol = NULL; VOID
EFIAPI
NVParamLibAddressChangeEvent (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
gRT->ConvertPointer (0x0, (VOID **)&mMmCommunicationProtocol);
@@ -48,12 +48,12 @@ NVParamLibAddressChangeEvent ( EFI_STATUS
EFIAPI
NVParamLibConstructor (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_EVENT VirtualAddressChangeEvent = NULL;
- EFI_STATUS Status;
+ EFI_EVENT VirtualAddressChangeEvent = NULL;
+ EFI_STATUS Status;
Status = gBS->LocateProtocol (
&gEfiMmCommunication2ProtocolGuid,
@@ -89,18 +89,19 @@ NVParamLibConstructor ( **/
EFI_STATUS
NVParamMmCommunicate (
- IN VOID *Request,
- IN UINT32 RequestDataSize,
- OUT VOID *Response,
- IN UINT32 ResponseDataSize
+ IN VOID *Request,
+ IN UINT32 RequestDataSize,
+ OUT VOID *Response,
+ IN UINT32 ResponseDataSize
)
{
- EFI_MM_COMMUNICATE_REQUEST CommBuffer;
- EFI_STATUS Status;
+ EFI_MM_COMMUNICATE_REQUEST CommBuffer;
+ EFI_STATUS Status;
- if (Request == NULL || RequestDataSize == 0
- || RequestDataSize > EFI_MM_MAX_PAYLOAD_SIZE
- || (ResponseDataSize == 0 && Response == NULL)) {
+ if ( (Request == NULL) || (RequestDataSize == 0)
+ || (RequestDataSize > EFI_MM_MAX_PAYLOAD_SIZE)
+ || ((ResponseDataSize == 0) && (Response == NULL)))
+ {
return EFI_INVALID_PARAMETER;
}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c index d1acc1dcb4..cd570df673 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c @@ -20,18 +20,18 @@ #include <Protocol/PciHostBridgeResourceAllocation.h>
GLOBAL_REMOVE_IF_UNREFERENCED
-STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
+STATIC CHAR16 CONST *CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
L"Mem", L"I/O", L"Bus"
};
#pragma pack(1)
typedef struct {
- ACPI_HID_DEVICE_PATH AcpiDevicePath;
- EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
#pragma pack ()
-STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
+STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
{
{
ACPI_DEVICE_PATH,
@@ -43,7 +43,7 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = { },
EISA_PNP_ID (0x0A08), // PCIe
0
- }, {
+ }, {
END_DEVICE_PATH_TYPE,
END_ENTIRE_DEVICE_PATH_SUBTYPE,
{
@@ -53,40 +53,40 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = { }
};
-STATIC PCI_ROOT_BRIDGE mRootBridgeTemplate = {
- 0, // Segment
- 0, // Supports
- 0, // Attributes
- TRUE, // DmaAbove4G
- FALSE, // NoExtendedConfigSpace
- FALSE, // ResourceAssigned
+STATIC PCI_ROOT_BRIDGE mRootBridgeTemplate = {
+ 0, // Segment
+ 0, // Supports
+ 0, // Attributes
+ TRUE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
{
// Bus
0,
0xFF,
0
- }, {
+ }, {
// Io
0,
0,
0
- }, {
+ }, {
// Mem
MAX_UINT64,
0,
0
- }, {
+ }, {
// MemAbove4G
MAX_UINT64,
0,
0
- }, {
+ }, {
// PMem
MAX_UINT64,
0,
0
- }, {
+ }, {
// PMemAbove4G
MAX_UINT64,
0,
@@ -107,17 +107,17 @@ STATIC PCI_ROOT_BRIDGE mRootBridgeTemplate = { PCI_ROOT_BRIDGE *
EFIAPI
PciHostBridgeGetRootBridges (
- UINTN *Count
+ UINTN *Count
)
{
- AC01_ROOT_COMPLEX *RootComplex;
- AC01_ROOT_COMPLEX *RootComplexList;
- EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
- PCI_ROOT_BRIDGE *RootBridge;
- PCI_ROOT_BRIDGE *RootBridges;
- UINT8 Index;
- UINT8 RootBridgeCount = 0;
- VOID *Hob;
+ AC01_ROOT_COMPLEX *RootComplex;
+ AC01_ROOT_COMPLEX *RootComplexList;
+ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;
+ PCI_ROOT_BRIDGE *RootBridge;
+ PCI_ROOT_BRIDGE *RootBridges;
+ UINT8 Index;
+ UINT8 RootBridgeCount = 0;
+ VOID *Hob;
Hob = GetFirstGuidHob (&gRootComplexInfoHobGuid);
if (Hob == NULL) {
@@ -137,20 +137,21 @@ PciHostBridgeGetRootBridges ( if (!RootComplex->Active) {
continue;
}
+
RootBridge = &RootBridges[RootBridgeCount];
CopyMem (RootBridge, &mRootBridgeTemplate, sizeof (PCI_ROOT_BRIDGE));
if (RootComplex->Mmio32Base != 0) {
- RootBridge->Mem.Base = RootComplex->Mmio32Base;
- RootBridge->Mem.Limit = RootComplex->Mmio32Base + RootComplex->Mmio32Size - 1;
- RootBridge->PMem.Base = RootBridge->Mem.Base;
+ RootBridge->Mem.Base = RootComplex->Mmio32Base;
+ RootBridge->Mem.Limit = RootComplex->Mmio32Base + RootComplex->Mmio32Size - 1;
+ RootBridge->PMem.Base = RootBridge->Mem.Base;
RootBridge->PMem.Limit = RootBridge->Mem.Limit;
- RootBridge->Io.Base = RootComplex->Mmio32Base + RootComplex->Mmio32Size - AC01_PCIE_IO_SIZE;
- RootBridge->Io.Limit = RootBridge->Mem.Limit;
+ RootBridge->Io.Base = RootComplex->Mmio32Base + RootComplex->Mmio32Size - AC01_PCIE_IO_SIZE;
+ RootBridge->Io.Limit = RootBridge->Mem.Limit;
}
if (RootComplex->MmioBase != 0) {
- RootBridge->PMemAbove4G.Base = RootComplex->MmioBase;
+ RootBridge->PMemAbove4G.Base = RootComplex->MmioBase;
RootBridge->PMemAbove4G.Limit = RootComplex->MmioBase + RootComplex->MmioSize - 1;
}
@@ -188,8 +189,8 @@ PciHostBridgeGetRootBridges ( VOID
EFIAPI
PciHostBridgeFreeRootBridges (
- PCI_ROOT_BRIDGE *Bridges,
- UINTN Count
+ PCI_ROOT_BRIDGE *Bridges,
+ UINTN Count
)
{
//
@@ -214,43 +215,52 @@ PciHostBridgeFreeRootBridges ( VOID
EFIAPI
PciHostBridgeResourceConflict (
- EFI_HANDLE HostBridgeHandle,
- VOID *Configuration
+ EFI_HANDLE HostBridgeHandle,
+ VOID *Configuration
)
{
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
- UINTN RootBridgeIndex;
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ UINTN RootBridgeIndex;
+
DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
RootBridgeIndex = 0;
- Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration;
while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
- for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
- ASSERT (Descriptor->ResType <
- (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
- sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
- )
- );
- DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
- mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
- Descriptor->AddrLen, Descriptor->AddrRangeMax
- ));
+ for ( ; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ ASSERT (
+ Descriptor->ResType <
+ (sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) /
+ sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr[0])
+ )
+ );
+ DEBUG ((
+ DEBUG_ERROR,
+ " %s: Length/Alignment = 0x%lx / 0x%lx\n",
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrLen,
+ Descriptor->AddrRangeMax
+ ));
if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
- DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
- Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
- ((Descriptor->SpecificFlag &
- EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
- ) != 0) ? L" (Prefetchable)" : L""
- ));
+ DEBUG ((
+ DEBUG_ERROR,
+ " Granularity/SpecificFlag = %ld / %02x%s\n",
+ Descriptor->AddrSpaceGranularity,
+ Descriptor->SpecificFlag,
+ ((Descriptor->SpecificFlag &
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+ ) != 0) ? L" (Prefetchable)" : L""
+ ));
}
}
+
//
// Skip the END descriptor for root bridge
//
ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
- (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
- );
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+ );
}
}
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c index 80e9f7888a..80d2c46cc6 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/PciSegmentLibPci/PciSegmentLib.c @@ -17,23 +17,23 @@ #include <Platform/Ac01.h>
-#define GET_SEG_NUM(Address) (((Address) >> 32) & 0xFFFF)
-#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F)
-#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F)
-#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07)
-#define GET_REG_NUM(Address) ((Address) & 0xFFF)
-
-#define WORD_ALIGN_MASK 0x3
-#define WORD_GET_BYTE(Word, ByteOffset) (((Word) >> ((ByteOffset) * 8)) & 0xFF)
+#define GET_SEG_NUM(Address) (((Address) >> 32) & 0xFFFF)
+#define GET_BUS_NUM(Address) (((Address) >> 20) & 0x7F)
+#define GET_DEV_NUM(Address) (((Address) >> 15) & 0x1F)
+#define GET_FUNC_NUM(Address) (((Address) >> 12) & 0x07)
+#define GET_REG_NUM(Address) ((Address) & 0xFFF)
+
+#define WORD_ALIGN_MASK 0x3
+#define WORD_GET_BYTE(Word, ByteOffset) (((Word) >> ((ByteOffset) * 8)) & 0xFF)
#define WORD_SET_BYTE(Word, Byte, ByteOffset) \
(((Word) & ~(0xFF << ((ByteOffset) * 8))) | ((UINT32)(Byte) << ((ByteOffset) * 8)))
-#define WORD_GET_HALF_WORD(Word, ByteOffset) (((Word) >> ((ByteOffset) * 8)) & 0xFFFF)
+#define WORD_GET_HALF_WORD(Word, ByteOffset) (((Word) >> ((ByteOffset) * 8)) & 0xFFFF)
#define WORD_SET_HALF_WORD(Word, HalfWord, ByteOffset) \
(((Word) & ~(0xFFFF << ((ByteOffset) * 8))) | ((UINT32)(HalfWord) << ((ByteOffset) * 8)))
-#define HEADER_TYPE_REG 0x0C
-#define GET_HEADER_TYPE(x) (((x) >> 16) & 0x7F)
+#define HEADER_TYPE_REG 0x0C
+#define GET_HEADER_TYPE(x) (((x) >> 16) & 0x7F)
#define PRIMARY_BUS_NUMBER_REG 0x18
/**
@@ -44,7 +44,7 @@ @param M Additional bits to assert to be zero.
**/
-#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
+#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A, M) \
ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)
/**
@@ -52,7 +52,7 @@ @param A The address to convert.
**/
-#define PCI_SEGMENT_TO_PCI_ADDRESS(A) ((UINTN)(UINT32)A)
+#define PCI_SEGMENT_TO_PCI_ADDRESS(A) ((UINTN)(UINT32)A)
/**
Get the MCFG Base address from the segment number.
@@ -62,9 +62,9 @@ GetMmcfgBase ( IN UINT16 SegmentNumber
)
{
- AC01_ROOT_COMPLEX *RootComplexList;
- UINTN Idx;
- VOID *Hob;
+ AC01_ROOT_COMPLEX *RootComplexList;
+ UINTN Idx;
+ VOID *Hob;
Hob = GetFirstGuidHob (&gRootComplexInfoHobGuid);
if (Hob == NULL) {
@@ -126,24 +126,24 @@ PciSegmentRegisterForRuntimeAccess ( UINT8
EFIAPI
PciSegmentRead8 (
- IN UINT64 Address
+ IN UINT64 Address
)
{
- UINT32 Val32;
- UINT64 AlignedAddr;
- UINT8 Value;
- UINTN CfgBase;
+ UINT32 Val32;
+ UINT64 AlignedAddr;
+ UINT8 Value;
+ UINTN CfgBase;
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
- CfgBase = GetMmcfgBase (GET_SEG_NUM (Address)) + (Address & 0x0FFFFFFF);
+ CfgBase = GetMmcfgBase (GET_SEG_NUM (Address)) + (Address & 0x0FFFFFFF);
AlignedAddr = CfgBase & ~WORD_ALIGN_MASK;
Val32 = MmioRead32 (AlignedAddr);
Value = WORD_GET_BYTE (Val32, CfgBase & WORD_ALIGN_MASK);
DEBUG ((
- DEBUG_VERBOSE, + DEBUG_VERBOSE,
"PCIe CFG RD8: 0x%p value: 0x%02X (0x%08llX 0x%08X)\n",
CfgBase,
Value,
@@ -171,17 +171,17 @@ PciSegmentRead8 ( UINT8
EFIAPI
PciSegmentWrite8 (
- IN UINT64 Address,
- IN UINT8 Value
+ IN UINT64 Address,
+ IN UINT8 Value
)
{
- UINT32 Val32;
- UINT64 AlignedAddr;
- UINTN CfgBase;
+ UINT32 Val32;
+ UINT64 AlignedAddr;
+ UINTN CfgBase;
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
- CfgBase = GetMmcfgBase (GET_SEG_NUM (Address)) + (Address & 0x0FFFFFFF);
+ CfgBase = GetMmcfgBase (GET_SEG_NUM (Address)) + (Address & 0x0FFFFFFF);
AlignedAddr = CfgBase & ~WORD_ALIGN_MASK;
Val32 = MmioRead32 (AlignedAddr);
@@ -190,7 +190,7 @@ PciSegmentWrite8 ( MmioWrite32 (AlignedAddr, Val32);
DEBUG ((
- DEBUG_VERBOSE, + DEBUG_VERBOSE,
"PCIe CFG WR8: 0x%p value: 0x%02X (0x%08llX 0x%08X)\n",
CfgBase,
Value,
@@ -221,8 +221,8 @@ PciSegmentWrite8 ( UINT8
EFIAPI
PciSegmentOr8 (
- IN UINT64 Address,
- IN UINT8 OrData
+ IN UINT64 Address,
+ IN UINT8 OrData
)
{
return PciSegmentWrite8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), (UINT8)(PciSegmentRead8 (Address) | OrData));
@@ -247,8 +247,8 @@ PciSegmentOr8 ( UINT8
EFIAPI
PciSegmentAnd8 (
- IN UINT64 Address,
- IN UINT8 AndData
+ IN UINT64 Address,
+ IN UINT8 AndData
)
{
return PciSegmentWrite8 (Address, (UINT8)(PciSegmentRead8 (Address) & AndData));
@@ -277,9 +277,9 @@ PciSegmentAnd8 ( UINT8
EFIAPI
PciSegmentAndThenOr8 (
- IN UINT64 Address,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINT64 Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
return PciSegmentWrite8 (Address, (UINT8)((PciSegmentRead8 (Address) & AndData) | OrData));
@@ -309,9 +309,9 @@ PciSegmentAndThenOr8 ( UINT8
EFIAPI
PciSegmentBitFieldRead8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
@@ -344,10 +344,10 @@ PciSegmentBitFieldRead8 ( UINT8
EFIAPI
PciSegmentBitFieldWrite8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
)
{
return PciSegmentWrite8 (
@@ -386,10 +386,10 @@ PciSegmentBitFieldWrite8 ( UINT8
EFIAPI
PciSegmentBitFieldOr8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
)
{
return PciSegmentWrite8 (
@@ -428,10 +428,10 @@ PciSegmentBitFieldOr8 ( UINT8
EFIAPI
PciSegmentBitFieldAnd8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
)
{
return PciSegmentWrite8 (
@@ -473,11 +473,11 @@ PciSegmentBitFieldAnd8 ( UINT8
EFIAPI
PciSegmentBitFieldAndThenOr8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
)
{
return PciSegmentWrite8 (
@@ -503,26 +503,26 @@ PciSegmentBitFieldAndThenOr8 ( UINT16
EFIAPI
PciSegmentRead16 (
- IN UINT64 Address
+ IN UINT64 Address
)
{
- UINT16 Value;
- UINT32 Val32;
- UINT64 AlignedAddr;
- UINT8 HeaderType;
- UINT8 PrimaryBus;
- UINTN CfgBase;
+ UINT16 Value;
+ UINT32 Val32;
+ UINT64 AlignedAddr;
+ UINT8 HeaderType;
+ UINT8 PrimaryBus;
+ UINTN CfgBase;
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
- PrimaryBus = 0;
- CfgBase = GetMmcfgBase (GET_SEG_NUM (Address)) + (Address & 0x0FFFFFFE);
+ PrimaryBus = 0;
+ CfgBase = GetMmcfgBase (GET_SEG_NUM (Address)) + (Address & 0x0FFFFFFE);
AlignedAddr = CfgBase & ~WORD_ALIGN_MASK;
if ((GET_BUS_NUM (CfgBase) > 0) && (GET_DEV_NUM (CfgBase) > 0) && (GET_REG_NUM (CfgBase) == 0)) {
Value = MmioRead32 (CfgBase);
DEBUG ((
- DEBUG_VERBOSE, + DEBUG_VERBOSE,
"PCIe CFG RD16: B%X|D%X 0x%p value: 0x%08X\n",
GET_BUS_NUM (CfgBase),
GET_DEV_NUM (CfgBase),
@@ -534,7 +534,7 @@ PciSegmentRead16 ( Val32 = MmioRead32 (CfgBase + HEADER_TYPE_REG);
HeaderType = GET_HEADER_TYPE (Val32);
- DEBUG ((DEBUG_VERBOSE, " Peek RD: HeaderType=0x%02X\n", HeaderType)); + DEBUG ((DEBUG_VERBOSE, " Peek RD: HeaderType=0x%02X\n", HeaderType));
// Type 1 Configuration Space Header
if (HeaderType != 0) {
@@ -545,7 +545,7 @@ PciSegmentRead16 ( if ((HeaderType == 0) || (PrimaryBus != 0)) {
Value = 0xFFFF;
DEBUG ((
- DEBUG_VERBOSE, + DEBUG_VERBOSE,
" Skip RD16 B%X|D%X PCIe CFG RD: 0x%p return 0xFFFF\n",
GET_BUS_NUM (CfgBase),
GET_DEV_NUM (CfgBase),
@@ -560,7 +560,7 @@ PciSegmentRead16 ( Value = WORD_GET_HALF_WORD (Val32, CfgBase & WORD_ALIGN_MASK);
DEBUG ((
- DEBUG_VERBOSE, + DEBUG_VERBOSE,
"PCIe CFG RD16: 0x%p value: 0x%04X (0x%08llX 0x%08X)\n",
CfgBase,
Value,
@@ -568,7 +568,7 @@ PciSegmentRead16 ( Val32
));
- if (GET_REG_NUM (Address) == 0xAE && Value == 0xFFFF) {
+ if ((GET_REG_NUM (Address) == 0xAE) && (Value == 0xFFFF)) {
DEBUG ((DEBUG_ERROR, "PANIC due to PCIe link issue - Addr 0x%llx\n", Address));
// Loop forever waiting for failsafe/watch dog time out
CpuDeadLoop ();
@@ -595,17 +595,17 @@ PciSegmentRead16 ( UINT16
EFIAPI
PciSegmentWrite16 (
- IN UINT64 Address,
- IN UINT16 Value
+ IN UINT64 Address,
+ IN UINT16 Value
)
{
- UINT32 Val32;
- UINT64 AlignedAddr;
- UINTN CfgBase;
+ UINT32 Val32;
+ UINT64 AlignedAddr;
+ UINTN CfgBase;
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
- CfgBase = GetMmcfgBase (GET_SEG_NUM (Address)) + (Address & 0x0FFFFFFE);
+ CfgBase = GetMmcfgBase (GET_SEG_NUM (Address)) + (Address & 0x0FFFFFFE);
AlignedAddr = CfgBase & ~WORD_ALIGN_MASK;
Val32 = MmioRead32 (AlignedAddr);
@@ -614,7 +614,7 @@ PciSegmentWrite16 ( MmioWrite32 (AlignedAddr, Val32);
DEBUG ((
- DEBUG_VERBOSE, + DEBUG_VERBOSE,
"PCIe CFG WR16: 0x%p value: 0x%04X (0x%08llX 0x%08X)\n",
CfgBase,
Value,
@@ -648,11 +648,11 @@ PciSegmentWrite16 ( UINT16
EFIAPI
PciSegmentOr16 (
- IN UINT64 Address,
- IN UINT16 OrData
+ IN UINT64 Address,
+ IN UINT16 OrData
)
{
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
+ return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) | OrData));
}
/**
@@ -676,11 +676,11 @@ PciSegmentOr16 ( UINT16
EFIAPI
PciSegmentAnd16 (
- IN UINT64 Address,
- IN UINT16 AndData
+ IN UINT64 Address,
+ IN UINT16 AndData
)
{
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
+ return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) & AndData));
}
/**
@@ -707,12 +707,12 @@ PciSegmentAnd16 ( UINT16
EFIAPI
PciSegmentAndThenOr16 (
- IN UINT64 Address,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINT64 Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
- return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
+ return PciSegmentWrite16 (Address, (UINT16)((PciSegmentRead16 (Address) & AndData) | OrData));
}
/**
@@ -740,9 +740,9 @@ PciSegmentAndThenOr16 ( UINT16
EFIAPI
PciSegmentBitFieldRead16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
@@ -776,10 +776,10 @@ PciSegmentBitFieldRead16 ( UINT16
EFIAPI
PciSegmentBitFieldWrite16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
)
{
return PciSegmentWrite16 (
@@ -819,10 +819,10 @@ PciSegmentBitFieldWrite16 ( UINT16
EFIAPI
PciSegmentBitFieldOr16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
)
{
return PciSegmentWrite16 (
@@ -862,10 +862,10 @@ PciSegmentBitFieldOr16 ( UINT16
EFIAPI
PciSegmentBitFieldAnd16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
)
{
return PciSegmentWrite16 (
@@ -908,11 +908,11 @@ PciSegmentBitFieldAnd16 ( UINT16
EFIAPI
PciSegmentBitFieldAndThenOr16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
)
{
return PciSegmentWrite16 (
@@ -938,24 +938,24 @@ PciSegmentBitFieldAndThenOr16 ( UINT32
EFIAPI
PciSegmentRead32 (
- IN UINT64 Address
+ IN UINT64 Address
)
{
- UINT32 Val32;
- UINT32 Value;
- UINT8 HeaderType;
- UINT8 PrimaryBus;
- UINTN CfgBase;
+ UINT32 Val32;
+ UINT32 Value;
+ UINT8 HeaderType;
+ UINT8 PrimaryBus;
+ UINTN CfgBase;
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
PrimaryBus = 0;
- CfgBase = GetMmcfgBase (GET_SEG_NUM (Address)) + (Address & 0x0FFFFFFC);
+ CfgBase = GetMmcfgBase (GET_SEG_NUM (Address)) + (Address & 0x0FFFFFFC);
if ((GET_BUS_NUM (CfgBase) > 0) && (GET_DEV_NUM (CfgBase) > 0) && (GET_REG_NUM (CfgBase) == 0)) {
Value = MmioRead32 (CfgBase);
DEBUG ((
- DEBUG_VERBOSE, + DEBUG_VERBOSE,
"PCIe CFG RD32: B%X|D%X 0x%p value: 0x%08X\n",
GET_BUS_NUM (CfgBase),
GET_DEV_NUM (CfgBase),
@@ -967,7 +967,7 @@ PciSegmentRead32 ( Val32 = MmioRead32 (CfgBase + HEADER_TYPE_REG);
HeaderType = GET_HEADER_TYPE (Val32);
- DEBUG ((DEBUG_VERBOSE, " Peek RD: HeaderType=0x%02X\n", HeaderType)); + DEBUG ((DEBUG_VERBOSE, " Peek RD: HeaderType=0x%02X\n", HeaderType));
// Type 1 Configuration Space Header
if (HeaderType != 0) {
@@ -978,7 +978,7 @@ PciSegmentRead32 ( if ((HeaderType == 0) || (PrimaryBus != 0)) {
Value = 0xFFFFFFFF;
DEBUG ((
- DEBUG_VERBOSE, + DEBUG_VERBOSE,
" Skip RD32 B%X|D%X PCIe CFG RD: 0x%p return 0xFFFFFFFF\n",
GET_BUS_NUM (CfgBase),
GET_DEV_NUM (CfgBase),
@@ -991,7 +991,7 @@ PciSegmentRead32 ( Value = MmioRead32 (CfgBase);
}
- DEBUG ((DEBUG_VERBOSE, "PCIe CFG RD32: 0x%p value: 0x%08X\n", CfgBase, Value)); + DEBUG ((DEBUG_VERBOSE, "PCIe CFG RD32: 0x%p value: 0x%08X\n", CfgBase, Value));
return Value;
}
@@ -1014,8 +1014,8 @@ PciSegmentRead32 ( UINT32
EFIAPI
PciSegmentWrite32 (
- IN UINT64 Address,
- IN UINT32 Value
+ IN UINT64 Address,
+ IN UINT32 Value
)
{
UINTN CfgBase;
@@ -1025,7 +1025,7 @@ PciSegmentWrite32 ( CfgBase = GetMmcfgBase (GET_SEG_NUM (Address)) + (Address & 0x0FFFFFFC);
MmioWrite32 (CfgBase, Value);
DEBUG ((
- DEBUG_VERBOSE, + DEBUG_VERBOSE,
"PCIe CFG WR32: 0x%p value: 0x%08X (0x%08X)\n",
CfgBase,
Value,
@@ -1056,8 +1056,8 @@ PciSegmentWrite32 ( UINT32
EFIAPI
PciSegmentOr32 (
- IN UINT64 Address,
- IN UINT32 OrData
+ IN UINT64 Address,
+ IN UINT32 OrData
)
{
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
@@ -1084,8 +1084,8 @@ PciSegmentOr32 ( UINT32
EFIAPI
PciSegmentAnd32 (
- IN UINT64 Address,
- IN UINT32 AndData
+ IN UINT64 Address,
+ IN UINT32 AndData
)
{
return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
@@ -1115,9 +1115,9 @@ PciSegmentAnd32 ( UINT32
EFIAPI
PciSegmentAndThenOr32 (
- IN UINT64 Address,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINT64 Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
@@ -1148,9 +1148,9 @@ PciSegmentAndThenOr32 ( UINT32
EFIAPI
PciSegmentBitFieldRead32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
)
{
return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
@@ -1184,10 +1184,10 @@ PciSegmentBitFieldRead32 ( UINT32
EFIAPI
PciSegmentBitFieldWrite32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
)
{
return PciSegmentWrite32 (
@@ -1226,10 +1226,10 @@ PciSegmentBitFieldWrite32 ( UINT32
EFIAPI
PciSegmentBitFieldOr32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
)
{
return PciSegmentWrite32 (
@@ -1268,10 +1268,10 @@ PciSegmentBitFieldOr32 ( UINT32
EFIAPI
PciSegmentBitFieldAnd32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
)
{
return PciSegmentWrite32 (
@@ -1314,11 +1314,11 @@ PciSegmentBitFieldAnd32 ( UINT32
EFIAPI
PciSegmentBitFieldAndThenOr32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
+ IN UINT64 Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
)
{
return PciSegmentWrite32 (
@@ -1353,12 +1353,12 @@ PciSegmentBitFieldAndThenOr32 ( UINTN
EFIAPI
PciSegmentReadBuffer (
- IN UINT64 StartAddress,
- IN UINTN Size,
- OUT VOID *Buffer
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
)
{
- UINTN ReturnValue;
+ UINTN ReturnValue;
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
ASSERT (((StartAddress & 0xFFF) + Size) <= SIZE_4KB);
@@ -1379,19 +1379,19 @@ PciSegmentReadBuffer ( // Read a byte if StartAddress is byte aligned
//
*(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
- StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8 *)Buffer + 1;
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
}
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {
//
// Read a word if StartAddress is word aligned
//
WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16 *)Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
while (Size >= sizeof (UINT32)) {
@@ -1400,8 +1400,8 @@ PciSegmentReadBuffer ( //
WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));
StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32 *)Buffer + 1;
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
}
if (Size >= sizeof (UINT16)) {
@@ -1410,8 +1410,8 @@ PciSegmentReadBuffer ( //
WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16 *)Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
if (Size >= sizeof (UINT8)) {
@@ -1451,12 +1451,12 @@ PciSegmentReadBuffer ( UINTN
EFIAPI
PciSegmentWriteBuffer (
- IN UINT64 StartAddress,
- IN UINTN Size,
- IN VOID *Buffer
+ IN UINT64 StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
)
{
- UINTN ReturnValue;
+ UINTN ReturnValue;
ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
ASSERT (((StartAddress & 0xFFF) + Size) <= SIZE_4KB);
@@ -1478,18 +1478,18 @@ PciSegmentWriteBuffer ( //
PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);
StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8 *)Buffer + 1;
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
}
- if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {
//
// Write a word if StartAddress is word aligned
//
PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16 *)Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
while (Size >= sizeof (UINT32)) {
@@ -1498,8 +1498,8 @@ PciSegmentWriteBuffer ( //
PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));
StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32 *)Buffer + 1;
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
}
if (Size >= sizeof (UINT16)) {
@@ -1508,8 +1508,8 @@ PciSegmentWriteBuffer ( //
PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));
StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16 *)Buffer + 1;
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
}
if (Size >= sizeof (UINT8)) {
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/PcieHotPlugLib/PcieHotPlugLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/PcieHotPlugLib/PcieHotPlugLib.c index 10de5d17d2..53b84ed26f 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/PcieHotPlugLib/PcieHotPlugLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/PcieHotPlugLib/PcieHotPlugLib.c @@ -20,7 +20,7 @@ // SPM takes up to 4 arguments as value for SPCI call (Args.SpciParam1->Args.SpciParam4).
#define MAX_MSG_CMD_ARGS 4
-UINT32 HandleId;
+UINT32 HandleId;
STATIC
EFI_STATUS
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.c index f7e6fb6092..11bf4b024b 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/RngLib/RngLib.c @@ -26,10 +26,10 @@ BOOLEAN
EFIAPI
GetRandomNumber16 (
- OUT UINT16 *Rand
+ OUT UINT16 *Rand
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Rand != NULL);
if (Rand == NULL) {
@@ -58,10 +58,10 @@ GetRandomNumber16 ( BOOLEAN
EFIAPI
GetRandomNumber32 (
- OUT UINT32 *Rand
+ OUT UINT32 *Rand
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Rand != NULL);
if (Rand == NULL) {
@@ -90,10 +90,10 @@ GetRandomNumber32 ( BOOLEAN
EFIAPI
GetRandomNumber64 (
- OUT UINT64 *Rand
+ OUT UINT64 *Rand
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Rand != NULL);
if (Rand == NULL) {
@@ -122,10 +122,10 @@ GetRandomNumber64 ( BOOLEAN
EFIAPI
GetRandomNumber128 (
- OUT UINT64 *Rand
+ OUT UINT64 *Rand
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT (Rand != NULL);
if (Rand == NULL) {
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceLib/SystemFirmwareInterfaceLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceLib/SystemFirmwareInterfaceLib.c index d27a35cfa7..2919e77147 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceLib/SystemFirmwareInterfaceLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/SystemFirmwareInterfaceLib/SystemFirmwareInterfaceLib.c @@ -16,18 +16,18 @@ #include <Library/MailboxInterfaceLib.h>
#include <Library/SystemFirmwareInterfaceLib.h>
-#define SMPRO_RTC_YEAR_SHIFT 16
-#define SMPRO_RTC_YEAR_MASK 0xFFFF0000
-#define SMPRO_RTC_MONTH_SHIFT 8
-#define SMPRO_RTC_MONTH_MASK 0x0000FF00
-#define SMPRO_RTC_DAY_SHIFT 0
-#define SMPRO_RTC_DAY_MASK 0x000000FF
+#define SMPRO_RTC_YEAR_SHIFT 16
+#define SMPRO_RTC_YEAR_MASK 0xFFFF0000
+#define SMPRO_RTC_MONTH_SHIFT 8
+#define SMPRO_RTC_MONTH_MASK 0x0000FF00
+#define SMPRO_RTC_DAY_SHIFT 0
+#define SMPRO_RTC_DAY_MASK 0x000000FF
#define CONVERT_EFI_TIME_TO_SMPRO_DATE(x) \
(((x)->Year << SMPRO_RTC_YEAR_SHIFT) & SMPRO_RTC_YEAR_MASK) | \
(((x)->Month << SMPRO_RTC_MONTH_SHIFT) & SMPRO_RTC_MONTH_MASK) | \
(((x)->Day << SMPRO_RTC_DAY_SHIFT) & SMPRO_RTC_DAY_MASK)
-#define MAILBOX_TRNG_MESSAGE_PARAM1_MASK 0x000000FF
+#define MAILBOX_TRNG_MESSAGE_PARAM1_MASK 0x000000FF
/**
Read a register which is not accessible from the non-secure world
@@ -46,15 +46,15 @@ EFI_STATUS
EFIAPI
MailboxMsgRegisterRead (
- IN UINT8 Socket,
- IN UINTN Address,
- OUT UINT32 *Value
+ IN UINT8 Socket,
+ IN UINTN Address,
+ OUT UINT32 *Value
)
{
- EFI_STATUS Status;
- MAILBOX_MESSAGE_DATA Message;
- UINT32 AddressLower32Bit;
- UINT32 AddressUpper32Bit;
+ EFI_STATUS Status;
+ MAILBOX_MESSAGE_DATA Message;
+ UINT32 AddressLower32Bit;
+ UINT32 AddressUpper32Bit;
if (Socket >= GetNumberOfActiveSockets ()) {
return EFI_INVALID_PARAMETER;
@@ -111,15 +111,15 @@ MailboxMsgRegisterRead ( EFI_STATUS
EFIAPI
MailboxMsgRegisterWrite (
- IN UINT8 Socket,
- IN UINTN Address,
- IN UINT32 Value
+ IN UINT8 Socket,
+ IN UINTN Address,
+ IN UINT32 Value
)
{
- EFI_STATUS Status;
- MAILBOX_MESSAGE_DATA Message;
- UINT32 AddressLower32Bit;
- UINT32 AddressUpper32Bit;
+ EFI_STATUS Status;
+ MAILBOX_MESSAGE_DATA Message;
+ UINT32 AddressLower32Bit;
+ UINT32 AddressUpper32Bit;
if (Socket >= GetNumberOfActiveSockets ()) {
return EFI_INVALID_PARAMETER;
@@ -158,26 +158,26 @@ MailboxMsgRegisterWrite ( EFI_STATUS
EFIAPI
MailboxMsgSetPccSharedMem (
- IN UINT8 Socket,
- IN UINT8 Doorbell,
- IN BOOLEAN AddressAlign256,
- IN UINTN Address
+ IN UINT8 Socket,
+ IN UINT8 Doorbell,
+ IN BOOLEAN AddressAlign256,
+ IN UINTN Address
)
{
- EFI_STATUS Status;
- MAILBOX_MESSAGE_DATA Message;
- UINT8 AlignBit;
- UINT8 AlignControl;
+ EFI_STATUS Status;
+ MAILBOX_MESSAGE_DATA Message;
+ UINT8 AlignBit;
+ UINT8 AlignControl;
- if (Socket >= GetNumberOfActiveSockets () || Doorbell >= NUMBER_OF_DOORBELLS_PER_SOCKET) {
+ if ((Socket >= GetNumberOfActiveSockets ()) || (Doorbell >= NUMBER_OF_DOORBELLS_PER_SOCKET)) {
return EFI_INVALID_PARAMETER;
}
if (AddressAlign256) {
- AlignBit = 8;
+ AlignBit = 8;
AlignControl = MAILBOX_ADDRESS_256_ALIGNMENT;
} else {
- AlignBit = 0;
+ AlignBit = 0;
AlignControl = MAILBOX_ADDRESS_NO_ALIGNMENT;
}
@@ -209,11 +209,11 @@ MailboxMsgSetPccSharedMem ( EFI_STATUS
EFIAPI
MailboxMsgGetRandomNumber64 (
- OUT UINT8 *Buffer
+ OUT UINT8 *Buffer
)
{
- EFI_STATUS Status;
- MAILBOX_MESSAGE_DATA Message;
+ EFI_STATUS Status;
+ MAILBOX_MESSAGE_DATA Message;
if (Buffer == NULL) {
return EFI_INVALID_PARAMETER;
@@ -270,8 +270,8 @@ MailboxMsgSetBootProgress ( IN UINT32 Checkpoint
)
{
- EFI_STATUS Status;
- MAILBOX_MESSAGE_DATA Message;
+ EFI_STATUS Status;
+ MAILBOX_MESSAGE_DATA Message;
if (Socket >= GetNumberOfActiveSockets ()) {
return EFI_INVALID_PARAMETER;
@@ -316,11 +316,11 @@ MailboxMsgSetBootProgress ( EFI_STATUS
EFIAPI
MailboxMsgDateConfig (
- IN EFI_TIME *Time
+ IN EFI_TIME *Time
)
{
- EFI_STATUS Status;
- MAILBOX_MESSAGE_DATA Message;
+ EFI_STATUS Status;
+ MAILBOX_MESSAGE_DATA Message;
UINT32 Date;
if (Time == NULL) {
diff --git a/Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.c b/Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.c index ee2a102bfd..755272021d 100644 --- a/Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.c +++ b/Silicon/Ampere/AmpereAltraPkg/Library/TrngLib/TrngLib.c @@ -27,14 +27,14 @@ EFI_STATUS
EFIAPI
GenerateRandomNumbers (
- OUT UINT8 *Buffer,
- IN UINTN BufferSize
+ OUT UINT8 *Buffer,
+ IN UINTN BufferSize
)
{
- UINTN Count;
- UINTN RandSize;
- UINT64 Value;
- EFI_STATUS Status;
+ UINTN Count;
+ UINTN RandSize;
+ UINT64 Value;
+ EFI_STATUS Status;
if ((BufferSize == 0) || (Buffer == NULL)) {
return EFI_INVALID_PARAMETER;
@@ -55,6 +55,7 @@ GenerateRandomNumbers ( DEBUG ((DEBUG_ERROR, "%a: Failed to get random number!\n", __func__));
return EFI_DEVICE_ERROR;
}
+
CopyMem (Buffer + Count * sizeof (UINT64), &Value, RandSize);
}
}
|