diff options
Diffstat (limited to 'Silicon/AMD/Styx')
25 files changed, 3109 insertions, 3109 deletions
diff --git a/Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec b/Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec index 15ee61b..8a89762 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec +++ b/Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec @@ -1,133 +1,133 @@ -#**
-# @file
-#
-# AmdModulePkg.dec
-#
-# AMD-specific package declaration file.
-#
-# @xrefitem bom "File Content Label" "Release Content"
-# @e project: FDK
-# @e sub-project: UEFI
-# @e version: $Revision: 337482 $ @e date: $Date: 2016-03-11 21:39:02 -0600 (Fri, 11 Mar 2016) $
-#
-#
-##*****************************************************************************
-#
-# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#***************************************************************************/
-
-
-################################################################################
-#
-# Defines Section - statements that will be processed to create a Makefile.
-#
-################################################################################
-[Defines]
- DEC_SPECIFICATION = 0x00010005
- PACKAGE_NAME = AmdModulePkg
- PACKAGE_GUID = E967965B-4447-4CBB-9521-898B5A329240
- PACKAGE_VERSION = 0.1
-
-################################################################################
-#
-# Include Section - list of Include Paths that are provided by this package.
-# Comments are used for Keywords and Module Types.
-#
-# Supported Module Types:
-# SEC PEIM DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER
-#
-################################################################################
-[Includes]
- Common
- Include
- Include/Library
- Include/Ppi
- Include/Protocol
-
-
-[LibraryClasses]
- ## @libraryclass Provides a library function to get a DXE driver name
- ##
-
-[Protocols]
- gAmdIscpDxeProtocolGuid = { 0x05c794c8, 0x6aef, 0x4450, { 0x91, 0x78, 0xca, 0x70, 0x53, 0x75, 0xbd, 0x91 } }
- gAmdRasApeiProtocolGuid = { 0xe9dbcc60, 0x8f93, 0x47ed, { 0x84, 0x78, 0x46, 0x78, 0xf1, 0x9f, 0x73, 0x4a } }
-
-[Ppis]
- gPeiIscpPpiGuid = { 0xca2c1ecd, 0xc702, 0x49b1, { 0xae, 0x24, 0x9b, 0x6f, 0xa8, 0x71, 0x3b, 0x23 } }
- gPeiFusePpiGuid = { 0xe074fa9f, 0x1bc7, 0x4af9, { 0x8f, 0x0d, 0x90, 0x0b, 0x76, 0x50, 0x5f, 0xfe } }
- gPeiGionbPpiGuid = { 0x24b8ebcc, 0x3871, 0x4b39, { 0xaa, 0x1a, 0x0f, 0x86, 0x7d, 0xbf, 0x97, 0xc6 } }
-
-[Guids]
- gAmdModulePkgTokenSpaceGuid = { 0x2f9003d7, 0xac98, 0x407d, { 0xae, 0x38, 0x9d, 0xbf, 0x81, 0x27, 0xe5, 0xb1 } }
- gAmdModulePkgVariableGuid = { 0xf3dd4189, 0xe1b7, 0x49da, { 0xa5, 0xd3, 0x34, 0x28, 0x6f, 0xae, 0x2f, 0x01 } }
-
-[PcdsFixedAtBuild]
- gAmdModulePkgTokenSpaceGuid.PcdFdkVersionMajor|0x1|UINT8|0x00000026
- gAmdModulePkgTokenSpaceGuid.PcdFdkVersionMinor|0x0|UINT8|0x00000027
- gAmdModulePkgTokenSpaceGuid.PcdFdkVersionPoint|0x0|UINT8|0x00000028
- gAmdModulePkgTokenSpaceGuid.PcdFdkVersionSubpoint|0x2|UINT8|0x00000029
-
-[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
- gAmdModulePkgTokenSpaceGuid.PcdCCPBase|0xE0100000|UINT64|0x00000001
- gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes0|0xE0B00000|UINT64|0x00000002
- gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes1|0xE0B20000|UINT64|0x00000003
- gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes2|0xE0B40000|UINT64|0x00000004
- gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes3|0xE0B60000|UINT64|0x00000005
- gAmdModulePkgTokenSpaceGuid.PcdSataSerdes0|0xE1200000|UINT64|0x00000006
- gAmdModulePkgTokenSpaceGuid.PcdSataSerdes1|0xE1210000|UINT64|0x00000007
- gAmdModulePkgTokenSpaceGuid.PcdSataSerdes2|0xE1220000|UINT64|0x00000008
- gAmdModulePkgTokenSpaceGuid.PcdSataSerdes3|0xE1230000|UINT64|0x00000009
- gAmdModulePkgTokenSpaceGuid.PcdEthernetSerdes|0xE1240000|UINT64|0x0000000a
- gAmdModulePkgTokenSpaceGuid.PcdSataMMU401|0xE0200000|UINT64|0x0000000b
- gAmdModulePkgTokenSpaceGuid.PcdDMA330MMU401|0xE0400000|UINT64|0x0000000c
- gAmdModulePkgTokenSpaceGuid.PcdCCN504Space|0xE8000000|UINT64|0x0000000d
- gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes|2|UINT8|0x0000000e
- gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase|0xE1200000|UINT32|0x0000000f
- gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset|0x00010000|UINT32|0x00000010
-
- gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp|FALSE|BOOLEAN|0x00000033
-
-#XGMAC ETH0 MAC
- gAmdModulePkgTokenSpaceGuid.PcdEthMacA|0|UINT64|0x0000011
-#XGMAC ETH1 MAC
- gAmdModulePkgTokenSpaceGuid.PcdEthMacB|0|UINT64|0x0000012
-
- gAmdModulePkgTokenSpaceGuid.PcdPort0PhyMode|1|UINT8|0x0000013
- gAmdModulePkgTokenSpaceGuid.PcdPort1PhyMode|1|UINT8|0x0000014
- gAmdModulePkgTokenSpaceGuid.PcdPort0NetSpeed|1|UINT8|0x0000015
- gAmdModulePkgTokenSpaceGuid.PcdPort1NetSpeed|1|UINT8|0x0000016
- gAmdModulePkgTokenSpaceGuid.PcdXgbeEnable|FALSE|BOOLEAN|0x0000017
-
- gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|0|UINT8|0x00000018
- gAmdModulePkgTokenSpaceGuid.PcdPcieGenMax|2|UINT8|0x00000019
- gAmdModulePkgTokenSpaceGuid.PcdIocClockGating|1|UINT8|0x0000001a
- gAmdModulePkgTokenSpaceGuid.PcdAifClockGating|1|UINT8|0x0000001b
- gAmdModulePkgTokenSpaceGuid.PcdPcieFuseEnable|TRUE|BOOLEAN|0x000001c
- gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|1|UINT8|0x000001d
- gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1|UINT8|0x000001e
- gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1|UINT8|0x000001f
- gAmdModulePkgTokenSpaceGuid.PcdPcieGen3|0|UINT8|0x00000020
- gAmdModulePkgTokenSpaceGuid.PcdPcieGen2|0|UINT8|0x00000021
- gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|FALSE|BOOLEAN|0x0000022
-
- gAmdModulePkgTokenSpaceGuid.PcdXgbeRev|1|UINT8|0x0000002A
-
- gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen1|31|UINT32|0x0000002B
- gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen2|47|UINT32|0x0000002C
- gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen3|63|UINT32|0x0000002D
- gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen1|31|UINT32|0x0000002E
- gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen2|47|UINT32|0x0000002F
- gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen3|63|UINT32|0x00000030
-
- gAmdModulePkgTokenSpaceGuid.PcdXgbePort0SwKrTrain|0|UINT8|0x00000031
- gAmdModulePkgTokenSpaceGuid.PcdXgbePort1SwKrTrain|0|UINT8|0x00000032
+#** +# @file +# +# AmdModulePkg.dec +# +# AMD-specific package declaration file. +# +# @xrefitem bom "File Content Label" "Release Content" +# @e project: FDK +# @e sub-project: UEFI +# @e version: $Revision: 337482 $ @e date: $Date: 2016-03-11 21:39:02 -0600 (Fri, 11 Mar 2016) $ +# +# +##***************************************************************************** +# +# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#***************************************************************************/ + + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ +[Defines] + DEC_SPECIFICATION = 0x00010005 + PACKAGE_NAME = AmdModulePkg + PACKAGE_GUID = E967965B-4447-4CBB-9521-898B5A329240 + PACKAGE_VERSION = 0.1 + +################################################################################ +# +# Include Section - list of Include Paths that are provided by this package. +# Comments are used for Keywords and Module Types. +# +# Supported Module Types: +# SEC PEIM DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER +# +################################################################################ +[Includes] + Common + Include + Include/Library + Include/Ppi + Include/Protocol + + +[LibraryClasses] + ## @libraryclass Provides a library function to get a DXE driver name + ## + +[Protocols] + gAmdIscpDxeProtocolGuid = { 0x05c794c8, 0x6aef, 0x4450, { 0x91, 0x78, 0xca, 0x70, 0x53, 0x75, 0xbd, 0x91 } } + gAmdRasApeiProtocolGuid = { 0xe9dbcc60, 0x8f93, 0x47ed, { 0x84, 0x78, 0x46, 0x78, 0xf1, 0x9f, 0x73, 0x4a } } + +[Ppis] + gPeiIscpPpiGuid = { 0xca2c1ecd, 0xc702, 0x49b1, { 0xae, 0x24, 0x9b, 0x6f, 0xa8, 0x71, 0x3b, 0x23 } } + gPeiFusePpiGuid = { 0xe074fa9f, 0x1bc7, 0x4af9, { 0x8f, 0x0d, 0x90, 0x0b, 0x76, 0x50, 0x5f, 0xfe } } + gPeiGionbPpiGuid = { 0x24b8ebcc, 0x3871, 0x4b39, { 0xaa, 0x1a, 0x0f, 0x86, 0x7d, 0xbf, 0x97, 0xc6 } } + +[Guids] + gAmdModulePkgTokenSpaceGuid = { 0x2f9003d7, 0xac98, 0x407d, { 0xae, 0x38, 0x9d, 0xbf, 0x81, 0x27, 0xe5, 0xb1 } } + gAmdModulePkgVariableGuid = { 0xf3dd4189, 0xe1b7, 0x49da, { 0xa5, 0xd3, 0x34, 0x28, 0x6f, 0xae, 0x2f, 0x01 } } + +[PcdsFixedAtBuild] + gAmdModulePkgTokenSpaceGuid.PcdFdkVersionMajor|0x1|UINT8|0x00000026 + gAmdModulePkgTokenSpaceGuid.PcdFdkVersionMinor|0x0|UINT8|0x00000027 + gAmdModulePkgTokenSpaceGuid.PcdFdkVersionPoint|0x0|UINT8|0x00000028 + gAmdModulePkgTokenSpaceGuid.PcdFdkVersionSubpoint|0x2|UINT8|0x00000029 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + gAmdModulePkgTokenSpaceGuid.PcdCCPBase|0xE0100000|UINT64|0x00000001 + gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes0|0xE0B00000|UINT64|0x00000002 + gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes1|0xE0B20000|UINT64|0x00000003 + gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes2|0xE0B40000|UINT64|0x00000004 + gAmdModulePkgTokenSpaceGuid.PcdPcieSerdes3|0xE0B60000|UINT64|0x00000005 + gAmdModulePkgTokenSpaceGuid.PcdSataSerdes0|0xE1200000|UINT64|0x00000006 + gAmdModulePkgTokenSpaceGuid.PcdSataSerdes1|0xE1210000|UINT64|0x00000007 + gAmdModulePkgTokenSpaceGuid.PcdSataSerdes2|0xE1220000|UINT64|0x00000008 + gAmdModulePkgTokenSpaceGuid.PcdSataSerdes3|0xE1230000|UINT64|0x00000009 + gAmdModulePkgTokenSpaceGuid.PcdEthernetSerdes|0xE1240000|UINT64|0x0000000a + gAmdModulePkgTokenSpaceGuid.PcdSataMMU401|0xE0200000|UINT64|0x0000000b + gAmdModulePkgTokenSpaceGuid.PcdDMA330MMU401|0xE0400000|UINT64|0x0000000c + gAmdModulePkgTokenSpaceGuid.PcdCCN504Space|0xE8000000|UINT64|0x0000000d + gAmdModulePkgTokenSpaceGuid.PcdSataNumChPerSerdes|2|UINT8|0x0000000e + gAmdModulePkgTokenSpaceGuid.PcdSataSerdesBase|0xE1200000|UINT32|0x0000000f + gAmdModulePkgTokenSpaceGuid.PcdSataSerdesOffset|0x00010000|UINT32|0x00000010 + + gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp|FALSE|BOOLEAN|0x00000033 + +#XGMAC ETH0 MAC + gAmdModulePkgTokenSpaceGuid.PcdEthMacA|0|UINT64|0x0000011 +#XGMAC ETH1 MAC + gAmdModulePkgTokenSpaceGuid.PcdEthMacB|0|UINT64|0x0000012 + + gAmdModulePkgTokenSpaceGuid.PcdPort0PhyMode|1|UINT8|0x0000013 + gAmdModulePkgTokenSpaceGuid.PcdPort1PhyMode|1|UINT8|0x0000014 + gAmdModulePkgTokenSpaceGuid.PcdPort0NetSpeed|1|UINT8|0x0000015 + gAmdModulePkgTokenSpaceGuid.PcdPort1NetSpeed|1|UINT8|0x0000016 + gAmdModulePkgTokenSpaceGuid.PcdXgbeEnable|FALSE|BOOLEAN|0x0000017 + + gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|0|UINT8|0x00000018 + gAmdModulePkgTokenSpaceGuid.PcdPcieGenMax|2|UINT8|0x00000019 + gAmdModulePkgTokenSpaceGuid.PcdIocClockGating|1|UINT8|0x0000001a + gAmdModulePkgTokenSpaceGuid.PcdAifClockGating|1|UINT8|0x0000001b + gAmdModulePkgTokenSpaceGuid.PcdPcieFuseEnable|TRUE|BOOLEAN|0x000001c + gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|1|UINT8|0x000001d + gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1|UINT8|0x000001e + gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1|UINT8|0x000001f + gAmdModulePkgTokenSpaceGuid.PcdPcieGen3|0|UINT8|0x00000020 + gAmdModulePkgTokenSpaceGuid.PcdPcieGen2|0|UINT8|0x00000021 + gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|FALSE|BOOLEAN|0x0000022 + + gAmdModulePkgTokenSpaceGuid.PcdXgbeRev|1|UINT8|0x0000002A + + gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen1|31|UINT32|0x0000002B + gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen2|47|UINT32|0x0000002C + gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen3|63|UINT32|0x0000002D + gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen1|31|UINT32|0x0000002E + gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen2|47|UINT32|0x0000002F + gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen3|63|UINT32|0x00000030 + + gAmdModulePkgTokenSpaceGuid.PcdXgbePort0SwKrTrain|0|UINT8|0x00000031 + gAmdModulePkgTokenSpaceGuid.PcdXgbePort1SwKrTrain|0|UINT8|0x00000032 diff --git a/Silicon/AMD/Styx/AmdModulePkg/Common/CoreState.h b/Silicon/AMD/Styx/AmdModulePkg/Common/CoreState.h index 7ce4998..6e7c666 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Common/CoreState.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Common/CoreState.h @@ -1,66 +1,66 @@ -/* $NoKeywords */
-/**
- * @file
- *
- * CoreState.h
- *
- * CPU Core State Structures and Definitions.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
- *
- */
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-//#########################################################################
-//#########################################################################
-//#########################################################################
-// NOTE: This file shared between SCP and UEFI, make sure all //
-// changes are reflected in both copies. //
-//#########################################################################
-//#########################################################################
-//#########################################################################
-
-#ifndef CORESTATUS_H_
-#define CORESTATUS_H_
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-/// Core State Enumeration
-typedef enum {
- CPU_CORE_UNDEFINED = 0, ///< Core is undefined
- CPU_CORE_DISABLED, ///< Core is disabled
- CPU_CORE_POWERUP, ///< Core/cluster is powered up
- CPU_CORE_POWERDOWN, ///< Core/cluster is powered down
- CPU_CORE_RESET, ///< Core is powered but in reset
- CPU_CORE_RUN, ///< Core is running
- CPU_CORE_SLEEP, ///< Core is powered and sleeping (TBD)
-} CPU_CORE_STATE;
-
-/// SOC Core Status Structure
-typedef struct {
- UINT32 ClusterId; ///< CPU Cluster ID
- UINT32 CoreId; ///< CPU Core ID
- CPU_CORE_STATE Status; ///< Core State Enumeration
- UINT64 ResetVector; ///< CPU Core Reset Vector
-} SocCoreStatus;
-
-#endif /* CORESTATUS_H_ */
+/* $NoKeywords */ +/** + * @file + * + * CoreState.h + * + * CPU Core State Structures and Definitions. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $ + * + */ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ +//######################################################################### +//######################################################################### +//######################################################################### +// NOTE: This file shared between SCP and UEFI, make sure all // +// changes are reflected in both copies. // +//######################################################################### +//######################################################################### +//######################################################################### + +#ifndef CORESTATUS_H_ +#define CORESTATUS_H_ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +/// Core State Enumeration +typedef enum { + CPU_CORE_UNDEFINED = 0, ///< Core is undefined + CPU_CORE_DISABLED, ///< Core is disabled + CPU_CORE_POWERUP, ///< Core/cluster is powered up + CPU_CORE_POWERDOWN, ///< Core/cluster is powered down + CPU_CORE_RESET, ///< Core is powered but in reset + CPU_CORE_RUN, ///< Core is running + CPU_CORE_SLEEP, ///< Core is powered and sleeping (TBD) +} CPU_CORE_STATE; + +/// SOC Core Status Structure +typedef struct { + UINT32 ClusterId; ///< CPU Cluster ID + UINT32 CoreId; ///< CPU Core ID + CPU_CORE_STATE Status; ///< Core State Enumeration + UINT64 ResetVector; ///< CPU Core Reset Vector +} SocCoreStatus; + +#endif /* CORESTATUS_H_ */ diff --git a/Silicon/AMD/Styx/AmdModulePkg/Common/CpuIscp.h b/Silicon/AMD/Styx/AmdModulePkg/Common/CpuIscp.h index ca86894..e95b905 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Common/CpuIscp.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Common/CpuIscp.h @@ -1,492 +1,492 @@ -/* $NoKeywords */
-/**
- * @file
- *
- * MemIscp.h
- *
- * Contains common Memory Training ISCP-related structures and defines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e version: $Revision: 317558 $ @e date: $Date: 2015-04-24 17:20:55 -0700 (Fri, 24 Apr 2015) $
- *
- */
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-
-//#########################################################################
-//#########################################################################
-//#########################################################################
-// NOTE: This file shared between SCP and UEFI, make sure all //
-// changes are reflected in both copies. //
-//#########################################################################
-//#########################################################################
-//#########################################################################
-
-#ifndef CPUISCP_H_
-#define CPUISCP_H_
-
-#ifdef __cplusplus
- extern "C" {
- #endif
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
- #include <ProcessorBind.h> // Included just so this file can be built into both the RTOS
- // and UEFI without needing separate copies for both build
- // environments.
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
- /// Processor ID
- typedef struct {
- UINT32 ProcIDMsd; ///< Processor ID Msd
- UINT32 ProcIDLsd; ///< Processor ID Lsd
- } ISCP_PROC_ID;
-
- /// Processor Type
- typedef enum {
- ISCP_CPU_TYPE_OTHER = 1, ///< Other
- ISCP_CPU_TYPE_UNKNOWN, ///< Unknown
- ISCP_CPU_TYPE_CENTRAL_PROCESSOR, ///< Central Processor
- ISCP_CPU_TYPE_MATH_COPROCESSOR, ///< Math Coprocessor
- ISCP_CPU_TYPE_DSP_PROCESSOR, ///< DSP Processor
- ISCP_CPU_TYPE_VIDEO_PROCESSOR ///< Video Processor
- } ISCP_PROCESSOR_TYPE;
-
- /// Processor Information - Processor Family.
- typedef enum {
- ISCP_ProcessorFamilyOther = 0x01, ///< Processor Family - Other
- ISCP_ProcessorFamilyUnknown = 0x02, ///< Processor Family - Unknown
- ISCP_ProcessorFamily8086 = 0x03, ///< Processor Family - 8086
- ISCP_ProcessorFamily80286 = 0x04, ///< Processor Family - 80286
- ISCP_ProcessorFamilyIntel386 = 0x05, ///< Processor Family - Intel 386
- ISCP_ProcessorFamilyIntel486 = 0x06, ///< Processor Family - Intel 486
- ISCP_ProcessorFamily8087 = 0x07, ///< Processor Family - 8087
- ISCP_ProcessorFamily80287 = 0x08, ///< Processor Family - 80287
- ISCP_ProcessorFamily80387 = 0x09, ///< Processor Family - 80387
- ISCP_ProcessorFamily80487 = 0x0A, ///< Processor Family - 80487
- ISCP_ProcessorFamilyPentium = 0x0B, ///< Processor Family - Pentium
- ISCP_ProcessorFamilyPentiumPro = 0x0C, ///< Processor Family - Pentium Pro
- ISCP_ProcessorFamilyPentiumII = 0x0D, ///< Processor Family - Pentium II
- ISCP_ProcessorFamilyPentiumMMX = 0x0E, ///< Processor Family - Pentium MMX
- ISCP_ProcessorFamilyCeleron = 0x0F, ///< Processor Family - Celeron
- ISCP_ProcessorFamilyPentiumIIXeon = 0x10, ///< Processor Family - Pentium II Xeon
- ISCP_ProcessorFamilyPentiumIII = 0x11, ///< Processor Family - Pentium III
- ISCP_ProcessorFamilyM1 = 0x12, ///< Processor Family - M1
- ISCP_ProcessorFamilyM2 = 0x13, ///< Processor Family - M2
- ISCP_ProcessorFamilyIntelCeleronM = 0x14, ///< Processor Family - Intel Celeron
- ISCP_ProcessorFamilyIntelPentium4Ht = 0x15, ///< Processor Family - Intel Pentium 4Ht
- ISCP_ProcessorFamilyAmdDuron = 0x18, ///< Processor Family - AMD Duron
- ISCP_ProcessorFamilyK5 = 0x19, ///< Processor Family - K5
- ISCP_ProcessorFamilyK6 = 0x1A, ///< Processor Family - K6
- ISCP_ProcessorFamilyK6_2 = 0x1B, ///< Processor Family - K6-2
- ISCP_ProcessorFamilyK6_3 = 0x1C, ///< Processor Family - K6-3
- ISCP_ProcessorFamilyAmdAthlon = 0x1D, ///< Processor Family - AMD Athlon
- ISCP_ProcessorFamilyAmd29000 = 0x1E, ///< Processor Family - AMD 29000
- ISCP_ProcessorFamilyK6_2Plus = 0x1F, ///< Processor Family - K6-2 Plus
- ISCP_ProcessorFamilyPowerPC = 0x20, ///< Processor Family - Power PC
- ISCP_ProcessorFamilyPowerPC601 = 0x21, ///< Processor Family - Power PC 601
- ISCP_ProcessorFamilyPowerPC603 = 0x22, ///< Processor Family - Power PC 603
- ISCP_ProcessorFamilyPowerPC603Plus = 0x23, ///< Processor Family - Power PC 603 Plus
- ISCP_ProcessorFamilyPowerPC604 = 0x24, ///< Processor Family - Power PC 604
- ISCP_ProcessorFamilyPowerPC620 = 0x25, ///< Processor Family - Power PC 620
- ISCP_ProcessorFamilyPowerPCx704 = 0x26, ///< Processor Family - Power PC x704
- ISCP_ProcessorFamilyPowerPC750 = 0x27, ///< Processor Family - Power PC 750
- ISCP_ProcessorFamilyIntelCoreDuo = 0x28, ///< Processor Family - Intel Core Duo
- ISCP_ProcessorFamilyIntelCoreDuoMobile = 0x29, ///< Processor Family - Intel core Duo Mobile
- ISCP_ProcessorFamilyIntelCoreSoloMobile = 0x2A, ///< Processor Family - Intel Core Solo Mobile
- ISCP_ProcessorFamilyIntelAtom = 0x2B, ///< Processor Family - Intel Atom
- ISCP_ProcessorFamilyAlpha = 0x30, ///< Processor Family - Alpha
- ISCP_ProcessorFamilyAlpha21064 = 0x31, ///< Processor Family - Alpha 21064
- ISCP_ProcessorFamilyAlpha21066 = 0x32, ///< Processor Family - Alpha 21166
- ISCP_ProcessorFamilyAlpha21164 = 0x33, ///< Processor Family - Alpha 21164
- ISCP_ProcessorFamilyAlpha21164PC = 0x34, ///< Processor Family - Alpha 21164PC
- ISCP_ProcessorFamilyAlpha21164a = 0x35, ///< Processor Family - Alpha 21164a
- ISCP_ProcessorFamilyAlpha21264 = 0x36, ///< Processor Family - Alpha 21264
- ISCP_ProcessorFamilyAlpha21364 = 0x37, ///< Processor Family - Alpha 21364
- ISCP_ProcessorFamilyAmdTurionIIUltraDualCoreMobileM = 0x38, ///< Processor Family - AMD Turion II Ultra Dual Core Mobile M
- ISCP_ProcessorFamilyAmdTurionIIDualCoreMobileM = 0x39, ///< Processor Family - AMD Turion II Dual Core Mobile M
- ISCP_ProcessorFamilyAmdAthlonIIDualCoreM = 0x3A, ///< Processor Family - AMD Athlon II Dual Core M
- ISCP_ProcessorFamilyAmdOpteron6100Series = 0x3B, ///< Processor Family - AMD Opteron 6100 Series
- ISCP_ProcessorFamilyAmdOpteron4100Series = 0x3C, ///< Processor Family - AMD Opteron 4100 Series
- ISCP_ProcessorFamilyAmdOpteron6200Series = 0x3D, ///< Processor Family - AMD Opteron 6200 Series
- ISCP_ProcessorFamilyAmdOpteron4200Series = 0x3E, ///< Processor Family - AMD Opteron 4200 Series
- ISCP_ProcessorFamilyAmdFxSeries = 0x3F, ///< Processor Family - AMD FX Series
- ISCP_ProcessorFamilyMips = 0x40, ///< Processor Family - MIPs
- ISCP_ProcessorFamilyMIPSR4000 = 0x41, ///< Processor Family - MIPs R4000
- ISCP_ProcessorFamilyMIPSR4200 = 0x42, ///< Processor Family - MIPs R4200
- ISCP_ProcessorFamilyMIPSR4400 = 0x43, ///< Processor Family - MIPs R4400
- ISCP_ProcessorFamilyMIPSR4600 = 0x44, ///< Processor Family - MIPs R4600
- ISCP_ProcessorFamilyMIPSR10000 = 0x45, ///< Processor Family - MIPs R10000
- ISCP_ProcessorFamilyAmdCSeries = 0x46, ///< Processor Family - AMD C Series
- ISCP_ProcessorFamilyAmdESeries = 0x47, ///< Processor Family - AMD E Series
- ISCP_ProcessorFamilyAmdASeries = 0x48, ///< Processor Family - AMD A Series
- ISCP_ProcessorFamilyAmdGSeries = 0x49, ///< Processor Family - AMD G Series
- ISCP_ProcessorFamilyAmdZSeries = 0x4A, ///< Processor Family - AMD Z Series
- ISCP_ProcessorFamilyAmdRSeries = 0x4B, ///< Processor Family - AMD R Series
- ISCP_ProcessorFamilyAmdOpteron4300 = 0x4C, ///< Processor Family - AMD Opteron 4300
- ISCP_ProcessorFamilyAmdOpteron6300 = 0x4D, ///< Processor Family - AMD Opteron 6300
- ISCP_ProcessorFamilyAmdOpteron3300 = 0x4E, ///< Processor Family - AMD Opteron 3300
- ISCP_ProcessorFamilyAmdFireProSeries = 0x4F, ///< Processor Family - AMD Fire Pro Series
- ISCP_ProcessorFamilySparc = 0x50, ///< Processor Family - Sparc
- ISCP_ProcessorFamilySuperSparc = 0x51, ///< Processor Family - Super Sparc
- ISCP_ProcessorFamilymicroSparcII = 0x52, ///< Processor Family - Sparc II
- ISCP_ProcessorFamilymicroSparcIIep = 0x53, ///< Processor Family - Sparc IIep
- ISCP_ProcessorFamilyUltraSparc = 0x54, ///< Processor Family - Ultra Sparc
- ISCP_ProcessorFamilyUltraSparcII = 0x55, ///< Processor Family - Ultra Sparc II
- ISCP_ProcessorFamilyUltraSparcIii = 0x56, ///< Processor Family - Ultra Sparc Iii
- ISCP_ProcessorFamilyUltraSparcIII = 0x57, ///< Processor Family - Ultra Sparc III
- ISCP_ProcessorFamilyUltraSparcIIIi = 0x58, ///< Processor Family - Ultra Sparc IIIi
- ISCP_ProcessorFamily68040 = 0x60, ///< Processor Family - 68040
- ISCP_ProcessorFamily68xxx = 0x61, ///< Processor Family - 68xxx
- ISCP_ProcessorFamily68000 = 0x62, ///< Processor Family - 68000
- ISCP_ProcessorFamily68010 = 0x63, ///< Processor Family - 68010
- ISCP_ProcessorFamily68020 = 0x64, ///< Processor Family - 68020
- ISCP_ProcessorFamily68030 = 0x65, ///< Processor Family - 68030
- ISCP_ProcessorFamilyAmdOpteronASeries = 0x69, ///< Processor Family - AMD Opteron A Series
- ISCP_ProcessorFamilyHobbit = 0x70, ///< Processor Family - Hobbit
- ISCP_ProcessorFamilyCrusoeTM5000 = 0x78, ///< Processor Family - Crusoe TM5000
- ISCP_ProcessorFamilyCrusoeTM3000 = 0x79, ///< Processor Family - Crusoe TM3000
- ISCP_ProcessorFamilyEfficeonTM8000 = 0x7A, ///< Processor Family - Efficeon TM8000
- ISCP_ProcessorFamilyWeitek = 0x80, ///< Processor Family - Weitek
- ISCP_ProcessorFamilyItanium = 0x82, ///< Processor Family - Itanium
- ISCP_ProcessorFamilyAmdAthlon64 = 0x83, ///< Processor Family - AMD Athlon64
- ISCP_ProcessorFamilyAmdOpteron = 0x84, ///< Processor Family - AMD Opeteron
- ISCP_ProcessorFamilyAmdSempron = 0x85, ///< Processor Family - AMD Sempron
- ISCP_ProcessorFamilyAmdTurion64Mobile = 0x86, ///< Processor Family - AMD Turion 64 Modbile
- ISCP_ProcessorFamilyDualCoreAmdOpteron = 0x87, ///< Processor Family - AMD Dual Core Opteron
- ISCP_ProcessorFamilyAmdAthlon64X2DualCore = 0x88, ///< Processor Family - AMD Athlon 64 X2 Dual Core
- ISCP_ProcessorFamilyAmdTurion64X2Mobile = 0x89, ///< Processor Family - AMD Turion 64 X2 Mobile
- ISCP_ProcessorFamilyQuadCoreAmdOpteron = 0x8A, ///< Processor Family - AMD Quad Core Opteron
- ISCP_ProcessorFamilyThirdGenerationAmdOpteron = 0x8B, ///< Processor Family - AMD 3rd Generation Opteron
- ISCP_ProcessorFamilyAmdPhenomFxQuadCore = 0x8C, ///< Processor Family - AMD Phenom FX Quad Core
- ISCP_ProcessorFamilyAmdPhenomX4QuadCore = 0x8D, ///< Processor Family - AMD Phenom X4 Quad Core
- ISCP_ProcessorFamilyAmdPhenomX2DualCore = 0x8E, ///< Processor Family - AMD Phenom X2 Quad Core
- ISCP_ProcessorFamilyAmdAthlonX2DualCore = 0x8F, ///< Processor Family - AMD Athlon X2 Dual Core
- ISCP_ProcessorFamilyPARISC = 0x90, ///< Processor Family - PARISC
- ISCP_ProcessorFamilyPaRisc8500 = 0x91, ///< Processor Family - PARISC 8500
- ISCP_ProcessorFamilyPaRisc8000 = 0x92, ///< Processor Family - PARISC 8000
- ISCP_ProcessorFamilyPaRisc7300LC = 0x93, ///< Processor Family - PARISC 7300LC
- ISCP_ProcessorFamilyPaRisc7200 = 0x94, ///< Processor Family - PARISC 7200
- ISCP_ProcessorFamilyPaRisc7100LC = 0x95, ///< Processor Family - PARISC 7100LC
- ISCP_ProcessorFamilyPaRisc7100 = 0x96, ///< Processor Family - PARISC 7100
- ISCP_ProcessorFamilyV30 = 0xA0, ///< Processor Family - V30
- ISCP_ProcessorFamilyQuadCoreIntelXeon3200Series = 0xA1, ///< Processor Family - Intel Quad Core Xeon 3200 Series
- ISCP_ProcessorFamilyDualCoreIntelXeon3000Series = 0xA2, ///< Processor Family - Intel Dual Core Xeon 3000 Series
- ISCP_ProcessorFamilyQuadCoreIntelXeon5300Series = 0xA3, ///< Processor Family - Intel Quad Core Xeon 5300 Series
- ISCP_ProcessorFamilyDualCoreIntelXeon5100Series = 0xA4, ///< Processor Family - Intel Dual Core Xeon 5100 Series
- ISCP_ProcessorFamilyDualCoreIntelXeon5000Series = 0xA5, ///< Processor Family - Intel Dual Core Xeon 5000 Series
- ISCP_ProcessorFamilyDualCoreIntelXeonLV = 0xA6, ///< Processor Family - Intel Dual Core Xeon LV
- ISCP_ProcessorFamilyDualCoreIntelXeonULV = 0xA7, ///< Processor Family - Intel Dual Core Xeon ULV
- ISCP_ProcessorFamilyDualCoreIntelXeon7100Series = 0xA8, ///< Processor Family - Intel Quad Core Xeon 7100 Series
- ISCP_ProcessorFamilyQuadCoreIntelXeon5400Series = 0xA9, ///< Processor Family - Intel Quad Core Xeon 5400 Series
- ISCP_ProcessorFamilyQuadCoreIntelXeon = 0xAA, ///< Processor Family - Intel Quad Core Xeon
- ISCP_ProcessorFamilyDualCoreIntelXeon5200Series = 0xAB, ///< Processor Family - Intel Dual Core Xeon 5200 Series
- ISCP_ProcessorFamilyDualCoreIntelXeon7200Series = 0xAC, ///< Processor Family - Intel Dual Core Xeon 7200 Series
- ISCP_ProcessorFamilyQuadCoreIntelXeon7300Series = 0xAD, ///< Processor Family - Intel Quad Core Xeon 7300 Series
- ISCP_ProcessorFamilyQuadCoreIntelXeon7400Series = 0xAE, ///< Processor Family - Intel Quad Core Xeon 7400 Series
- ISCP_ProcessorFamilyMultiCoreIntelXeon7400Series = 0xAF, ///< Processor Family - Intel Multi-Core Xeon 7400 Series
- ISCP_ProcessorFamilyPentiumIIIXeon = 0xB0, ///< Processor Family - Intel Pentium III Xeon
- ISCP_ProcessorFamilyPentiumIIISpeedStep = 0xB1, ///< Processor Family - Intel Pentium III Speed Step
- ISCP_ProcessorFamilyPentium4 = 0xB2, ///< Processor Family - Pentium 4
- ISCP_ProcessorFamilyIntelXeon = 0xB3, ///< Processor Family - Intel Xeon
- ISCP_ProcessorFamilyAS400 = 0xB4, ///< Processor Family - AS400
- ISCP_ProcessorFamilyIntelXeonMP = 0xB5, ///< Processor Family - Intel Xeon MP
- ISCP_ProcessorFamilyAMDAthlonXP = 0xB6, ///< Processor Family - AMD Athlon XP
- ISCP_ProcessorFamilyAMDAthlonMP = 0xB7, ///< Processor Family - AMD Athlon MP
- ISCP_ProcessorFamilyIntelItanium2 = 0xB8, ///< Processor Family - Intel Itanum2
- ISCP_ProcessorFamilyIntelPentiumM = 0xB9, ///< Processor Family - Intel Pentium M
- ISCP_ProcessorFamilyIntelCeleronD = 0xBA, ///< Processor Family - Intel Celeron D
- ISCP_ProcessorFamilyIntelPentiumD = 0xBB, ///< Processor Family - Intel Pentium D
- ISCP_ProcessorFamilyIntelPentiumEx = 0xBC, ///< Processor Family - Intel pentium Ex
- ISCP_ProcessorFamilyIntelCoreSolo = 0xBD, ///< Processor Family - Intel Core Solo
- ISCP_ProcessorFamilyReserved = 0xBE, ///< Processor Family - Reserved
- ISCP_ProcessorFamilyIntelCore2 = 0xBF, ///< Processor Family - Intel Core 2
- ISCP_ProcessorFamilyIntelCore2Solo = 0xC0, ///< Processor Family - Intel Core 2 Solo
- ISCP_ProcessorFamilyIntelCore2Extreme = 0xC1, ///< Processor Family - Intel Core 2 Extreme
- ISCP_ProcessorFamilyIntelCore2Quad = 0xC2, ///< Processor Family - Intel Core 2 Quad
- ISCP_ProcessorFamilyIntelCore2ExtremeMobile = 0xC3, ///< Processor Family - Intel Core 2 Extremem Mobile
- ISCP_ProcessorFamilyIntelCore2DuoMobile = 0xC4, ///< Processor Family - Intel core 2 Duo Mobile
- ISCP_ProcessorFamilyIntelCore2SoloMobile = 0xC5, ///< Processor Family - Intel Core 2 Solo Mobile
- ISCP_ProcessorFamilyIntelCoreI7 = 0xC6, ///< Processor Family - Intel Core I7
- ISCP_ProcessorFamilyDualCoreIntelCeleron = 0xC7, ///< Processor Family - Intel Dual Core Celeron
- ISCP_ProcessorFamilyIBM390 = 0xC8, ///< Processor Family - IBM 390
- ISCP_ProcessorFamilyG4 = 0xC9, ///< Processor Family - G4
- ISCP_ProcessorFamilyG5 = 0xCA, ///< Processor Family - G5
- ISCP_ProcessorFamilyG6 = 0xCB, ///< Processor Family - G6
- ISCP_ProcessorFamilyzArchitecture = 0xCC, ///< Processor Family - zArchitecture
- ISCP_ProcessorFamilyIntelCoreI5 = 0xCD, ///< Processor Family - Intel Core I5
- ISCP_ProcessorFamilyIntelCoreI3 = 0xCE, ///< Processor Family - Intel Core I3
- ISCP_ProcessorFamilyViaC7M = 0xD2, ///< Processor Family - Via C7M
- ISCP_ProcessorFamilyViaC7D = 0xD3, ///< Processor Family - Via C7D
- ISCP_ProcessorFamilyViaC7 = 0xD4, ///< Processor Family - Via C7
- ISCP_ProcessorFamilyViaEden = 0xD5, ///< Processor Family - Via Eden
- ISCP_ProcessorFamilyMultiCoreIntelXeon = 0xD6, ///< Processor Family - Intel Multi-core Xeon
- ISCP_ProcessorFamilyDualCoreIntelXeon3Series = 0xD7, ///< Processor Family - Intel Dual-core Xeon 3-Series
- ISCP_ProcessorFamilyQuadCoreIntelXeon3Series = 0xD8, ///< Processor Family - Intel Quad-core Xeon 3-Series
- ISCP_ProcessorFamilyViaNano = 0xD9, ///< Processor Family - Via Nano
- ISCP_ProcessorFamilyDualCoreIntelXeon5Series = 0xDA, ///< Processor Family - Intel Dual-core Xeon 5-Series
- ISCP_ProcessorFamilyQuadCoreIntelXeon5Series = 0xDB, ///< Processor Family - Intel Quad-core Xeon 5-Series
- ISCP_ProcessorFamilyDualCoreIntelXeon7Series = 0xDD, ///< Processor Family - Intel Dual-core Xeon 7-Series
- ISCP_ProcessorFamilyQuadCoreIntelXeon7Series = 0xDE, ///< Processor Family - Intel Quad-core Xeon 7-Series
- ISCP_ProcessorFamilyMultiCoreIntelXeon7Series = 0xDF, ///< Processor Family - Intel Multi-core Xeon 7-Series
- ISCP_ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0, ///< Processor Family - Intel Multi-core Xeon 3400-Series
- ISCP_ProcessorFamilyAmdOpteron3000Series = 0xE4, ///< Processor Family - AMD Opteron 3000 Series
- ISCP_ProcessorFamilyAmdSempronII = 0xE5, ///< Processor Family - AMD Sempron II
- ISCP_ProcessorFamilyEmbeddedAmdOpteronQuadCore = 0xE6, ///< Processor Family - AMD Embedded Opteron Quad Core
- ISCP_ProcessorFamilyAmdPhenomTripleCore = 0xE7, ///< Processor Family - AMD Phonon Triple Core
- ISCP_ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8, ///< Processor Family - AMD Turion Ultra Dual Core Mobile
- ISCP_ProcessorFamilyAmdTurionDualCoreMobile = 0xE9, ///< Processor Family - AMD Turion Dual Core Mobile
- ISCP_ProcessorFamilyAmdAthlonDualCore = 0xEA, ///< Processor Family - AMD Turion Dual Core Mobile
- ISCP_ProcessorFamilyAmdSempronSI = 0xEB, ///< Processor Family - AMD Sempron SI
- ISCP_ProcessorFamilyAmdPhenomII = 0xEC, ///< Processor Family - AMD Phenon II
- ISCP_ProcessorFamilyAmdAthlonII = 0xED, ///< Processor Family - AMD Athlon II
- ISCP_ProcessorFamilySixCoreAmdOpteron = 0xEE, ///< Processor Family - AMD 6-Core Opteron
- ISCP_ProcessorFamilyAmdSempronM = 0xEF, ///< Processor Family - AMD Sempon M
- ISCP_ProcessorFamilyi860 = 0xFA, ///< Processor Family - i860
- ISCP_ProcessorFamilyi960 = 0xFB, ///< Processor Family - i960
- ISCP_ProcessorFamilyIndicatorFamily2 = 0xFE, ///< Processor Family - Indicator Family 2
- ISCP_ProcessorFamilyReserved1 = 0xFF ///< Processor Family - Reserved
- } ISCP_PROCESSOR_FAMILY_DATA;
-
- /// Processor Information2 - Processor Family2.
- typedef enum {
- ISCP_ProcessorFamilySH3 = 0x0104, ///< ProcessorFamily - SH3
- ISCP_ProcessorFamilySH4 = 0x0105, ///< ProcessorFamily - SH4
- ISCP_ProcessorFamilyARM = 0x0118, ///< ProcessorFamily - ARM
- ISCP_ProcessorFamilyStrongARM = 0x0119, ///< ProcessorFamily - Strong ARM
- ISCP_ProcessorFamily6x86 = 0x012C, ///< ProcessorFamily - x86
- ISCP_ProcessorFamilyMediaGX = 0x012D, ///< ProcessorFamily - Media GX
- ISCP_ProcessorFamilyMII = 0x012E, ///< ProcessorFamily - MII
- ISCP_ProcessorFamilyWinChip = 0x0140, ///< ProcessorFamily - WinChip
- ISCP_ProcessorFamilyDSP = 0x015E, ///< ProcessorFamily - DSP
- ISCP_ProcessorFamilyVideoProcessor = 0x01F4 ///< ProcessorFamily - Video Processor
- } ISCP_PROCESSOR_FAMILY2_DATA;
-
- /// Processor Information - Processor Upgrade.
- typedef enum {
- ISCP_ProcessorUpgradeOther = 0x01, ///< Processor Upgrade - Other
- ISCP_ProcessorUpgradeUnknown = 0x02, ///< Processor Upgrade - Unknown
- ISCP_ProcessorUpgradeDaughterBoard = 0x03, ///< Processor Upgrade - Daughter Board
- ISCP_ProcessorUpgradeZIFSocket = 0x04, ///< Processor Upgrade - ZIF Socket
- ISCP_ProcessorUpgradePiggyBack = 0x05, ///< Processor Upgrade - Piggyback
- ISCP_ProcessorUpgradeNone = 0x06, ///< Processor Upgrade - None
- ISCP_ProcessorUpgradeLIFSocket = 0x07, ///< Processor Upgrade - LIF Socket
- ISCP_ProcessorUpgradeSlot1 = 0x08, ///< Processor Upgrade - Slot 1
- ISCP_ProcessorUpgradeSlot2 = 0x09, ///< Processor Upgrade - Slot 2
- ISCP_ProcessorUpgrade370PinSocket = 0x0A, ///< Processor Upgrade - 370 Pin Socket
- ISCP_ProcessorUpgradeSlotA = 0x0B, ///< Processor Upgrade - Slot A
- ISCP_ProcessorUpgradeSlotM = 0x0C, ///< Processor Upgrade - Slot M
- ISCP_ProcessorUpgradeSocket423 = 0x0D, ///< Processor Upgrade - Socket 423
- ISCP_ProcessorUpgradeSocketA = 0x0E, ///< Processor Upgrade - Socket A
- ISCP_ProcessorUpgradeSocket478 = 0x0F, ///< Processor Upgrade - Socket 478
- ISCP_ProcessorUpgradeSocket754 = 0x10, ///< Processor Upgrade - Socket 754
- ISCP_ProcessorUpgradeSocket940 = 0x11, ///< Processor Upgrade - Socket 940
- ISCP_ProcessorUpgradeSocket939 = 0x12, ///< Processor Upgrade - Socket 939
- ISCP_ProcessorUpgradeSocketmPGA604 = 0x13, ///< Processor Upgrade - PGA 604
- ISCP_ProcessorUpgradeSocketLGA771 = 0x14, ///< Processor Upgrade - LGA 771
- ISCP_ProcessorUpgradeSocketLGA775 = 0x15, ///< Processor Upgrade - LGA 775
- ISCP_ProcessorUpgradeSocketS1 = 0x16, ///< Processor Upgrade - S1
- ISCP_ProcessorUpgradeAM2 = 0x17, ///< Processor Upgrade - AM2
- ISCP_ProcessorUpgradeF1207 = 0x18, ///< Processor Upgrade - F1207
- ISCP_ProcessorSocketLGA1366 = 0x19, ///< Processor Upgrade - LGA 1366
- ISCP_ProcessorUpgradeSocketG34 = 0x1A, ///< Processor Upgrade - G34
- ISCP_ProcessorUpgradeSocketAM3 = 0x1B, ///< Processor Upgrade - AM3
- ISCP_ProcessorUpgradeSocketC32 = 0x1C, ///< Processor Upgrade - C32
- ISCP_ProcessorUpgradeSocketLGA1156 = 0x1D, ///< Processor Upgrade - LGA 1156
- ISCP_ProcessorUpgradeSocketLGA1567 = 0x1E, ///< Processor Upgrade - LGA 1567
- ISCP_ProcessorUpgradeSocketPGA988A = 0x1F, ///< Processor Upgrade - PGA 988A
- ISCP_ProcessorUpgradeSocketBGA1288 = 0x20, ///< Processor Upgrade - PGA 1288
- ISCP_ProcessorUpgradeSocketrPGA988B = 0x21, ///< Processor Upgrade - PGA 988B
- ISCP_ProcessorUpgradeSocketBGA1023 = 0x22, ///< Processor Upgrade - BGA 1023
- ISCP_ProcessorUpgradeSocketBGA1224 = 0x23, ///< Processor Upgrade - BGA 1224
- ISCP_ProcessorUpgradeSocketLGA1155 = 0x24, ///< Processor Upgrade - LGA 1155
- ISCP_ProcessorUpgradeSocketLGA1356 = 0x25, ///< Processor Upgrade - LGA 1356
- ISCP_ProcessorUpgradeSocketLGA2011 = 0x26, ///< Processor Upgrade - LGA 2011
- ISCP_ProcessorUpgradeSocketFS1 = 0x27, ///< Processor Upgrade - FS1
- ISCP_ProcessorUpgradeSocketFS2 = 0x28, ///< Processor Upgrade - FS2
- ISCP_ProcessorUpgradeSocketFM1 = 0x29, ///< Processor Upgrade - FM1
- ISCP_ProcessorUpgradeSocketFM2 = 0x2A, ///< Processor Upgrade - FM2
- ISCP_ProcessorUpgradeSocketLGA2011_3 = 0x2B, ///< Processor Upgrade - LGA 2011-3
- ISCP_ProcessorUpgradeSocketLGA1356_3 = 0x2C ///< Processor Upgrade - LGA 1356-3
- } ISCP_PROCESSOR_UPGRADE;
-
- /// CPU Information - Characteristics.
- typedef struct {
- UINT16 Reserved0 :1; ///< CPU Information - Reserved
- UINT16 Unknown :1; ///< CPU Information - Unknown
- UINT16 Capable64Bit :1; ///< CPU Information - Capable 64-Bit
- UINT16 MultiCore :1; ///< CPU Information - Multi-core
- UINT16 HardwareThread :1; ///< CPU Information - Hardware Thread
- UINT16 ExecuteProtection :1; ///< CPU Information - Execute Protection
- UINT16 EnhancedVirtualization :1; ///< CPU Information - Enhanced Virtualization
- UINT16 PowerPerformanceControl :1; ///< CPU Information - Power Performance Control
- UINT16 Reserved8_15 :8; ///< CPU Information - Reserved
- } ISCP_PROCESSOR_CHARACTERISTICS;
-
- /// CPU Information - CPU Status.
- typedef enum {
- ISCP_CPU_STATUS_UNKNOWN = 0, ///< CPU Status - Unknown
- ISCP_CPU_STATUS_ENABLED, ///< CPU Status - Enabled
- ISCP_CPU_STATUS_DISABLED_BY_USER, ///< CPU Status - Disabled by user
- ISCP_CPU_STATUS_DISABLED_BY_BIOS, ///< CPU Status - Disabled by BIOS
- ISCP_CPU_STATUS_IDLE, ///< CPU Status - Idle
- ISCP_CPU_STATUS_RESERVED_5, ///< CPU Status - Reserved
- ISCP_CPU_STATUS_RESERVED_6, ///< CPU Status - Reserved
- ISCP_CPU_STATUS_OTHER ///< CPU Status - Other
- } ISCP_CPU_STATUS;
-
-
- /// CPU Information - Status.
- typedef struct {
- UINT16 CpuStatus :3; ///< CPU Status
- UINT16 Reserved3_5 :3; ///< Reserved Bits[5:3]
- UINT16 CpuSocketPopulated :1; ///< CPU Socket Populated
- UINT16 Reserved7_15 :9; ///< Reserved Bits[15:9]
- } PROCESSOR_STATUS;
-
- /// Cache Information - Operation Mode.
- typedef enum {
- ISCP_CACHE_OPERATION_MODE_WRITE_THROUGH = 0, ///< Cache Operation Mode Write Through
- ISCP_CACHE_OPERATION_MODE_WRITE_BACK, ///< Cache Operation Mode Write Back
- ISCP_CACHE_OPERATION_MODE_VARIES_WITH_MEMORY_ADDRESS, ///< Cache Operation Mode Varies with Memory Address
- ISCP_CACHE_OPERATION_MODE_UNKNOWN, ///< Cache Operation Mode Unknown
- } ISCP_CACHE_OPERATION_MODE;
-
- /// Cache Information - Location.
- typedef enum {
- ISCP_CACHE_LOCATION_INTERNAL = 0, ///< Cache Location Internal
- ISCP_CACHE_LOCATION_EXTERNAL, ///< Cache Location External
- ISCP_CACHE_LOCATION_RESERVED, ///< Cache Location Reserved
- ISCP_CACHE_LOCATION_UNKNOWN, ///< Cache Location Unknown
- } ISCP_CACHE_LOCATION;
-
- /// Cache Information - Level.
- typedef enum {
- ISCP_CACHE_LEVEL_1 = 0, ///< Cache Level 1
- ISCP_CACHE_LEVEL_2, ///< Cache Level 2
- ISCP_CACHE_LEVEL_3, ///< Cache Level 3
- ISCP_CACHE_LEVEL_4, ///< Cache Level 4
- } ISCP_CACHE_LEVEL;
-
- /// Cache Information - Configuration.
- typedef struct {
- UINT16 CacheLevel :3; ///< Cache Level
- UINT16 CacheSocketd :1; ///< Cache Socket ID
- UINT16 Reserved_4 :1; ///< Cache Reserved
- UINT16 Location :2; ///< Cache Location
- UINT16 EnabledDisabled :1; ///< Cache Enabled / Disabled
- UINT16 OperationMode :2; ///< Operation Mode
- UINT16 Reserved10_15 :6; ///< Cache Reserved
- } ISCP_CACHE_CONFIGURATION;
-
- /// Cache Information - SRAM Type.
- typedef struct {
- UINT16 Other :1; ///< SRAM Type - Other
- UINT16 Unknown :1; ///< SRAM Type - Unknown
- UINT16 NonBurst :1; ///< SRAM Type - NonBurst
- UINT16 Burst :1; ///< SRAM Type - Burst
- UINT16 PipelineBurst :1; ///< SRAM Type - Pipeline Burst
- UINT16 Synchronous :1; ///< SRAM Type - Synchronous
- UINT16 Asynchronous :1; ///< SRAM Type - Asynchronous
- UINT16 Reserved7_15 :9; ///< SRAM Type - Reserved
- } ISCP_CACHE_SRAM_TYPE;
-
- /// Cache Information - Error Correction Type.
- typedef enum {
- ISCP_ECC_TYPE_OTHER = 1, ///< ECC Type - Other
- ISCP_ECC_TYPE_UNKNOWN, ///< ECC Type - Unknown
- ISCP_ECC_TYPE_NONE, ///< ECC Type - None
- ISCP_ECC_TYPE_PARITY, ///< ECC Type - Parity
- ISCP_ECC_TYPE_SINGLE_BIT, ///< ECC Type - Single-Bit
- ISCP_ECC_TYPE_MULTI_BIT ///< ECC Type - Multi-Bit
- } ISCP_CACHE_ECC_TYPE;
-
- /// Cache Information - System Cache Type.
- typedef enum {
- ISCP_SYSTEM_CACHE_TYPE_OTHER = 1, ///< System Cache Type - Other
- ISCP_SYSTEM_CACHE_TYPE_UNKNOWN, ///< System Cache Type - Unknown
- ISCP_SYSTEM_CACHE_TYPE_INSTRUCTION, ///< System Cache Type - Instruction
- ISCP_SYSTEM_CACHE_TYPE_DATA, ///< System Cache Type - Data
- ISCP_SYSTEM_CACHE_TYPE_UNIFIED ///< System Cache Type - Unified
- } ISCP_SYSTEM_CACHE_TYPE;
-
- /// Cache Information - Associativity.
- typedef enum {
- ISCP_CACHE_ASSOCIATIVITY_OTHER = 1, ///< Cache Associativity - Other
- ISCP_CACHE_ASSOCIATIVITY_UNKNOWN, ///< Cache Associativity - Unknown
- ISCP_CACHE_ASSOCIATIVITY_DIRECT_MAPPED, ///< Cache Associativity - Direct Mapped
- ISCP_CACHE_ASSOCIATIVITY_2_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 2-way Set Assciative
- ISCP_CACHE_ASSOCIATIVITY_4_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 4-way Set Assciative
- ISCP_CACHE_ASSOCIATIVITY_FULLY_ASSOCIATIVE, ///< Cache Associativity - Fully Assciative
- ISCP_CACHE_ASSOCIATIVITY_8_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 8-way Set Assciative
- ISCP_CACHE_ASSOCIATIVITY_16_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 16-way Set Assciative
- ISCP_CACHE_ASSOCIATIVITY_12_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 12-way Set Assciative
- ISCP_CACHE_ASSOCIATIVITY_24_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 24-way Set Assciative
- ISCP_CACHE_ASSOCIATIVITY_32_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 32-way Set Assciative
- ISCP_CACHE_ASSOCIATIVITY_48_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 48-way Set Assciative
- ISCP_CACHE_ASSOCIATIVITY_64_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 64-way Set Assciative
- ISCP_CACHE_ASSOCIATIVITY_20_WAY_SET_ASSOCIATIVE ///< Cache Associativity - 20-way Set Assciative
- } ISCP_CACHE_ASSOCIATIVITY;
-
- /// DMI TYPE 4 - CPU Information
- typedef struct {
- UINT16 T4ProcType; ///< Processor Type
- UINT16 T4ProcFamily; ///< Processor Family
- ISCP_PROC_ID T4ProcId; ///< Processor Id
- UINT16 T4Voltage; ///< Processor Voltage
- UINT16 T4ExternalClock; ///< Processor External Clock
- UINT16 T4MaxSpeed; ///< Processor Maximum Speed
- UINT16 T4CurrentSpeed; ///< Processor Current Speed
- UINT16 T4Status; ///< Processor Status
- UINT16 T4ProcUpgrade; ///< Processor Upgrade
- UINT16 T4CoreCount; ///< Processor Core Count
- UINT16 T4CoreEnabled; ///< Processor Core Enabled
- UINT16 T4ThreadCount; ///< Processor Thread Count
- UINT16 T4ProcCharacteristics; ///< Processor Characteristics
- UINT16 T4ProcFamily2; ///< Processor Family 2
- UINT16 T4CoreCount2; ///< Processor Core Count 2
- UINT16 T4CoreEnabled2; ///< Processor Core Enabled 2
- UINT16 T4ThreadCount2; ///< Processor Thread Count 2
- UINT8 T4SerialNumber[8]; ///< Processor Serial Number
- } ISCP_TYPE4_SMBIOS_INFO;
-
- /// DMI Type 7 - Cache Information
- typedef struct {
- UINT16 T7CacheCfg; ///< Cache Configuration
- UINT16 T7MaxCacheSize; ///< Maximum Cache Size
- UINT16 T7InstallSize; ///< Cache Install Size
- UINT16 T7SupportedSramType; ///< Supported SRAM Type
- UINT16 T7CurrentSramType; ///< Current SRAM Type
- UINT16 T7CacheSpeed; ///< Cache Speed in nanoseconds
- UINT16 T7ErrorCorrectionType; ///< Cache Error Correction Type
- UINT16 T7SystemCacheType; ///< System Cache Type
- UINT16 T7Associativity; ///< Cache Associativity
- } ISCP_TYPE7_SMBIOS_INFO;
-
- #ifdef __cplusplus
- }
-#endif
-
-
-#endif /* CPUISCP_H_ */
+/* $NoKeywords */ +/** + * @file + * + * MemIscp.h + * + * Contains common Memory Training ISCP-related structures and defines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e version: $Revision: 317558 $ @e date: $Date: 2015-04-24 17:20:55 -0700 (Fri, 24 Apr 2015) $ + * + */ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ + +//######################################################################### +//######################################################################### +//######################################################################### +// NOTE: This file shared between SCP and UEFI, make sure all // +// changes are reflected in both copies. // +//######################################################################### +//######################################################################### +//######################################################################### + +#ifndef CPUISCP_H_ +#define CPUISCP_H_ + +#ifdef __cplusplus + extern "C" { + #endif + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + #include <ProcessorBind.h> // Included just so this file can be built into both the RTOS + // and UEFI without needing separate copies for both build + // environments. + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + /// Processor ID + typedef struct { + UINT32 ProcIDMsd; ///< Processor ID Msd + UINT32 ProcIDLsd; ///< Processor ID Lsd + } ISCP_PROC_ID; + + /// Processor Type + typedef enum { + ISCP_CPU_TYPE_OTHER = 1, ///< Other + ISCP_CPU_TYPE_UNKNOWN, ///< Unknown + ISCP_CPU_TYPE_CENTRAL_PROCESSOR, ///< Central Processor + ISCP_CPU_TYPE_MATH_COPROCESSOR, ///< Math Coprocessor + ISCP_CPU_TYPE_DSP_PROCESSOR, ///< DSP Processor + ISCP_CPU_TYPE_VIDEO_PROCESSOR ///< Video Processor + } ISCP_PROCESSOR_TYPE; + + /// Processor Information - Processor Family. + typedef enum { + ISCP_ProcessorFamilyOther = 0x01, ///< Processor Family - Other + ISCP_ProcessorFamilyUnknown = 0x02, ///< Processor Family - Unknown + ISCP_ProcessorFamily8086 = 0x03, ///< Processor Family - 8086 + ISCP_ProcessorFamily80286 = 0x04, ///< Processor Family - 80286 + ISCP_ProcessorFamilyIntel386 = 0x05, ///< Processor Family - Intel 386 + ISCP_ProcessorFamilyIntel486 = 0x06, ///< Processor Family - Intel 486 + ISCP_ProcessorFamily8087 = 0x07, ///< Processor Family - 8087 + ISCP_ProcessorFamily80287 = 0x08, ///< Processor Family - 80287 + ISCP_ProcessorFamily80387 = 0x09, ///< Processor Family - 80387 + ISCP_ProcessorFamily80487 = 0x0A, ///< Processor Family - 80487 + ISCP_ProcessorFamilyPentium = 0x0B, ///< Processor Family - Pentium + ISCP_ProcessorFamilyPentiumPro = 0x0C, ///< Processor Family - Pentium Pro + ISCP_ProcessorFamilyPentiumII = 0x0D, ///< Processor Family - Pentium II + ISCP_ProcessorFamilyPentiumMMX = 0x0E, ///< Processor Family - Pentium MMX + ISCP_ProcessorFamilyCeleron = 0x0F, ///< Processor Family - Celeron + ISCP_ProcessorFamilyPentiumIIXeon = 0x10, ///< Processor Family - Pentium II Xeon + ISCP_ProcessorFamilyPentiumIII = 0x11, ///< Processor Family - Pentium III + ISCP_ProcessorFamilyM1 = 0x12, ///< Processor Family - M1 + ISCP_ProcessorFamilyM2 = 0x13, ///< Processor Family - M2 + ISCP_ProcessorFamilyIntelCeleronM = 0x14, ///< Processor Family - Intel Celeron + ISCP_ProcessorFamilyIntelPentium4Ht = 0x15, ///< Processor Family - Intel Pentium 4Ht + ISCP_ProcessorFamilyAmdDuron = 0x18, ///< Processor Family - AMD Duron + ISCP_ProcessorFamilyK5 = 0x19, ///< Processor Family - K5 + ISCP_ProcessorFamilyK6 = 0x1A, ///< Processor Family - K6 + ISCP_ProcessorFamilyK6_2 = 0x1B, ///< Processor Family - K6-2 + ISCP_ProcessorFamilyK6_3 = 0x1C, ///< Processor Family - K6-3 + ISCP_ProcessorFamilyAmdAthlon = 0x1D, ///< Processor Family - AMD Athlon + ISCP_ProcessorFamilyAmd29000 = 0x1E, ///< Processor Family - AMD 29000 + ISCP_ProcessorFamilyK6_2Plus = 0x1F, ///< Processor Family - K6-2 Plus + ISCP_ProcessorFamilyPowerPC = 0x20, ///< Processor Family - Power PC + ISCP_ProcessorFamilyPowerPC601 = 0x21, ///< Processor Family - Power PC 601 + ISCP_ProcessorFamilyPowerPC603 = 0x22, ///< Processor Family - Power PC 603 + ISCP_ProcessorFamilyPowerPC603Plus = 0x23, ///< Processor Family - Power PC 603 Plus + ISCP_ProcessorFamilyPowerPC604 = 0x24, ///< Processor Family - Power PC 604 + ISCP_ProcessorFamilyPowerPC620 = 0x25, ///< Processor Family - Power PC 620 + ISCP_ProcessorFamilyPowerPCx704 = 0x26, ///< Processor Family - Power PC x704 + ISCP_ProcessorFamilyPowerPC750 = 0x27, ///< Processor Family - Power PC 750 + ISCP_ProcessorFamilyIntelCoreDuo = 0x28, ///< Processor Family - Intel Core Duo + ISCP_ProcessorFamilyIntelCoreDuoMobile = 0x29, ///< Processor Family - Intel core Duo Mobile + ISCP_ProcessorFamilyIntelCoreSoloMobile = 0x2A, ///< Processor Family - Intel Core Solo Mobile + ISCP_ProcessorFamilyIntelAtom = 0x2B, ///< Processor Family - Intel Atom + ISCP_ProcessorFamilyAlpha = 0x30, ///< Processor Family - Alpha + ISCP_ProcessorFamilyAlpha21064 = 0x31, ///< Processor Family - Alpha 21064 + ISCP_ProcessorFamilyAlpha21066 = 0x32, ///< Processor Family - Alpha 21166 + ISCP_ProcessorFamilyAlpha21164 = 0x33, ///< Processor Family - Alpha 21164 + ISCP_ProcessorFamilyAlpha21164PC = 0x34, ///< Processor Family - Alpha 21164PC + ISCP_ProcessorFamilyAlpha21164a = 0x35, ///< Processor Family - Alpha 21164a + ISCP_ProcessorFamilyAlpha21264 = 0x36, ///< Processor Family - Alpha 21264 + ISCP_ProcessorFamilyAlpha21364 = 0x37, ///< Processor Family - Alpha 21364 + ISCP_ProcessorFamilyAmdTurionIIUltraDualCoreMobileM = 0x38, ///< Processor Family - AMD Turion II Ultra Dual Core Mobile M + ISCP_ProcessorFamilyAmdTurionIIDualCoreMobileM = 0x39, ///< Processor Family - AMD Turion II Dual Core Mobile M + ISCP_ProcessorFamilyAmdAthlonIIDualCoreM = 0x3A, ///< Processor Family - AMD Athlon II Dual Core M + ISCP_ProcessorFamilyAmdOpteron6100Series = 0x3B, ///< Processor Family - AMD Opteron 6100 Series + ISCP_ProcessorFamilyAmdOpteron4100Series = 0x3C, ///< Processor Family - AMD Opteron 4100 Series + ISCP_ProcessorFamilyAmdOpteron6200Series = 0x3D, ///< Processor Family - AMD Opteron 6200 Series + ISCP_ProcessorFamilyAmdOpteron4200Series = 0x3E, ///< Processor Family - AMD Opteron 4200 Series + ISCP_ProcessorFamilyAmdFxSeries = 0x3F, ///< Processor Family - AMD FX Series + ISCP_ProcessorFamilyMips = 0x40, ///< Processor Family - MIPs + ISCP_ProcessorFamilyMIPSR4000 = 0x41, ///< Processor Family - MIPs R4000 + ISCP_ProcessorFamilyMIPSR4200 = 0x42, ///< Processor Family - MIPs R4200 + ISCP_ProcessorFamilyMIPSR4400 = 0x43, ///< Processor Family - MIPs R4400 + ISCP_ProcessorFamilyMIPSR4600 = 0x44, ///< Processor Family - MIPs R4600 + ISCP_ProcessorFamilyMIPSR10000 = 0x45, ///< Processor Family - MIPs R10000 + ISCP_ProcessorFamilyAmdCSeries = 0x46, ///< Processor Family - AMD C Series + ISCP_ProcessorFamilyAmdESeries = 0x47, ///< Processor Family - AMD E Series + ISCP_ProcessorFamilyAmdASeries = 0x48, ///< Processor Family - AMD A Series + ISCP_ProcessorFamilyAmdGSeries = 0x49, ///< Processor Family - AMD G Series + ISCP_ProcessorFamilyAmdZSeries = 0x4A, ///< Processor Family - AMD Z Series + ISCP_ProcessorFamilyAmdRSeries = 0x4B, ///< Processor Family - AMD R Series + ISCP_ProcessorFamilyAmdOpteron4300 = 0x4C, ///< Processor Family - AMD Opteron 4300 + ISCP_ProcessorFamilyAmdOpteron6300 = 0x4D, ///< Processor Family - AMD Opteron 6300 + ISCP_ProcessorFamilyAmdOpteron3300 = 0x4E, ///< Processor Family - AMD Opteron 3300 + ISCP_ProcessorFamilyAmdFireProSeries = 0x4F, ///< Processor Family - AMD Fire Pro Series + ISCP_ProcessorFamilySparc = 0x50, ///< Processor Family - Sparc + ISCP_ProcessorFamilySuperSparc = 0x51, ///< Processor Family - Super Sparc + ISCP_ProcessorFamilymicroSparcII = 0x52, ///< Processor Family - Sparc II + ISCP_ProcessorFamilymicroSparcIIep = 0x53, ///< Processor Family - Sparc IIep + ISCP_ProcessorFamilyUltraSparc = 0x54, ///< Processor Family - Ultra Sparc + ISCP_ProcessorFamilyUltraSparcII = 0x55, ///< Processor Family - Ultra Sparc II + ISCP_ProcessorFamilyUltraSparcIii = 0x56, ///< Processor Family - Ultra Sparc Iii + ISCP_ProcessorFamilyUltraSparcIII = 0x57, ///< Processor Family - Ultra Sparc III + ISCP_ProcessorFamilyUltraSparcIIIi = 0x58, ///< Processor Family - Ultra Sparc IIIi + ISCP_ProcessorFamily68040 = 0x60, ///< Processor Family - 68040 + ISCP_ProcessorFamily68xxx = 0x61, ///< Processor Family - 68xxx + ISCP_ProcessorFamily68000 = 0x62, ///< Processor Family - 68000 + ISCP_ProcessorFamily68010 = 0x63, ///< Processor Family - 68010 + ISCP_ProcessorFamily68020 = 0x64, ///< Processor Family - 68020 + ISCP_ProcessorFamily68030 = 0x65, ///< Processor Family - 68030 + ISCP_ProcessorFamilyAmdOpteronASeries = 0x69, ///< Processor Family - AMD Opteron A Series + ISCP_ProcessorFamilyHobbit = 0x70, ///< Processor Family - Hobbit + ISCP_ProcessorFamilyCrusoeTM5000 = 0x78, ///< Processor Family - Crusoe TM5000 + ISCP_ProcessorFamilyCrusoeTM3000 = 0x79, ///< Processor Family - Crusoe TM3000 + ISCP_ProcessorFamilyEfficeonTM8000 = 0x7A, ///< Processor Family - Efficeon TM8000 + ISCP_ProcessorFamilyWeitek = 0x80, ///< Processor Family - Weitek + ISCP_ProcessorFamilyItanium = 0x82, ///< Processor Family - Itanium + ISCP_ProcessorFamilyAmdAthlon64 = 0x83, ///< Processor Family - AMD Athlon64 + ISCP_ProcessorFamilyAmdOpteron = 0x84, ///< Processor Family - AMD Opeteron + ISCP_ProcessorFamilyAmdSempron = 0x85, ///< Processor Family - AMD Sempron + ISCP_ProcessorFamilyAmdTurion64Mobile = 0x86, ///< Processor Family - AMD Turion 64 Modbile + ISCP_ProcessorFamilyDualCoreAmdOpteron = 0x87, ///< Processor Family - AMD Dual Core Opteron + ISCP_ProcessorFamilyAmdAthlon64X2DualCore = 0x88, ///< Processor Family - AMD Athlon 64 X2 Dual Core + ISCP_ProcessorFamilyAmdTurion64X2Mobile = 0x89, ///< Processor Family - AMD Turion 64 X2 Mobile + ISCP_ProcessorFamilyQuadCoreAmdOpteron = 0x8A, ///< Processor Family - AMD Quad Core Opteron + ISCP_ProcessorFamilyThirdGenerationAmdOpteron = 0x8B, ///< Processor Family - AMD 3rd Generation Opteron + ISCP_ProcessorFamilyAmdPhenomFxQuadCore = 0x8C, ///< Processor Family - AMD Phenom FX Quad Core + ISCP_ProcessorFamilyAmdPhenomX4QuadCore = 0x8D, ///< Processor Family - AMD Phenom X4 Quad Core + ISCP_ProcessorFamilyAmdPhenomX2DualCore = 0x8E, ///< Processor Family - AMD Phenom X2 Quad Core + ISCP_ProcessorFamilyAmdAthlonX2DualCore = 0x8F, ///< Processor Family - AMD Athlon X2 Dual Core + ISCP_ProcessorFamilyPARISC = 0x90, ///< Processor Family - PARISC + ISCP_ProcessorFamilyPaRisc8500 = 0x91, ///< Processor Family - PARISC 8500 + ISCP_ProcessorFamilyPaRisc8000 = 0x92, ///< Processor Family - PARISC 8000 + ISCP_ProcessorFamilyPaRisc7300LC = 0x93, ///< Processor Family - PARISC 7300LC + ISCP_ProcessorFamilyPaRisc7200 = 0x94, ///< Processor Family - PARISC 7200 + ISCP_ProcessorFamilyPaRisc7100LC = 0x95, ///< Processor Family - PARISC 7100LC + ISCP_ProcessorFamilyPaRisc7100 = 0x96, ///< Processor Family - PARISC 7100 + ISCP_ProcessorFamilyV30 = 0xA0, ///< Processor Family - V30 + ISCP_ProcessorFamilyQuadCoreIntelXeon3200Series = 0xA1, ///< Processor Family - Intel Quad Core Xeon 3200 Series + ISCP_ProcessorFamilyDualCoreIntelXeon3000Series = 0xA2, ///< Processor Family - Intel Dual Core Xeon 3000 Series + ISCP_ProcessorFamilyQuadCoreIntelXeon5300Series = 0xA3, ///< Processor Family - Intel Quad Core Xeon 5300 Series + ISCP_ProcessorFamilyDualCoreIntelXeon5100Series = 0xA4, ///< Processor Family - Intel Dual Core Xeon 5100 Series + ISCP_ProcessorFamilyDualCoreIntelXeon5000Series = 0xA5, ///< Processor Family - Intel Dual Core Xeon 5000 Series + ISCP_ProcessorFamilyDualCoreIntelXeonLV = 0xA6, ///< Processor Family - Intel Dual Core Xeon LV + ISCP_ProcessorFamilyDualCoreIntelXeonULV = 0xA7, ///< Processor Family - Intel Dual Core Xeon ULV + ISCP_ProcessorFamilyDualCoreIntelXeon7100Series = 0xA8, ///< Processor Family - Intel Quad Core Xeon 7100 Series + ISCP_ProcessorFamilyQuadCoreIntelXeon5400Series = 0xA9, ///< Processor Family - Intel Quad Core Xeon 5400 Series + ISCP_ProcessorFamilyQuadCoreIntelXeon = 0xAA, ///< Processor Family - Intel Quad Core Xeon + ISCP_ProcessorFamilyDualCoreIntelXeon5200Series = 0xAB, ///< Processor Family - Intel Dual Core Xeon 5200 Series + ISCP_ProcessorFamilyDualCoreIntelXeon7200Series = 0xAC, ///< Processor Family - Intel Dual Core Xeon 7200 Series + ISCP_ProcessorFamilyQuadCoreIntelXeon7300Series = 0xAD, ///< Processor Family - Intel Quad Core Xeon 7300 Series + ISCP_ProcessorFamilyQuadCoreIntelXeon7400Series = 0xAE, ///< Processor Family - Intel Quad Core Xeon 7400 Series + ISCP_ProcessorFamilyMultiCoreIntelXeon7400Series = 0xAF, ///< Processor Family - Intel Multi-Core Xeon 7400 Series + ISCP_ProcessorFamilyPentiumIIIXeon = 0xB0, ///< Processor Family - Intel Pentium III Xeon + ISCP_ProcessorFamilyPentiumIIISpeedStep = 0xB1, ///< Processor Family - Intel Pentium III Speed Step + ISCP_ProcessorFamilyPentium4 = 0xB2, ///< Processor Family - Pentium 4 + ISCP_ProcessorFamilyIntelXeon = 0xB3, ///< Processor Family - Intel Xeon + ISCP_ProcessorFamilyAS400 = 0xB4, ///< Processor Family - AS400 + ISCP_ProcessorFamilyIntelXeonMP = 0xB5, ///< Processor Family - Intel Xeon MP + ISCP_ProcessorFamilyAMDAthlonXP = 0xB6, ///< Processor Family - AMD Athlon XP + ISCP_ProcessorFamilyAMDAthlonMP = 0xB7, ///< Processor Family - AMD Athlon MP + ISCP_ProcessorFamilyIntelItanium2 = 0xB8, ///< Processor Family - Intel Itanum2 + ISCP_ProcessorFamilyIntelPentiumM = 0xB9, ///< Processor Family - Intel Pentium M + ISCP_ProcessorFamilyIntelCeleronD = 0xBA, ///< Processor Family - Intel Celeron D + ISCP_ProcessorFamilyIntelPentiumD = 0xBB, ///< Processor Family - Intel Pentium D + ISCP_ProcessorFamilyIntelPentiumEx = 0xBC, ///< Processor Family - Intel pentium Ex + ISCP_ProcessorFamilyIntelCoreSolo = 0xBD, ///< Processor Family - Intel Core Solo + ISCP_ProcessorFamilyReserved = 0xBE, ///< Processor Family - Reserved + ISCP_ProcessorFamilyIntelCore2 = 0xBF, ///< Processor Family - Intel Core 2 + ISCP_ProcessorFamilyIntelCore2Solo = 0xC0, ///< Processor Family - Intel Core 2 Solo + ISCP_ProcessorFamilyIntelCore2Extreme = 0xC1, ///< Processor Family - Intel Core 2 Extreme + ISCP_ProcessorFamilyIntelCore2Quad = 0xC2, ///< Processor Family - Intel Core 2 Quad + ISCP_ProcessorFamilyIntelCore2ExtremeMobile = 0xC3, ///< Processor Family - Intel Core 2 Extremem Mobile + ISCP_ProcessorFamilyIntelCore2DuoMobile = 0xC4, ///< Processor Family - Intel core 2 Duo Mobile + ISCP_ProcessorFamilyIntelCore2SoloMobile = 0xC5, ///< Processor Family - Intel Core 2 Solo Mobile + ISCP_ProcessorFamilyIntelCoreI7 = 0xC6, ///< Processor Family - Intel Core I7 + ISCP_ProcessorFamilyDualCoreIntelCeleron = 0xC7, ///< Processor Family - Intel Dual Core Celeron + ISCP_ProcessorFamilyIBM390 = 0xC8, ///< Processor Family - IBM 390 + ISCP_ProcessorFamilyG4 = 0xC9, ///< Processor Family - G4 + ISCP_ProcessorFamilyG5 = 0xCA, ///< Processor Family - G5 + ISCP_ProcessorFamilyG6 = 0xCB, ///< Processor Family - G6 + ISCP_ProcessorFamilyzArchitecture = 0xCC, ///< Processor Family - zArchitecture + ISCP_ProcessorFamilyIntelCoreI5 = 0xCD, ///< Processor Family - Intel Core I5 + ISCP_ProcessorFamilyIntelCoreI3 = 0xCE, ///< Processor Family - Intel Core I3 + ISCP_ProcessorFamilyViaC7M = 0xD2, ///< Processor Family - Via C7M + ISCP_ProcessorFamilyViaC7D = 0xD3, ///< Processor Family - Via C7D + ISCP_ProcessorFamilyViaC7 = 0xD4, ///< Processor Family - Via C7 + ISCP_ProcessorFamilyViaEden = 0xD5, ///< Processor Family - Via Eden + ISCP_ProcessorFamilyMultiCoreIntelXeon = 0xD6, ///< Processor Family - Intel Multi-core Xeon + ISCP_ProcessorFamilyDualCoreIntelXeon3Series = 0xD7, ///< Processor Family - Intel Dual-core Xeon 3-Series + ISCP_ProcessorFamilyQuadCoreIntelXeon3Series = 0xD8, ///< Processor Family - Intel Quad-core Xeon 3-Series + ISCP_ProcessorFamilyViaNano = 0xD9, ///< Processor Family - Via Nano + ISCP_ProcessorFamilyDualCoreIntelXeon5Series = 0xDA, ///< Processor Family - Intel Dual-core Xeon 5-Series + ISCP_ProcessorFamilyQuadCoreIntelXeon5Series = 0xDB, ///< Processor Family - Intel Quad-core Xeon 5-Series + ISCP_ProcessorFamilyDualCoreIntelXeon7Series = 0xDD, ///< Processor Family - Intel Dual-core Xeon 7-Series + ISCP_ProcessorFamilyQuadCoreIntelXeon7Series = 0xDE, ///< Processor Family - Intel Quad-core Xeon 7-Series + ISCP_ProcessorFamilyMultiCoreIntelXeon7Series = 0xDF, ///< Processor Family - Intel Multi-core Xeon 7-Series + ISCP_ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0, ///< Processor Family - Intel Multi-core Xeon 3400-Series + ISCP_ProcessorFamilyAmdOpteron3000Series = 0xE4, ///< Processor Family - AMD Opteron 3000 Series + ISCP_ProcessorFamilyAmdSempronII = 0xE5, ///< Processor Family - AMD Sempron II + ISCP_ProcessorFamilyEmbeddedAmdOpteronQuadCore = 0xE6, ///< Processor Family - AMD Embedded Opteron Quad Core + ISCP_ProcessorFamilyAmdPhenomTripleCore = 0xE7, ///< Processor Family - AMD Phonon Triple Core + ISCP_ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8, ///< Processor Family - AMD Turion Ultra Dual Core Mobile + ISCP_ProcessorFamilyAmdTurionDualCoreMobile = 0xE9, ///< Processor Family - AMD Turion Dual Core Mobile + ISCP_ProcessorFamilyAmdAthlonDualCore = 0xEA, ///< Processor Family - AMD Turion Dual Core Mobile + ISCP_ProcessorFamilyAmdSempronSI = 0xEB, ///< Processor Family - AMD Sempron SI + ISCP_ProcessorFamilyAmdPhenomII = 0xEC, ///< Processor Family - AMD Phenon II + ISCP_ProcessorFamilyAmdAthlonII = 0xED, ///< Processor Family - AMD Athlon II + ISCP_ProcessorFamilySixCoreAmdOpteron = 0xEE, ///< Processor Family - AMD 6-Core Opteron + ISCP_ProcessorFamilyAmdSempronM = 0xEF, ///< Processor Family - AMD Sempon M + ISCP_ProcessorFamilyi860 = 0xFA, ///< Processor Family - i860 + ISCP_ProcessorFamilyi960 = 0xFB, ///< Processor Family - i960 + ISCP_ProcessorFamilyIndicatorFamily2 = 0xFE, ///< Processor Family - Indicator Family 2 + ISCP_ProcessorFamilyReserved1 = 0xFF ///< Processor Family - Reserved + } ISCP_PROCESSOR_FAMILY_DATA; + + /// Processor Information2 - Processor Family2. + typedef enum { + ISCP_ProcessorFamilySH3 = 0x0104, ///< ProcessorFamily - SH3 + ISCP_ProcessorFamilySH4 = 0x0105, ///< ProcessorFamily - SH4 + ISCP_ProcessorFamilyARM = 0x0118, ///< ProcessorFamily - ARM + ISCP_ProcessorFamilyStrongARM = 0x0119, ///< ProcessorFamily - Strong ARM + ISCP_ProcessorFamily6x86 = 0x012C, ///< ProcessorFamily - x86 + ISCP_ProcessorFamilyMediaGX = 0x012D, ///< ProcessorFamily - Media GX + ISCP_ProcessorFamilyMII = 0x012E, ///< ProcessorFamily - MII + ISCP_ProcessorFamilyWinChip = 0x0140, ///< ProcessorFamily - WinChip + ISCP_ProcessorFamilyDSP = 0x015E, ///< ProcessorFamily - DSP + ISCP_ProcessorFamilyVideoProcessor = 0x01F4 ///< ProcessorFamily - Video Processor + } ISCP_PROCESSOR_FAMILY2_DATA; + + /// Processor Information - Processor Upgrade. + typedef enum { + ISCP_ProcessorUpgradeOther = 0x01, ///< Processor Upgrade - Other + ISCP_ProcessorUpgradeUnknown = 0x02, ///< Processor Upgrade - Unknown + ISCP_ProcessorUpgradeDaughterBoard = 0x03, ///< Processor Upgrade - Daughter Board + ISCP_ProcessorUpgradeZIFSocket = 0x04, ///< Processor Upgrade - ZIF Socket + ISCP_ProcessorUpgradePiggyBack = 0x05, ///< Processor Upgrade - Piggyback + ISCP_ProcessorUpgradeNone = 0x06, ///< Processor Upgrade - None + ISCP_ProcessorUpgradeLIFSocket = 0x07, ///< Processor Upgrade - LIF Socket + ISCP_ProcessorUpgradeSlot1 = 0x08, ///< Processor Upgrade - Slot 1 + ISCP_ProcessorUpgradeSlot2 = 0x09, ///< Processor Upgrade - Slot 2 + ISCP_ProcessorUpgrade370PinSocket = 0x0A, ///< Processor Upgrade - 370 Pin Socket + ISCP_ProcessorUpgradeSlotA = 0x0B, ///< Processor Upgrade - Slot A + ISCP_ProcessorUpgradeSlotM = 0x0C, ///< Processor Upgrade - Slot M + ISCP_ProcessorUpgradeSocket423 = 0x0D, ///< Processor Upgrade - Socket 423 + ISCP_ProcessorUpgradeSocketA = 0x0E, ///< Processor Upgrade - Socket A + ISCP_ProcessorUpgradeSocket478 = 0x0F, ///< Processor Upgrade - Socket 478 + ISCP_ProcessorUpgradeSocket754 = 0x10, ///< Processor Upgrade - Socket 754 + ISCP_ProcessorUpgradeSocket940 = 0x11, ///< Processor Upgrade - Socket 940 + ISCP_ProcessorUpgradeSocket939 = 0x12, ///< Processor Upgrade - Socket 939 + ISCP_ProcessorUpgradeSocketmPGA604 = 0x13, ///< Processor Upgrade - PGA 604 + ISCP_ProcessorUpgradeSocketLGA771 = 0x14, ///< Processor Upgrade - LGA 771 + ISCP_ProcessorUpgradeSocketLGA775 = 0x15, ///< Processor Upgrade - LGA 775 + ISCP_ProcessorUpgradeSocketS1 = 0x16, ///< Processor Upgrade - S1 + ISCP_ProcessorUpgradeAM2 = 0x17, ///< Processor Upgrade - AM2 + ISCP_ProcessorUpgradeF1207 = 0x18, ///< Processor Upgrade - F1207 + ISCP_ProcessorSocketLGA1366 = 0x19, ///< Processor Upgrade - LGA 1366 + ISCP_ProcessorUpgradeSocketG34 = 0x1A, ///< Processor Upgrade - G34 + ISCP_ProcessorUpgradeSocketAM3 = 0x1B, ///< Processor Upgrade - AM3 + ISCP_ProcessorUpgradeSocketC32 = 0x1C, ///< Processor Upgrade - C32 + ISCP_ProcessorUpgradeSocketLGA1156 = 0x1D, ///< Processor Upgrade - LGA 1156 + ISCP_ProcessorUpgradeSocketLGA1567 = 0x1E, ///< Processor Upgrade - LGA 1567 + ISCP_ProcessorUpgradeSocketPGA988A = 0x1F, ///< Processor Upgrade - PGA 988A + ISCP_ProcessorUpgradeSocketBGA1288 = 0x20, ///< Processor Upgrade - PGA 1288 + ISCP_ProcessorUpgradeSocketrPGA988B = 0x21, ///< Processor Upgrade - PGA 988B + ISCP_ProcessorUpgradeSocketBGA1023 = 0x22, ///< Processor Upgrade - BGA 1023 + ISCP_ProcessorUpgradeSocketBGA1224 = 0x23, ///< Processor Upgrade - BGA 1224 + ISCP_ProcessorUpgradeSocketLGA1155 = 0x24, ///< Processor Upgrade - LGA 1155 + ISCP_ProcessorUpgradeSocketLGA1356 = 0x25, ///< Processor Upgrade - LGA 1356 + ISCP_ProcessorUpgradeSocketLGA2011 = 0x26, ///< Processor Upgrade - LGA 2011 + ISCP_ProcessorUpgradeSocketFS1 = 0x27, ///< Processor Upgrade - FS1 + ISCP_ProcessorUpgradeSocketFS2 = 0x28, ///< Processor Upgrade - FS2 + ISCP_ProcessorUpgradeSocketFM1 = 0x29, ///< Processor Upgrade - FM1 + ISCP_ProcessorUpgradeSocketFM2 = 0x2A, ///< Processor Upgrade - FM2 + ISCP_ProcessorUpgradeSocketLGA2011_3 = 0x2B, ///< Processor Upgrade - LGA 2011-3 + ISCP_ProcessorUpgradeSocketLGA1356_3 = 0x2C ///< Processor Upgrade - LGA 1356-3 + } ISCP_PROCESSOR_UPGRADE; + + /// CPU Information - Characteristics. + typedef struct { + UINT16 Reserved0 :1; ///< CPU Information - Reserved + UINT16 Unknown :1; ///< CPU Information - Unknown + UINT16 Capable64Bit :1; ///< CPU Information - Capable 64-Bit + UINT16 MultiCore :1; ///< CPU Information - Multi-core + UINT16 HardwareThread :1; ///< CPU Information - Hardware Thread + UINT16 ExecuteProtection :1; ///< CPU Information - Execute Protection + UINT16 EnhancedVirtualization :1; ///< CPU Information - Enhanced Virtualization + UINT16 PowerPerformanceControl :1; ///< CPU Information - Power Performance Control + UINT16 Reserved8_15 :8; ///< CPU Information - Reserved + } ISCP_PROCESSOR_CHARACTERISTICS; + + /// CPU Information - CPU Status. + typedef enum { + ISCP_CPU_STATUS_UNKNOWN = 0, ///< CPU Status - Unknown + ISCP_CPU_STATUS_ENABLED, ///< CPU Status - Enabled + ISCP_CPU_STATUS_DISABLED_BY_USER, ///< CPU Status - Disabled by user + ISCP_CPU_STATUS_DISABLED_BY_BIOS, ///< CPU Status - Disabled by BIOS + ISCP_CPU_STATUS_IDLE, ///< CPU Status - Idle + ISCP_CPU_STATUS_RESERVED_5, ///< CPU Status - Reserved + ISCP_CPU_STATUS_RESERVED_6, ///< CPU Status - Reserved + ISCP_CPU_STATUS_OTHER ///< CPU Status - Other + } ISCP_CPU_STATUS; + + + /// CPU Information - Status. + typedef struct { + UINT16 CpuStatus :3; ///< CPU Status + UINT16 Reserved3_5 :3; ///< Reserved Bits[5:3] + UINT16 CpuSocketPopulated :1; ///< CPU Socket Populated + UINT16 Reserved7_15 :9; ///< Reserved Bits[15:9] + } PROCESSOR_STATUS; + + /// Cache Information - Operation Mode. + typedef enum { + ISCP_CACHE_OPERATION_MODE_WRITE_THROUGH = 0, ///< Cache Operation Mode Write Through + ISCP_CACHE_OPERATION_MODE_WRITE_BACK, ///< Cache Operation Mode Write Back + ISCP_CACHE_OPERATION_MODE_VARIES_WITH_MEMORY_ADDRESS, ///< Cache Operation Mode Varies with Memory Address + ISCP_CACHE_OPERATION_MODE_UNKNOWN, ///< Cache Operation Mode Unknown + } ISCP_CACHE_OPERATION_MODE; + + /// Cache Information - Location. + typedef enum { + ISCP_CACHE_LOCATION_INTERNAL = 0, ///< Cache Location Internal + ISCP_CACHE_LOCATION_EXTERNAL, ///< Cache Location External + ISCP_CACHE_LOCATION_RESERVED, ///< Cache Location Reserved + ISCP_CACHE_LOCATION_UNKNOWN, ///< Cache Location Unknown + } ISCP_CACHE_LOCATION; + + /// Cache Information - Level. + typedef enum { + ISCP_CACHE_LEVEL_1 = 0, ///< Cache Level 1 + ISCP_CACHE_LEVEL_2, ///< Cache Level 2 + ISCP_CACHE_LEVEL_3, ///< Cache Level 3 + ISCP_CACHE_LEVEL_4, ///< Cache Level 4 + } ISCP_CACHE_LEVEL; + + /// Cache Information - Configuration. + typedef struct { + UINT16 CacheLevel :3; ///< Cache Level + UINT16 CacheSocketd :1; ///< Cache Socket ID + UINT16 Reserved_4 :1; ///< Cache Reserved + UINT16 Location :2; ///< Cache Location + UINT16 EnabledDisabled :1; ///< Cache Enabled / Disabled + UINT16 OperationMode :2; ///< Operation Mode + UINT16 Reserved10_15 :6; ///< Cache Reserved + } ISCP_CACHE_CONFIGURATION; + + /// Cache Information - SRAM Type. + typedef struct { + UINT16 Other :1; ///< SRAM Type - Other + UINT16 Unknown :1; ///< SRAM Type - Unknown + UINT16 NonBurst :1; ///< SRAM Type - NonBurst + UINT16 Burst :1; ///< SRAM Type - Burst + UINT16 PipelineBurst :1; ///< SRAM Type - Pipeline Burst + UINT16 Synchronous :1; ///< SRAM Type - Synchronous + UINT16 Asynchronous :1; ///< SRAM Type - Asynchronous + UINT16 Reserved7_15 :9; ///< SRAM Type - Reserved + } ISCP_CACHE_SRAM_TYPE; + + /// Cache Information - Error Correction Type. + typedef enum { + ISCP_ECC_TYPE_OTHER = 1, ///< ECC Type - Other + ISCP_ECC_TYPE_UNKNOWN, ///< ECC Type - Unknown + ISCP_ECC_TYPE_NONE, ///< ECC Type - None + ISCP_ECC_TYPE_PARITY, ///< ECC Type - Parity + ISCP_ECC_TYPE_SINGLE_BIT, ///< ECC Type - Single-Bit + ISCP_ECC_TYPE_MULTI_BIT ///< ECC Type - Multi-Bit + } ISCP_CACHE_ECC_TYPE; + + /// Cache Information - System Cache Type. + typedef enum { + ISCP_SYSTEM_CACHE_TYPE_OTHER = 1, ///< System Cache Type - Other + ISCP_SYSTEM_CACHE_TYPE_UNKNOWN, ///< System Cache Type - Unknown + ISCP_SYSTEM_CACHE_TYPE_INSTRUCTION, ///< System Cache Type - Instruction + ISCP_SYSTEM_CACHE_TYPE_DATA, ///< System Cache Type - Data + ISCP_SYSTEM_CACHE_TYPE_UNIFIED ///< System Cache Type - Unified + } ISCP_SYSTEM_CACHE_TYPE; + + /// Cache Information - Associativity. + typedef enum { + ISCP_CACHE_ASSOCIATIVITY_OTHER = 1, ///< Cache Associativity - Other + ISCP_CACHE_ASSOCIATIVITY_UNKNOWN, ///< Cache Associativity - Unknown + ISCP_CACHE_ASSOCIATIVITY_DIRECT_MAPPED, ///< Cache Associativity - Direct Mapped + ISCP_CACHE_ASSOCIATIVITY_2_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 2-way Set Assciative + ISCP_CACHE_ASSOCIATIVITY_4_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 4-way Set Assciative + ISCP_CACHE_ASSOCIATIVITY_FULLY_ASSOCIATIVE, ///< Cache Associativity - Fully Assciative + ISCP_CACHE_ASSOCIATIVITY_8_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 8-way Set Assciative + ISCP_CACHE_ASSOCIATIVITY_16_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 16-way Set Assciative + ISCP_CACHE_ASSOCIATIVITY_12_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 12-way Set Assciative + ISCP_CACHE_ASSOCIATIVITY_24_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 24-way Set Assciative + ISCP_CACHE_ASSOCIATIVITY_32_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 32-way Set Assciative + ISCP_CACHE_ASSOCIATIVITY_48_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 48-way Set Assciative + ISCP_CACHE_ASSOCIATIVITY_64_WAY_SET_ASSOCIATIVE, ///< Cache Associativity - 64-way Set Assciative + ISCP_CACHE_ASSOCIATIVITY_20_WAY_SET_ASSOCIATIVE ///< Cache Associativity - 20-way Set Assciative + } ISCP_CACHE_ASSOCIATIVITY; + + /// DMI TYPE 4 - CPU Information + typedef struct { + UINT16 T4ProcType; ///< Processor Type + UINT16 T4ProcFamily; ///< Processor Family + ISCP_PROC_ID T4ProcId; ///< Processor Id + UINT16 T4Voltage; ///< Processor Voltage + UINT16 T4ExternalClock; ///< Processor External Clock + UINT16 T4MaxSpeed; ///< Processor Maximum Speed + UINT16 T4CurrentSpeed; ///< Processor Current Speed + UINT16 T4Status; ///< Processor Status + UINT16 T4ProcUpgrade; ///< Processor Upgrade + UINT16 T4CoreCount; ///< Processor Core Count + UINT16 T4CoreEnabled; ///< Processor Core Enabled + UINT16 T4ThreadCount; ///< Processor Thread Count + UINT16 T4ProcCharacteristics; ///< Processor Characteristics + UINT16 T4ProcFamily2; ///< Processor Family 2 + UINT16 T4CoreCount2; ///< Processor Core Count 2 + UINT16 T4CoreEnabled2; ///< Processor Core Enabled 2 + UINT16 T4ThreadCount2; ///< Processor Thread Count 2 + UINT8 T4SerialNumber[8]; ///< Processor Serial Number + } ISCP_TYPE4_SMBIOS_INFO; + + /// DMI Type 7 - Cache Information + typedef struct { + UINT16 T7CacheCfg; ///< Cache Configuration + UINT16 T7MaxCacheSize; ///< Maximum Cache Size + UINT16 T7InstallSize; ///< Cache Install Size + UINT16 T7SupportedSramType; ///< Supported SRAM Type + UINT16 T7CurrentSramType; ///< Current SRAM Type + UINT16 T7CacheSpeed; ///< Cache Speed in nanoseconds + UINT16 T7ErrorCorrectionType; ///< Cache Error Correction Type + UINT16 T7SystemCacheType; ///< System Cache Type + UINT16 T7Associativity; ///< Cache Associativity + } ISCP_TYPE7_SMBIOS_INFO; + + #ifdef __cplusplus + } +#endif + + +#endif /* CPUISCP_H_ */ diff --git a/Silicon/AMD/Styx/AmdModulePkg/Common/Iscp.h b/Silicon/AMD/Styx/AmdModulePkg/Common/Iscp.h index 30f8c65..5031519 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Common/Iscp.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Common/Iscp.h @@ -1,400 +1,400 @@ -/* $NoKeywords */
-/**
- * @file
- *
- * Iscp.h
- *
- * Contains common ISCP-related structures and defines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e version: $Revision: 338015 $ @e date: $Date: 2016-04-04 10:40:16 -0500 (Mon, 04 Apr 2016) $
- *
- */
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-
-//#########################################################################
-//#########################################################################
-//#########################################################################
-// NOTE: This file shared between SCP and UEFI, make sure all //
-// changes are reflected in both copies. //
-//#########################################################################
-//#########################################################################
-//#########################################################################
-
-#ifndef ISCP_H_
-#define ISCP_H_
-
-#ifdef __cplusplus
- extern "C" {
- #endif
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
- #include "SocConfiguration.h"
- #include "IscpConfig.h"
- #include "CoreState.h"
- #include "MemSetup.h"
- #include "MemIscp.h"
- #include "UartLineSettings.h"
- #include "CpuIscp.h"
- #include "NetworkAddress.h"
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
-// *** NOTE: This controls the size of a queue in SRAM. This is the
-// maximum number of elements that will fit, without changing the
-// overall SRAM layout.
-#define ISCP_ECC_EVENT_QUEUE_SIZE 8
-
- /// Types of ECC errors
- typedef enum _ECC_FAIL_TYPE {
- ECC_FAIL_NO_ERROR = 0, ///< ECC No Error
- ECC_FAIL_CORRECTABLE, ///< ECC Multiple Correctable Error
- ECC_FAIL_CORRECTABLE_MULTIPLE, ///< ECC Correctable Multiple Error
- ECC_FAIL_UNCORRECTABLE, ///< ECC Correctable Error
- ECC_FAIL_UNCORRECTABLE_MULTIPLE, ///< ECC Uncorrectable Multiple Error
- ECC_FAIL_PARITY, ///< ECC Parity Error
- ECC_FAIL_END ///< End of ECC Fail Types
- } ECC_FAIL_TYPE;
-
- /// ISCP ECC error events
- typedef struct _ISCP_ECC_EVENT_DETAILS {
- UINT64 Address; ///< Address
- UINT64 PhysicalAddress; ///< DRAM Physical Address
- UINT64 Data; ///< Data
- UINT32 Channel; ///< DRAM Channel
- UINT32 SourceId; ///< Scource ID
- UINT32 Syndrome; ///< ECC Syndrome
- UINT32 Type; ///< Restricted to ECC_FAIL_TYPE values
- UINT32 Module; ///< DRAM Module
- UINT32 Bank; ///< DRAM Bank
- UINT32 Row; ///< DRAM Row
- UINT32 Column; ///< DRAM Column
- } ISCP_ECC_EVENT_DETAILS;
-
- /// ISCP Block Transfer Memory Buffer
- typedef struct {
- UINT64 BuffAddress; ///< 64-Bit Communication Buffer Address
- UINT64 BufferSize; ///< 64-Bit Communication Buffer Size
- } BLOCK_TRANSFER_BUFFER;
-
- /// ISCP Data Window
- typedef struct {
- union {
- UINT8 szData[248]; ///< 8-bit ISCP data array
- BLOCK_TRANSFER_BUFFER BlockTransferBuffer; ///< ISCP Memory block Transfer Buffer structure
- } Data;
- } DATA_WINDOW;
-
- /// ISCP Communication Block. This structure must fit within the 4K SRAM area.
- typedef struct {
- UINT32 Signature; ///< Command Signature
- UINT8 BlockLength; ///< Block Length of the entire message
- UINT8 RequestCode; ///< Request Code - Operation Requested by the recipient
- UINT8 ResponseCode; ///< Response Code - Response Code from recipient
- UINT8 DataLength; ///< Data Length - Length in bytes of data
- ///< being transmitted, zero if MEMORY_BUFFER is used
- DATA_WINDOW DataWin; ///< Data Window Union (This completes the 256 byte header)
- UINT8 ExtraPayload[3072]; ///< Reserved for large payloads (A maximum of 3K)
- ISCP_ECC_EVENT_DETAILS FatalEccEvent; ///< Only one fatal ECC error event needed (56 bytes)
- ISCP_ECC_EVENT_DETAILS EccEventList[ISCP_ECC_EVENT_QUEUE_SIZE]; ///< List of ECC error events (448 bytes, which nearly finishes the 4K area)
- UINT8 HeadIndex; ///< Index of first ECC event, when head == tail queue is empty
- UINT8 TailIndex; ///< Index of empty queue entry, to be filled next.
- UINT8 Overflow; ///< Indicates a queue overflow, saturates at 0xFF
- } ISCP_COMM_BLOCK __attribute__ ((__aligned__ (64)));
-
- /// Memory info HOB structure
- typedef struct {
- UINT32 Version; ///< Version of HOB structure
- UINT32 NumberOfDescriptor; ///< Number of memory range descriptor
- AMD_MEMORY_RANGE_DESCRIPTOR Ranges; ///< Memory ranges
- } ISCP_MEMORY_INFO;
-
- /// SMBIOS Memory Buffer structure
- typedef struct {
- ISCP_TYPE16_SMBIOS_INFO T16; ///< SMBIOS Type 16 Record Data
- ISCP_TYPE17_SMBIOS_INFO T17[2][2]; ///< SMBIOS Type 17 Record Data
- ISCP_TYPE19_SMBIOS_INFO T19; ///< SMBIOS Type 19 Record Data
- } AMD_SMBIOS_MEM_BUFFER;
-
- /// SMBIOS CPU Buffer structure
- typedef struct {
- ISCP_TYPE4_SMBIOS_INFO T4[1]; ///< SMBIOS Type 4 Record Data
- ISCP_TYPE7_SMBIOS_INFO T7L1[1]; ///< SMBIOS Type 7 Level 1 Cache Record Data
- ISCP_TYPE7_SMBIOS_INFO T7L2[1]; ///< SMBIOS Type 7 Level 2 Cache Record Data
- ISCP_TYPE7_SMBIOS_INFO T7L3[1]; ///< SMBIOS Type 7 Level 3 Cache Record Data
- } AMD_SMBIOS_CPU_BUFFER;
-
- /// SMBIOS Buffer structure
- typedef struct {
- AMD_SMBIOS_MEM_BUFFER SmbiosMemBuffer; ///< SMBIOS Memory Buffer
- AMD_SMBIOS_CPU_BUFFER SmbiosCpuBuffer; ///< SMBIOS CPU Buffer
- } ISCP_SMBIOS_INFO;
-
- /// NV Data structure
- typedef struct {
- UINT32 Version; ///< Version of NV data structure
- UINT32 FvOffset; ///< Offset from the base of the UEFI image
- UINT32 FvSize; ///< Firmware Volume Data Size to be written, read, or erased
- UINT8 FvData[64*1024]; ///< Firmware Volume Data block
- } ISCP_OEM_NV_INFO;
-
- /// Firmware Fuse Buffer structure
- typedef struct {
- UINT32 Version; ///< Version of Fuse Info Buffer structure
- SocConfiguration SocConfiguration; ///< Fuse Structure to be passed to UEFI
- } ISCP_FUSE_INFO;
-
- /// Firmware CPU Reset Buffer structure
- typedef struct {
- UINT32 Version; ///< Version of CPU reset Buffer structure
- UINT32 CoreNum; ///< The core number we want data for, e.g. 0,1,2,..
- SocCoreStatus CoreStatus; ///< Core Status Structure
- } ISCP_CPU_RESET_INFO;
-
- /// Firmware MAC Address structure
- typedef struct {
- UINT32 Version; ///< Version of MAC address Info Buffer structure
- UINT8 MacAddress0[6]; ///< MAC Address 0 10Gb Ethernet port 0
- UINT8 MacAddress1[6]; ///< MAC Address 1 10Gb Ethernet port 1
- UINT8 MacAddress2[6]; ///< MAC Address 2 1Gb Ethernet
- } ISCP_MAC_INFO;
-
- /// ISCP RTC Time structure (Based on subset of EFI_TIME structure)
- typedef struct {
- UINT32 Version; ///< Version of RTC Info Buffer structure
- UINT16 Year; ///< Year: 2000 - 20XX
- UINT8 Month; ///< Month: 1 - 12
- UINT8 Day; ///< Day: 1 - 31
- UINT8 Hour; ///< Hour: 0 - 23
- UINT8 Minute; ///< Minute: 0 - 59
- UINT8 Second; ///< Second: 0 - 59
- UINT8 Pad; ///< Padding to made structure 32-bit aligned
- } ISCP_RTC_INFO;
-
- /// ISCP PCIE Reset structure
- typedef struct {
- UINT32 Version; ///< Version of PCIE reset Buffer structure
- UINT8 ResetSeq; ///< Sequence of Reset
- UINT16 SVID; ///< VRM value / Voltage
- } ISCP_PCIE_RESET_INFO;
-
- /// ISCP Ready To Boot structure
- typedef struct {
- UINT32 Version; ///< Version of Ready To Boot
- UINT8 ReadyToBoot; ///< Signal Ready To Boot Event
- } ISCP_READY_TO_BOOT_INFO;
-
- /// ISCP BMC IP Address structure
- typedef struct {
- UINT32 Version; ///< Version of BMC IP Address
- ISCP_BMC_IPV4_ADDRESS Ipv4Address; ///< BMC IPv4 Address Structure
- ISCP_BMC_IPV6_ADDRESS Ipv6Address; ///< BMC IPv6 Address Structure
- } ISCP_BMC_IP_ADDRESS_INFO;
-
- /// EEPROM info structure
- typedef struct {
- UINT32 Version; ///< Version of EEPROM Info structure
- UINT32 EepromOffset; ///< EEPROM Offset from the base of the UEFI image
- UINT32 EepromSize; ///< EEPROM Data Size to be written, read, or erased
- UINT32 EepromArea; ///< EEPROM Area to be affected by read, write,erase commands
- UINT8 EepromData[64*1024]; ///< EEPROm Data block [64K]
- } ISCP_EEPROM_INFO;
-
- /// UART info structure. The legal values for these fields are in UartLineSettings.h and are
- /// shared between the SCP and UEFI.
- typedef struct {
- UINT32 Version; ///< Version of UART Info structure
- UART_LINE_SETTINGS A57UartConfig; ///< A57 UART Config
- } ISCP_UART_INFO;
-
- /// Override Command structure
- typedef struct {
- UINT32 Version; ///< Version of Override Command structure
- UINT8 Command; ///< Override command
- } ISCP_OVERRIDE_CMD_INFO;
-
- /// SATA1 reset structure
- typedef struct {
- UINT32 Version; ///< Version of SATA en/disable structure
- UINT8 State; ///< Enable/Disable state
- } ISCP_SATA1_RESET_INFO;
-
- /// BMC presence structure
- typedef struct {
- UINT32 Version; ///< Version of BMC presence structure
- UINT8 BmcPresent; ///< BMC presence
- } ISCP_BMC_PRESENCE_INFO;
-
- /// BERT Region structure
- typedef struct {
- UINT32 IscpVersion; ///< Version of BERT Region structure
- UINT64 RegionPhysAddr; ///< ACPI v6.0: Table 18-319 [Boot Error Region]
- UINT32 RegionLength; ///< ACPI v6.0: Table 18-319 [Boot Error Region Length]
- } ISCP_BERT_REGION_INFO;
-
- /// SCP Doorbell Record structure
- typedef struct {
- UINT32 IscpVersion; ///< Version of Doorbell Info structure
- UINT32 ToggleRateMilliSec; ///< Doorbell Toggle Rate
- } ISCP_SCP_DOORBELL_INFO;
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-#define ISCP_TIMEOUT (1000000)
-
-// Request Codes
-#define ISCP_TRANSACTION_SUCCESS (0x00)
-
-#define ISCP_REQ_MEMORY (0x03)
-#define ISCP_RETRIEVE_SETUP (0x04)
-#define ISCP_STORE_SETUP (0x05)
-#define ISCP_FUSE_BLOB (0x07)
-#define ISCP_CPU_RETRIEVE_ID (0x09)
-#define ISCP_CPU_RESET (0x0A)
-#define ISCP_REQ_OEM_NV (0x0B)
-#define ISCP_STORE_OEM_NV (0x0C)
-#define ISCP_ERASE_OEM_NV (0x0D)
-#define ISCP_GET_MAC_ADDRESS (0x0E)
-#define ISCP_SET_MAC_ADDRESS (0x0F)
-#define ISCP_REQ_RTC (0x10)
-#define ISCP_SET_RTC (0x11)
-#define ISCP_GET_SMBIOS (0x12)
-#define ISCP_RESET_PCIE (0x13)
-#define ISCP_READY_TO_BOOT (0x14)
-#define ISCP_GET_BMC_IP (0x15)
-#define ISCP_RETRIEVE_VERSION (0x16)
-#define ISCP_STORE_EEPROM (0x17)
-#define ISCP_REQ_EEPROM (0x18)
-#define ISCP_ERASE_EEPROM (0x19)
-#define ISCP_MEM_SETUP (0x1A)
-#define ISCP_SEND_UART_CONFIG (0x1C)
-#define ISCP_OVERRIDE_CMD (0x1D)
-#define ISCP_SATA1_GET (0x1E)
-#define ISCP_SATA1_SET (0x1F)
-#define ISCP_BMC_PRESENT (0x20)
-#define ISCP_RETRIEVE_BERT_RECORD (0x21)
-#define ISCP_SUBMIT_BERT_RECORD (0x22)
-#define ISCP_POWER_OFF (0xAA)
-#define ISCP_SYSTEM_RESET (0xBB)
-
-// Response Codes
-#define ISCP_TRANSACTION_SUCCESS (0x00)
-#define ISCP_UNSUCCESSFUL (0x01)
-#define ISCP_INVALID (0x02)
-#define ISCP_SIGNATURE_NOT_FOUND (0x03)
-#define ISCP_NOT_SUPPORTED (0x04)
-#define ISCP_INVALID_BLOCK_LENGTH (0x05)
-#define ISCP_INVALID_REQUEST_CODE (0x06)
-#define ISCP_INVALID_DATA_LENGTH (0x07)
-#define ISCP_NV_WRITE_FAIL (0x0A)
-#define ISCP_NV_READ_FAIL (0x0B)
-#define ISCP_NV_ERASE_FAIL (0x0C)
-#define ISCP_SETUP_READ_FAIL (0x0D)
-#define ISCP_SETUP_WRITE_FAIL (0x0E)
-#define ISCP_EE_WRITE_FAIL (0x0F)
-#define ISCP_EE_READ_FAIL (0x10)
-#define ISCP_EE_ERASE_FAIL (0x11)
-#define ISCP_SMBIOS_FAIL (0x12)
-#define ISCP_INVALID_RESPONSE_CODE (0xFF)
-
-// ISCP Signatures
-#define BOOT_CORE_SIG (0x524F4342) //"BCOR" spelled backwards - Boot Core
-#define BERT_SIG (0x54524542) //"BERT" spelled backwards - BERT Error Block Buffer Address
-#define BMC_PRESENT_SIG (0x50434D42) //"BMCP" spelled backwards - BMC Present
-#define BMC_IP_ADDR_SIG (0x50494D42) //"BMIP" spelled backwards - BMC IP Address
-#define CPU_MP_SIG (0x4D555043) //"CPUM" spelled backwards - CPU Reset
-#define DOORBELL_SIG (0x4C454244) //"DBEL" spelled backwards - Doorbell
-#define EEPROM_SIG (0x52504545) //"EEPR" spelled backwards - EEPROM
-#define FUSE_BLOB_SIG (0x45535546) //"FUSE" spelled backwards - Fuse blob
-#define HOBS_SIG (0x53424F48) //"HOBS" spelled backwards - Memory HOBs buffer
-#define GET_MAC_ADDR_SIG (0x4143414D) //"MACA" spelled backwards - Get MAC Address
-#define OEM_NV_SIG (0x564E454F) //"OENV" spelled backwards - OEM NV Storage save and retrieval actions
-#define OVERRIDE_CMD_SIG (0x4452564F) //"OVRD" spelled backwards - Override Command
-#define PCIE_SIG (0x45494350) //"PCIE" spelled backwards - PCIE Reset
-#define READY2BOOT_SIG (0x54425452) //"RTBT" spelled backwards - Ready-To-Boot
-#define RTC_SIG (0x4B435452) //"RTCK" spelled backwards - Real-Time-Clock
-#define SATA1_GET_SIG (0x47544153) //"SATG" spelled backwards - SATA 1 get state
-#define SATA1_SET_SIG (0x53544153) //"SATS" spelled backwards - SATA 1 set state
-#define SETUP_SIG (0x55544553) //"SETU" spelled backwards - BIOS Setup
-#define SHUTDOWN_SIG (0x4E444853) //"SHDN" spelled backwards - System Shutdown
-#define SET_MAC_ADDR_SIG (0x43414D53) //"SMAC" spelled backwards - Set MAC Address
-#define SMBIOS_SIG (0x534D4253) //"SMBS" spelled backwards - SMBIOS
-#define UART_SIG (0x54524155) //"UART" spelled backwards - UART Config
-
-
-#define ISCP_BERT_REGION_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-
-#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
-#define ISCP_BMC_PRESENT_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-#endif
-
-#define ISCP_BMC_IP_ADDR_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-#define ISCP_CPU_RESET_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-
-#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
-#define ISCP_DOORBELL_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-#endif
-
-#define ISCP_EEPROM_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-#define ISCP_FUSE_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-#define ISCP_MEMORY_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-#define ISCP_MAC_INFO_VERSION (0x00000002ul) ///< Ver: 00.00.00.02
-#define ISCP_OEM_NV_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-
-#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
-#define ISCP_OVERRIDE_CMD_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-#endif
-
-#define ISCP_PCIE_RESET_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-
-#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
-#define ISCP_READY2BOOT_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-#endif
-
-#define ISCP_RTC_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-
-#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES
-#define ISCP_SATA1_RESET_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-#endif
-
-#define ISCP_UART_CONFIG_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01
-
-#define ISCP_COMM_BLK_MAX_SIZE (0x100) ///< Max length of ISCP communication block, 256 bytes
-#define MAX_NUMBER_OF_EXTENDED_MEMORY_DESCRIPTOR (2)
-#define MAX_SIZEOF_AMD_MEMORY_INFO_HOB_BUFFER (sizeof (ISCP_MEM_HOB) + \
- (MAX_NUMBER_OF_EXTENDED_MEMORY_DESCRIPTOR * sizeof (AMD_MEMORY_RANGE_DESCRIPTOR)))
-#define MAX_SIZEOF_AMD_SETUP_BUFFER (sizeof (ISCP_SETUP_INFO))
-#define MAX_SIZEOF_AMD_SMBIOS_BUFFER (sizeof (AMD_ISCP_SMBIOS_INFO))
-
-#define FOREVER for (;;)
-#define USE_DRAM_BUFFER (0x00)
-#define ISCP_BLOCK_LENGTH (0x08)
-
- #ifdef __cplusplus
- }
-#endif
-
-#endif /* ISCP_H_ */
+/* $NoKeywords */ +/** + * @file + * + * Iscp.h + * + * Contains common ISCP-related structures and defines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e version: $Revision: 338015 $ @e date: $Date: 2016-04-04 10:40:16 -0500 (Mon, 04 Apr 2016) $ + * + */ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ + +//######################################################################### +//######################################################################### +//######################################################################### +// NOTE: This file shared between SCP and UEFI, make sure all // +// changes are reflected in both copies. // +//######################################################################### +//######################################################################### +//######################################################################### + +#ifndef ISCP_H_ +#define ISCP_H_ + +#ifdef __cplusplus + extern "C" { + #endif + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + #include "SocConfiguration.h" + #include "IscpConfig.h" + #include "CoreState.h" + #include "MemSetup.h" + #include "MemIscp.h" + #include "UartLineSettings.h" + #include "CpuIscp.h" + #include "NetworkAddress.h" + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + +// *** NOTE: This controls the size of a queue in SRAM. This is the +// maximum number of elements that will fit, without changing the +// overall SRAM layout. +#define ISCP_ECC_EVENT_QUEUE_SIZE 8 + + /// Types of ECC errors + typedef enum _ECC_FAIL_TYPE { + ECC_FAIL_NO_ERROR = 0, ///< ECC No Error + ECC_FAIL_CORRECTABLE, ///< ECC Multiple Correctable Error + ECC_FAIL_CORRECTABLE_MULTIPLE, ///< ECC Correctable Multiple Error + ECC_FAIL_UNCORRECTABLE, ///< ECC Correctable Error + ECC_FAIL_UNCORRECTABLE_MULTIPLE, ///< ECC Uncorrectable Multiple Error + ECC_FAIL_PARITY, ///< ECC Parity Error + ECC_FAIL_END ///< End of ECC Fail Types + } ECC_FAIL_TYPE; + + /// ISCP ECC error events + typedef struct _ISCP_ECC_EVENT_DETAILS { + UINT64 Address; ///< Address + UINT64 PhysicalAddress; ///< DRAM Physical Address + UINT64 Data; ///< Data + UINT32 Channel; ///< DRAM Channel + UINT32 SourceId; ///< Scource ID + UINT32 Syndrome; ///< ECC Syndrome + UINT32 Type; ///< Restricted to ECC_FAIL_TYPE values + UINT32 Module; ///< DRAM Module + UINT32 Bank; ///< DRAM Bank + UINT32 Row; ///< DRAM Row + UINT32 Column; ///< DRAM Column + } ISCP_ECC_EVENT_DETAILS; + + /// ISCP Block Transfer Memory Buffer + typedef struct { + UINT64 BuffAddress; ///< 64-Bit Communication Buffer Address + UINT64 BufferSize; ///< 64-Bit Communication Buffer Size + } BLOCK_TRANSFER_BUFFER; + + /// ISCP Data Window + typedef struct { + union { + UINT8 szData[248]; ///< 8-bit ISCP data array + BLOCK_TRANSFER_BUFFER BlockTransferBuffer; ///< ISCP Memory block Transfer Buffer structure + } Data; + } DATA_WINDOW; + + /// ISCP Communication Block. This structure must fit within the 4K SRAM area. + typedef struct { + UINT32 Signature; ///< Command Signature + UINT8 BlockLength; ///< Block Length of the entire message + UINT8 RequestCode; ///< Request Code - Operation Requested by the recipient + UINT8 ResponseCode; ///< Response Code - Response Code from recipient + UINT8 DataLength; ///< Data Length - Length in bytes of data + ///< being transmitted, zero if MEMORY_BUFFER is used + DATA_WINDOW DataWin; ///< Data Window Union (This completes the 256 byte header) + UINT8 ExtraPayload[3072]; ///< Reserved for large payloads (A maximum of 3K) + ISCP_ECC_EVENT_DETAILS FatalEccEvent; ///< Only one fatal ECC error event needed (56 bytes) + ISCP_ECC_EVENT_DETAILS EccEventList[ISCP_ECC_EVENT_QUEUE_SIZE]; ///< List of ECC error events (448 bytes, which nearly finishes the 4K area) + UINT8 HeadIndex; ///< Index of first ECC event, when head == tail queue is empty + UINT8 TailIndex; ///< Index of empty queue entry, to be filled next. + UINT8 Overflow; ///< Indicates a queue overflow, saturates at 0xFF + } ISCP_COMM_BLOCK __attribute__ ((__aligned__ (64))); + + /// Memory info HOB structure + typedef struct { + UINT32 Version; ///< Version of HOB structure + UINT32 NumberOfDescriptor; ///< Number of memory range descriptor + AMD_MEMORY_RANGE_DESCRIPTOR Ranges; ///< Memory ranges + } ISCP_MEMORY_INFO; + + /// SMBIOS Memory Buffer structure + typedef struct { + ISCP_TYPE16_SMBIOS_INFO T16; ///< SMBIOS Type 16 Record Data + ISCP_TYPE17_SMBIOS_INFO T17[2][2]; ///< SMBIOS Type 17 Record Data + ISCP_TYPE19_SMBIOS_INFO T19; ///< SMBIOS Type 19 Record Data + } AMD_SMBIOS_MEM_BUFFER; + + /// SMBIOS CPU Buffer structure + typedef struct { + ISCP_TYPE4_SMBIOS_INFO T4[1]; ///< SMBIOS Type 4 Record Data + ISCP_TYPE7_SMBIOS_INFO T7L1[1]; ///< SMBIOS Type 7 Level 1 Cache Record Data + ISCP_TYPE7_SMBIOS_INFO T7L2[1]; ///< SMBIOS Type 7 Level 2 Cache Record Data + ISCP_TYPE7_SMBIOS_INFO T7L3[1]; ///< SMBIOS Type 7 Level 3 Cache Record Data + } AMD_SMBIOS_CPU_BUFFER; + + /// SMBIOS Buffer structure + typedef struct { + AMD_SMBIOS_MEM_BUFFER SmbiosMemBuffer; ///< SMBIOS Memory Buffer + AMD_SMBIOS_CPU_BUFFER SmbiosCpuBuffer; ///< SMBIOS CPU Buffer + } ISCP_SMBIOS_INFO; + + /// NV Data structure + typedef struct { + UINT32 Version; ///< Version of NV data structure + UINT32 FvOffset; ///< Offset from the base of the UEFI image + UINT32 FvSize; ///< Firmware Volume Data Size to be written, read, or erased + UINT8 FvData[64*1024]; ///< Firmware Volume Data block + } ISCP_OEM_NV_INFO; + + /// Firmware Fuse Buffer structure + typedef struct { + UINT32 Version; ///< Version of Fuse Info Buffer structure + SocConfiguration SocConfiguration; ///< Fuse Structure to be passed to UEFI + } ISCP_FUSE_INFO; + + /// Firmware CPU Reset Buffer structure + typedef struct { + UINT32 Version; ///< Version of CPU reset Buffer structure + UINT32 CoreNum; ///< The core number we want data for, e.g. 0,1,2,.. + SocCoreStatus CoreStatus; ///< Core Status Structure + } ISCP_CPU_RESET_INFO; + + /// Firmware MAC Address structure + typedef struct { + UINT32 Version; ///< Version of MAC address Info Buffer structure + UINT8 MacAddress0[6]; ///< MAC Address 0 10Gb Ethernet port 0 + UINT8 MacAddress1[6]; ///< MAC Address 1 10Gb Ethernet port 1 + UINT8 MacAddress2[6]; ///< MAC Address 2 1Gb Ethernet + } ISCP_MAC_INFO; + + /// ISCP RTC Time structure (Based on subset of EFI_TIME structure) + typedef struct { + UINT32 Version; ///< Version of RTC Info Buffer structure + UINT16 Year; ///< Year: 2000 - 20XX + UINT8 Month; ///< Month: 1 - 12 + UINT8 Day; ///< Day: 1 - 31 + UINT8 Hour; ///< Hour: 0 - 23 + UINT8 Minute; ///< Minute: 0 - 59 + UINT8 Second; ///< Second: 0 - 59 + UINT8 Pad; ///< Padding to made structure 32-bit aligned + } ISCP_RTC_INFO; + + /// ISCP PCIE Reset structure + typedef struct { + UINT32 Version; ///< Version of PCIE reset Buffer structure + UINT8 ResetSeq; ///< Sequence of Reset + UINT16 SVID; ///< VRM value / Voltage + } ISCP_PCIE_RESET_INFO; + + /// ISCP Ready To Boot structure + typedef struct { + UINT32 Version; ///< Version of Ready To Boot + UINT8 ReadyToBoot; ///< Signal Ready To Boot Event + } ISCP_READY_TO_BOOT_INFO; + + /// ISCP BMC IP Address structure + typedef struct { + UINT32 Version; ///< Version of BMC IP Address + ISCP_BMC_IPV4_ADDRESS Ipv4Address; ///< BMC IPv4 Address Structure + ISCP_BMC_IPV6_ADDRESS Ipv6Address; ///< BMC IPv6 Address Structure + } ISCP_BMC_IP_ADDRESS_INFO; + + /// EEPROM info structure + typedef struct { + UINT32 Version; ///< Version of EEPROM Info structure + UINT32 EepromOffset; ///< EEPROM Offset from the base of the UEFI image + UINT32 EepromSize; ///< EEPROM Data Size to be written, read, or erased + UINT32 EepromArea; ///< EEPROM Area to be affected by read, write,erase commands + UINT8 EepromData[64*1024]; ///< EEPROm Data block [64K] + } ISCP_EEPROM_INFO; + + /// UART info structure. The legal values for these fields are in UartLineSettings.h and are + /// shared between the SCP and UEFI. + typedef struct { + UINT32 Version; ///< Version of UART Info structure + UART_LINE_SETTINGS A57UartConfig; ///< A57 UART Config + } ISCP_UART_INFO; + + /// Override Command structure + typedef struct { + UINT32 Version; ///< Version of Override Command structure + UINT8 Command; ///< Override command + } ISCP_OVERRIDE_CMD_INFO; + + /// SATA1 reset structure + typedef struct { + UINT32 Version; ///< Version of SATA en/disable structure + UINT8 State; ///< Enable/Disable state + } ISCP_SATA1_RESET_INFO; + + /// BMC presence structure + typedef struct { + UINT32 Version; ///< Version of BMC presence structure + UINT8 BmcPresent; ///< BMC presence + } ISCP_BMC_PRESENCE_INFO; + + /// BERT Region structure + typedef struct { + UINT32 IscpVersion; ///< Version of BERT Region structure + UINT64 RegionPhysAddr; ///< ACPI v6.0: Table 18-319 [Boot Error Region] + UINT32 RegionLength; ///< ACPI v6.0: Table 18-319 [Boot Error Region Length] + } ISCP_BERT_REGION_INFO; + + /// SCP Doorbell Record structure + typedef struct { + UINT32 IscpVersion; ///< Version of Doorbell Info structure + UINT32 ToggleRateMilliSec; ///< Doorbell Toggle Rate + } ISCP_SCP_DOORBELL_INFO; + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define ISCP_TIMEOUT (1000000) + +// Request Codes +#define ISCP_TRANSACTION_SUCCESS (0x00) + +#define ISCP_REQ_MEMORY (0x03) +#define ISCP_RETRIEVE_SETUP (0x04) +#define ISCP_STORE_SETUP (0x05) +#define ISCP_FUSE_BLOB (0x07) +#define ISCP_CPU_RETRIEVE_ID (0x09) +#define ISCP_CPU_RESET (0x0A) +#define ISCP_REQ_OEM_NV (0x0B) +#define ISCP_STORE_OEM_NV (0x0C) +#define ISCP_ERASE_OEM_NV (0x0D) +#define ISCP_GET_MAC_ADDRESS (0x0E) +#define ISCP_SET_MAC_ADDRESS (0x0F) +#define ISCP_REQ_RTC (0x10) +#define ISCP_SET_RTC (0x11) +#define ISCP_GET_SMBIOS (0x12) +#define ISCP_RESET_PCIE (0x13) +#define ISCP_READY_TO_BOOT (0x14) +#define ISCP_GET_BMC_IP (0x15) +#define ISCP_RETRIEVE_VERSION (0x16) +#define ISCP_STORE_EEPROM (0x17) +#define ISCP_REQ_EEPROM (0x18) +#define ISCP_ERASE_EEPROM (0x19) +#define ISCP_MEM_SETUP (0x1A) +#define ISCP_SEND_UART_CONFIG (0x1C) +#define ISCP_OVERRIDE_CMD (0x1D) +#define ISCP_SATA1_GET (0x1E) +#define ISCP_SATA1_SET (0x1F) +#define ISCP_BMC_PRESENT (0x20) +#define ISCP_RETRIEVE_BERT_RECORD (0x21) +#define ISCP_SUBMIT_BERT_RECORD (0x22) +#define ISCP_POWER_OFF (0xAA) +#define ISCP_SYSTEM_RESET (0xBB) + +// Response Codes +#define ISCP_TRANSACTION_SUCCESS (0x00) +#define ISCP_UNSUCCESSFUL (0x01) +#define ISCP_INVALID (0x02) +#define ISCP_SIGNATURE_NOT_FOUND (0x03) +#define ISCP_NOT_SUPPORTED (0x04) +#define ISCP_INVALID_BLOCK_LENGTH (0x05) +#define ISCP_INVALID_REQUEST_CODE (0x06) +#define ISCP_INVALID_DATA_LENGTH (0x07) +#define ISCP_NV_WRITE_FAIL (0x0A) +#define ISCP_NV_READ_FAIL (0x0B) +#define ISCP_NV_ERASE_FAIL (0x0C) +#define ISCP_SETUP_READ_FAIL (0x0D) +#define ISCP_SETUP_WRITE_FAIL (0x0E) +#define ISCP_EE_WRITE_FAIL (0x0F) +#define ISCP_EE_READ_FAIL (0x10) +#define ISCP_EE_ERASE_FAIL (0x11) +#define ISCP_SMBIOS_FAIL (0x12) +#define ISCP_INVALID_RESPONSE_CODE (0xFF) + +// ISCP Signatures +#define BOOT_CORE_SIG (0x524F4342) //"BCOR" spelled backwards - Boot Core +#define BERT_SIG (0x54524542) //"BERT" spelled backwards - BERT Error Block Buffer Address +#define BMC_PRESENT_SIG (0x50434D42) //"BMCP" spelled backwards - BMC Present +#define BMC_IP_ADDR_SIG (0x50494D42) //"BMIP" spelled backwards - BMC IP Address +#define CPU_MP_SIG (0x4D555043) //"CPUM" spelled backwards - CPU Reset +#define DOORBELL_SIG (0x4C454244) //"DBEL" spelled backwards - Doorbell +#define EEPROM_SIG (0x52504545) //"EEPR" spelled backwards - EEPROM +#define FUSE_BLOB_SIG (0x45535546) //"FUSE" spelled backwards - Fuse blob +#define HOBS_SIG (0x53424F48) //"HOBS" spelled backwards - Memory HOBs buffer +#define GET_MAC_ADDR_SIG (0x4143414D) //"MACA" spelled backwards - Get MAC Address +#define OEM_NV_SIG (0x564E454F) //"OENV" spelled backwards - OEM NV Storage save and retrieval actions +#define OVERRIDE_CMD_SIG (0x4452564F) //"OVRD" spelled backwards - Override Command +#define PCIE_SIG (0x45494350) //"PCIE" spelled backwards - PCIE Reset +#define READY2BOOT_SIG (0x54425452) //"RTBT" spelled backwards - Ready-To-Boot +#define RTC_SIG (0x4B435452) //"RTCK" spelled backwards - Real-Time-Clock +#define SATA1_GET_SIG (0x47544153) //"SATG" spelled backwards - SATA 1 get state +#define SATA1_SET_SIG (0x53544153) //"SATS" spelled backwards - SATA 1 set state +#define SETUP_SIG (0x55544553) //"SETU" spelled backwards - BIOS Setup +#define SHUTDOWN_SIG (0x4E444853) //"SHDN" spelled backwards - System Shutdown +#define SET_MAC_ADDR_SIG (0x43414D53) //"SMAC" spelled backwards - Set MAC Address +#define SMBIOS_SIG (0x534D4253) //"SMBS" spelled backwards - SMBIOS +#define UART_SIG (0x54524155) //"UART" spelled backwards - UART Config + + +#define ISCP_BERT_REGION_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 + +#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES +#define ISCP_BMC_PRESENT_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 +#endif + +#define ISCP_BMC_IP_ADDR_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 +#define ISCP_CPU_RESET_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 + +#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES +#define ISCP_DOORBELL_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 +#endif + +#define ISCP_EEPROM_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 +#define ISCP_FUSE_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 +#define ISCP_MEMORY_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 +#define ISCP_MAC_INFO_VERSION (0x00000002ul) ///< Ver: 00.00.00.02 +#define ISCP_OEM_NV_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 + +#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES +#define ISCP_OVERRIDE_CMD_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 +#endif + +#define ISCP_PCIE_RESET_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 + +#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES +#define ISCP_READY2BOOT_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 +#endif + +#define ISCP_RTC_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 + +#ifdef THESE_SHOULD_BE_USED_ON_BOTH_SIDES +#define ISCP_SATA1_RESET_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 +#endif + +#define ISCP_UART_CONFIG_INFO_VERSION (0x00000001ul) ///< Ver: 00.00.00.01 + +#define ISCP_COMM_BLK_MAX_SIZE (0x100) ///< Max length of ISCP communication block, 256 bytes +#define MAX_NUMBER_OF_EXTENDED_MEMORY_DESCRIPTOR (2) +#define MAX_SIZEOF_AMD_MEMORY_INFO_HOB_BUFFER (sizeof (ISCP_MEM_HOB) + \ + (MAX_NUMBER_OF_EXTENDED_MEMORY_DESCRIPTOR * sizeof (AMD_MEMORY_RANGE_DESCRIPTOR))) +#define MAX_SIZEOF_AMD_SETUP_BUFFER (sizeof (ISCP_SETUP_INFO)) +#define MAX_SIZEOF_AMD_SMBIOS_BUFFER (sizeof (AMD_ISCP_SMBIOS_INFO)) + +#define FOREVER for (;;) +#define USE_DRAM_BUFFER (0x00) +#define ISCP_BLOCK_LENGTH (0x08) + + #ifdef __cplusplus + } +#endif + +#endif /* ISCP_H_ */ diff --git a/Silicon/AMD/Styx/AmdModulePkg/Common/IscpConfig.h b/Silicon/AMD/Styx/AmdModulePkg/Common/IscpConfig.h index cac451a..7fc899a 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Common/IscpConfig.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Common/IscpConfig.h @@ -1,63 +1,63 @@ -/* $NoKeywords */
-/**
- * @file
- *
- * IscpConfig.h
- *
- * Contains Intra-SoC Communication Protocol configuration definitions.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
- *
- */
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-#ifndef ISCP_CONFIG_H_
-#define ISCP_CONFIG_H_
-
-#ifdef __cplusplus
- extern "C" {
- #endif
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
- #include <ProcessorBind.h> // Included just so this file can be built into both the RTOS
- // and UEFI without needing separate copies for both build
- // environments.
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-// Door Bell Flag Register
-#define ISCP_DRAM_BUFFER_ADDR_REG_LO (0xE0000008UL)
-#define ISCP_DRAM_BUFFER_ADDR_REG_HI (0xE000000CUL)
-#define ISCP_BUFFER_SIZE (0x1000)
-#define DOORBELL_OFFSET_NS (0x100)
-#define DOORBELL_BIT_NS (UINT32) (1 << 7) // Door Bell bit = [GPIO_1 (Line 14)]
-#define DOORBELL_BIT_SEC (UINT32) (1 << 7) // Door Bell bit = [GPIO_1 (Line 15)]
-
- #ifdef __cplusplus
- }
-#endif
-
-
-#endif /* ISCP_CONFIG_H_ */
+/* $NoKeywords */ +/** + * @file + * + * IscpConfig.h + * + * Contains Intra-SoC Communication Protocol configuration definitions. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $ + * + */ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ +#ifndef ISCP_CONFIG_H_ +#define ISCP_CONFIG_H_ + +#ifdef __cplusplus + extern "C" { + #endif + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + #include <ProcessorBind.h> // Included just so this file can be built into both the RTOS + // and UEFI without needing separate copies for both build + // environments. + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ + +// Door Bell Flag Register +#define ISCP_DRAM_BUFFER_ADDR_REG_LO (0xE0000008UL) +#define ISCP_DRAM_BUFFER_ADDR_REG_HI (0xE000000CUL) +#define ISCP_BUFFER_SIZE (0x1000) +#define DOORBELL_OFFSET_NS (0x100) +#define DOORBELL_BIT_NS (UINT32) (1 << 7) // Door Bell bit = [GPIO_1 (Line 14)] +#define DOORBELL_BIT_SEC (UINT32) (1 << 7) // Door Bell bit = [GPIO_1 (Line 15)] + + #ifdef __cplusplus + } +#endif + + +#endif /* ISCP_CONFIG_H_ */ diff --git a/Silicon/AMD/Styx/AmdModulePkg/Common/MemIscp.h b/Silicon/AMD/Styx/AmdModulePkg/Common/MemIscp.h index 68cd0ec..c8ffe9d 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Common/MemIscp.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Common/MemIscp.h @@ -1,174 +1,174 @@ -/* $NoKeywords */
-/**
- * @file
- *
- * MemIscp.h
- *
- * Contains common Memory Training ISCP-related structures and defines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e version: $Revision: 317558 $ @e date: $Date: 2015-04-24 17:20:55 -0700 (Fri, 24 Apr 2015) $
- *
- */
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-
-//#########################################################################
-//#########################################################################
-//#########################################################################
-// NOTE: This file shared between SCP and UEFI, make sure all //
-// changes are reflected in both copies. //
-//#########################################################################
-//#########################################################################
-//#########################################################################
-
-#ifndef MEMISCP_H_
-#define MEMISCP_H_
-
-#ifdef __cplusplus
- extern "C" {
- #endif
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
- /// Memory Attribute enum
- typedef enum {
- MEM_AVAILABLE = 1, ///< Memory Available
- MEM_RESERVED, ///< Memory Reserved
- MEM_ACPI, ///< Memory ACPI
- MEM_NVS, ///< Memory NVS
- MEM_UNUSABLE ///< Memory Unavailable
- } MEMORY_ATTRIBUTE;
-
- /// Memory descriptor structure for each memory range
- typedef struct {
- UINT64 Base0; ///< Base address of memory range 0
- UINT64 Size0; ///< Size of memory range 0
- MEMORY_ATTRIBUTE Attribute0; ///< Attribute of memory range 0
- UINT32 Padding0; ///< 4-byte Padding to get 8-byte alignment
- UINT64 Base1; ///< Base address of memory range 1
- UINT64 Size1; ///< Size of memory range 1
- MEMORY_ATTRIBUTE Attribute1; ///< Attribute of memory range 1
- UINT32 Padding1; ///< 4-byte Padding to get 8-byte alignment
- UINT64 Base2; ///< Base address of memory range 2
- UINT64 Size2; ///< Size of memory range 2
- MEMORY_ATTRIBUTE Attribute2; ///< Attribute of memory range 2
- UINT32 Padding2; ///< 4-byte Padding to get 8-byte alignment
- UINT64 Base3; ///< Base address of memory range 3
- UINT64 Size3; ///< Size of memory range 3
- MEMORY_ATTRIBUTE Attribute3; ///< Attribute of memory range 3
- UINT32 Padding3; ///< 4-byte Padding to get 8-byte alignment
- } AMD_MEMORY_RANGE_DESCRIPTOR;
-
- /// SMBIOS Structure Header
- typedef struct {
- UINT8 Type; ///< TYPE
- UINT8 Length; ///< Length of TYPE
- UINT16 Handle; ///< structure handle, a unique 16-bit number in the range 0 to 0FEFFh
- } ISCP_SMBIOS_STRUCTURE_HEADER;
-
- /// DMI Type 16 - Physical Memory Array
- typedef struct {
- UINT16 Location; ///< The physical location of the Memory Array,
- ///< whether on the system board or an add-in board.
- UINT16 Use; ///< Identifies the function for which the array
- ///< is used.
- UINT16 MemoryErrorCorrection; ///< The primary hardware error correction or
- ///< detection method supported by this memory array.
- ///< ..for memory devices in this array.
- UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available..
- ///< ..for memory devices in this array.
- } ISCP_TYPE16_SMBIOS_INFO;
-
- /// DMI Type 17 offset 13h - Type Detail
- typedef struct {
- UINT16 Reserved1:1; ///< Reserved
- UINT16 Other:1; ///< Other
- UINT16 Unknown:1; ///< Unknown
- UINT16 FastPaged:1; ///< Fast-Paged
- UINT16 StaticColumn:1; ///< Static column
- UINT16 PseudoStatic:1; ///< Pseudo-static
- UINT16 Rambus:1; ///< RAMBUS
- UINT16 Synchronous:1; ///< Synchronous
- UINT16 Cmos:1; ///< CMOS
- UINT16 Edo:1; ///< EDO
- UINT16 WindowDram:1; ///< Window DRAM
- UINT16 CacheDram:1; ///< Cache Dram
- UINT16 NonVolatile:1; ///< Non-volatile
- UINT16 Registered:1; ///< Registered (Buffered)
- UINT16 Unbuffered:1; ///< Unbuffered (Unregistered)
- UINT16 Reserved2:1; ///< Reserved
- } SMBIOS_T17_TYPE_DETAIL;
-
- /// DMI Type 17 - Memory Device
- typedef struct {
- UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure
- UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
- UINT16 DataWidth; ///< Data Width, in bits, of this memory device.
- UINT16 MemorySize; ///< The size of the memory device.
- UINT16 FormFactor; ///< The implementation form factor for this memory device.
- UINT16 DeviceSet; ///< Identifies when the Memory Device is one of a set of..
- ///< ..memory devices that must be populated with all devices of..
- ///< ..the same type and size, and the set to which this device belongs.
- CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
- CHAR8 BankLocator[16]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
- UINT16 MemoryType; ///< The type of memory used in this device.
- SMBIOS_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type
- UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz).
- UINT8 ManufacturerIdCode[8]; ///< Manufacturer ID code.
- CHAR8 SerialNumber[16]; ///< Serial Number.
- CHAR8 PartNumber[20]; ///< Part Number.
- UINT16 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank.
- UINT32 ExtSize; ///< Extended Size.
- UINT16 ConfigSpeed; ///< Configured memory clock speed
- } ISCP_TYPE17_SMBIOS_INFO;
-
- /// DMI Type 19 - Memory Array Mapped Address
- typedef struct {
- UINT32 StartingAddr; ///< The physical address, in kilobytes,
- ///< of a range of memory mapped to the
- ///< specified physical memory array.
- UINT32 EndingAddr; ///< The physical ending address of the
- ///< last kilobyte of a range of addresses
- ///< mapped to the specified physical memory array.
- UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated
- ///< with the physical memory array to which this
- ///< address range is mapped.
- UINT8 PartitionWidth; ///< Identifies the number of memory devices that
- ///< form a single row of memory for the address
- ///< partition defined by this structure.
- UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of
- ///< memory mapped to the specified Physical Memory Array.
- UINT64 ExtEndingAddr; ///< The physical address, in bytes, of a range of
- ///< memory mapped to the specified Physical Memory Array.
- } ISCP_TYPE19_SMBIOS_INFO;
-
- #ifdef __cplusplus
- }
-#endif
-
-
-#endif /* MEMISCP_H_ */
+/* $NoKeywords */ +/** + * @file + * + * MemIscp.h + * + * Contains common Memory Training ISCP-related structures and defines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e version: $Revision: 317558 $ @e date: $Date: 2015-04-24 17:20:55 -0700 (Fri, 24 Apr 2015) $ + * + */ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ + +//######################################################################### +//######################################################################### +//######################################################################### +// NOTE: This file shared between SCP and UEFI, make sure all // +// changes are reflected in both copies. // +//######################################################################### +//######################################################################### +//######################################################################### + +#ifndef MEMISCP_H_ +#define MEMISCP_H_ + +#ifdef __cplusplus + extern "C" { + #endif + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + /// Memory Attribute enum + typedef enum { + MEM_AVAILABLE = 1, ///< Memory Available + MEM_RESERVED, ///< Memory Reserved + MEM_ACPI, ///< Memory ACPI + MEM_NVS, ///< Memory NVS + MEM_UNUSABLE ///< Memory Unavailable + } MEMORY_ATTRIBUTE; + + /// Memory descriptor structure for each memory range + typedef struct { + UINT64 Base0; ///< Base address of memory range 0 + UINT64 Size0; ///< Size of memory range 0 + MEMORY_ATTRIBUTE Attribute0; ///< Attribute of memory range 0 + UINT32 Padding0; ///< 4-byte Padding to get 8-byte alignment + UINT64 Base1; ///< Base address of memory range 1 + UINT64 Size1; ///< Size of memory range 1 + MEMORY_ATTRIBUTE Attribute1; ///< Attribute of memory range 1 + UINT32 Padding1; ///< 4-byte Padding to get 8-byte alignment + UINT64 Base2; ///< Base address of memory range 2 + UINT64 Size2; ///< Size of memory range 2 + MEMORY_ATTRIBUTE Attribute2; ///< Attribute of memory range 2 + UINT32 Padding2; ///< 4-byte Padding to get 8-byte alignment + UINT64 Base3; ///< Base address of memory range 3 + UINT64 Size3; ///< Size of memory range 3 + MEMORY_ATTRIBUTE Attribute3; ///< Attribute of memory range 3 + UINT32 Padding3; ///< 4-byte Padding to get 8-byte alignment + } AMD_MEMORY_RANGE_DESCRIPTOR; + + /// SMBIOS Structure Header + typedef struct { + UINT8 Type; ///< TYPE + UINT8 Length; ///< Length of TYPE + UINT16 Handle; ///< structure handle, a unique 16-bit number in the range 0 to 0FEFFh + } ISCP_SMBIOS_STRUCTURE_HEADER; + + /// DMI Type 16 - Physical Memory Array + typedef struct { + UINT16 Location; ///< The physical location of the Memory Array, + ///< whether on the system board or an add-in board. + UINT16 Use; ///< Identifies the function for which the array + ///< is used. + UINT16 MemoryErrorCorrection; ///< The primary hardware error correction or + ///< detection method supported by this memory array. + ///< ..for memory devices in this array. + UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available.. + ///< ..for memory devices in this array. + } ISCP_TYPE16_SMBIOS_INFO; + + /// DMI Type 17 offset 13h - Type Detail + typedef struct { + UINT16 Reserved1:1; ///< Reserved + UINT16 Other:1; ///< Other + UINT16 Unknown:1; ///< Unknown + UINT16 FastPaged:1; ///< Fast-Paged + UINT16 StaticColumn:1; ///< Static column + UINT16 PseudoStatic:1; ///< Pseudo-static + UINT16 Rambus:1; ///< RAMBUS + UINT16 Synchronous:1; ///< Synchronous + UINT16 Cmos:1; ///< CMOS + UINT16 Edo:1; ///< EDO + UINT16 WindowDram:1; ///< Window DRAM + UINT16 CacheDram:1; ///< Cache Dram + UINT16 NonVolatile:1; ///< Non-volatile + UINT16 Registered:1; ///< Registered (Buffered) + UINT16 Unbuffered:1; ///< Unbuffered (Unregistered) + UINT16 Reserved2:1; ///< Reserved + } SMBIOS_T17_TYPE_DETAIL; + + /// DMI Type 17 - Memory Device + typedef struct { + UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure + UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. + UINT16 DataWidth; ///< Data Width, in bits, of this memory device. + UINT16 MemorySize; ///< The size of the memory device. + UINT16 FormFactor; ///< The implementation form factor for this memory device. + UINT16 DeviceSet; ///< Identifies when the Memory Device is one of a set of.. + ///< ..memory devices that must be populated with all devices of.. + ///< ..the same type and size, and the set to which this device belongs. + CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. + CHAR8 BankLocator[16]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. + UINT16 MemoryType; ///< The type of memory used in this device. + SMBIOS_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type + UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). + UINT8 ManufacturerIdCode[8]; ///< Manufacturer ID code. + CHAR8 SerialNumber[16]; ///< Serial Number. + CHAR8 PartNumber[20]; ///< Part Number. + UINT16 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. + UINT32 ExtSize; ///< Extended Size. + UINT16 ConfigSpeed; ///< Configured memory clock speed + } ISCP_TYPE17_SMBIOS_INFO; + + /// DMI Type 19 - Memory Array Mapped Address + typedef struct { + UINT32 StartingAddr; ///< The physical address, in kilobytes, + ///< of a range of memory mapped to the + ///< specified physical memory array. + UINT32 EndingAddr; ///< The physical ending address of the + ///< last kilobyte of a range of addresses + ///< mapped to the specified physical memory array. + UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated + ///< with the physical memory array to which this + ///< address range is mapped. + UINT8 PartitionWidth; ///< Identifies the number of memory devices that + ///< form a single row of memory for the address + ///< partition defined by this structure. + UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of + ///< memory mapped to the specified Physical Memory Array. + UINT64 ExtEndingAddr; ///< The physical address, in bytes, of a range of + ///< memory mapped to the specified Physical Memory Array. + } ISCP_TYPE19_SMBIOS_INFO; + + #ifdef __cplusplus + } +#endif + + +#endif /* MEMISCP_H_ */ diff --git a/Silicon/AMD/Styx/AmdModulePkg/Common/MemSetup.h b/Silicon/AMD/Styx/AmdModulePkg/Common/MemSetup.h index ec7c3ce..5c81dec 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Common/MemSetup.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Common/MemSetup.h @@ -1,84 +1,84 @@ -/* $NoKeywords */
-/**
- * @file
- *
- * MemSetup.h
- *
- * Contains common MemSetup-related structures and defines.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e version: $Revision: 317558 $ @e date: $Date: 2015-04-24 17:20:55 -0700 (Fri, 24 Apr 2015) $
- *
- */
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-
-//#########################################################################
-//#########################################################################
-//#########################################################################
-// NOTE: This file shared between SCP and UEFI, make sure all //
-// changes are reflected in both copies. //
-//#########################################################################
-//#########################################################################
-//#########################################################################
-
-#ifndef MEMSETUP_H_
-#define MEMSETUP_H_
-
-#ifdef __cplusplus
- extern "C" {
- #endif
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-
- /// Memory Set up Structure for customer visibility
- typedef struct {
- UINT8 MemoryClockSpeed; ///< Memory clock speed
- UINT8 DDR3RttWr; ///< DDR3 Rtt_Wr
- UINT8 DDR3RttNom; ///< DDR3 Rtt_Nom
- UINT8 DDR4RttWr; ///< DDR4 Rtt_Wr
- UINT8 DDR4RttNom; ///< DDR4 Rtt_Nom
- UINT8 AddCtrlDriveStrength; ///< Address/Control Drive Strength
- UINT8 ClockDriveStrengt; ///< Clock Drive Strength
- UINT8 DataDMDriveStrength; ///< Data/DM Drive Strength
- UINT8 DQSDriveStrength; ///< DQS Drive Strength
- UINT8 PowerdownEnable; ///< Power down Enable
- UINT16 PowerdownIdleClocks; ///< Power down Idle Clocks
- UINT8 LongCountMask; ///< Long Count Mask
- UINT8 ECCEnable; ///< ECC Enable/Disable
- UINT16 tref; ///< tref
- UINT16 tselseldq; ///< tsel_sel_dq
- UINT16 tselseldqs; ///< tsel_sel_dqs
- UINT16 trainingProgress; ///< training progress
- UINT16 trainingRestore; ///< restore training results
- } MEM_SETUP_VAR;
-
- #ifdef __cplusplus
- }
-#endif
-
-
-#endif /* MEMSETUP_H_ */
+/* $NoKeywords */ +/** + * @file + * + * MemSetup.h + * + * Contains common MemSetup-related structures and defines. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e version: $Revision: 317558 $ @e date: $Date: 2015-04-24 17:20:55 -0700 (Fri, 24 Apr 2015) $ + * + */ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ + +//######################################################################### +//######################################################################### +//######################################################################### +// NOTE: This file shared between SCP and UEFI, make sure all // +// changes are reflected in both copies. // +//######################################################################### +//######################################################################### +//######################################################################### + +#ifndef MEMSETUP_H_ +#define MEMSETUP_H_ + +#ifdef __cplusplus + extern "C" { + #endif + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + + /// Memory Set up Structure for customer visibility + typedef struct { + UINT8 MemoryClockSpeed; ///< Memory clock speed + UINT8 DDR3RttWr; ///< DDR3 Rtt_Wr + UINT8 DDR3RttNom; ///< DDR3 Rtt_Nom + UINT8 DDR4RttWr; ///< DDR4 Rtt_Wr + UINT8 DDR4RttNom; ///< DDR4 Rtt_Nom + UINT8 AddCtrlDriveStrength; ///< Address/Control Drive Strength + UINT8 ClockDriveStrengt; ///< Clock Drive Strength + UINT8 DataDMDriveStrength; ///< Data/DM Drive Strength + UINT8 DQSDriveStrength; ///< DQS Drive Strength + UINT8 PowerdownEnable; ///< Power down Enable + UINT16 PowerdownIdleClocks; ///< Power down Idle Clocks + UINT8 LongCountMask; ///< Long Count Mask + UINT8 ECCEnable; ///< ECC Enable/Disable + UINT16 tref; ///< tref + UINT16 tselseldq; ///< tsel_sel_dq + UINT16 tselseldqs; ///< tsel_sel_dqs + UINT16 trainingProgress; ///< training progress + UINT16 trainingRestore; ///< restore training results + } MEM_SETUP_VAR; + + #ifdef __cplusplus + } +#endif + + +#endif /* MEMSETUP_H_ */ diff --git a/Silicon/AMD/Styx/AmdModulePkg/Common/NetworkAddress.h b/Silicon/AMD/Styx/AmdModulePkg/Common/NetworkAddress.h index 9d1f77f..3236df6 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Common/NetworkAddress.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Common/NetworkAddress.h @@ -1,55 +1,55 @@ -/**
- * @file
- *
- * Network Definitions.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: STYX
- * @e sub-project: (TBD)
- * @e \$Revision$ @e \$Date$
- *
- **/
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-
-
-#ifndef __NETWORK_ADDRESS_H__
-#define __NETWORK_ADDRESS_H__
-
-/// Indicates the status of an IP address field within a structure
- typedef enum {
- DISABLED, ///< Disabled
- ENABLED ///< Enabled
- } IP_ADDRESS_STATUS;
-
-/// Structure for an IPv4 address
- typedef struct {
- UINT32 Status; ///< Indicates if the address is valid
- UINT8 IpAddress[4]; ///< IPv4 address data, if enabled (xxx.xxx.xxx.xxx)
- } ISCP_BMC_IPV4_ADDRESS;
-
-/// Structure for an IPv6 address
- typedef struct {
- UINT32 Status; ///< Indicates if the address is valid
- UINT8 IpAddress[16]; ///< IPv6 address data, if enabled (xxxx:xxxx:xxxx:xxx:xxxx:xxxx:xxxx:xxxx)
- } ISCP_BMC_IPV6_ADDRESS;
-
-/// Structure for any combination of an IPv4 and an IPv6 address
- typedef struct {
- ISCP_BMC_IPV4_ADDRESS Ipv4Address; ///< IPv4 Network Address Structure
- ISCP_BMC_IPV6_ADDRESS Ipv6Address; ///< IPv6 Network Address Structure
- } IP_ADDRESS_INFO;
-
-#endif /* __NETWORK_ADDRESS_H__ */
+/** + * @file + * + * Network Definitions. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: STYX + * @e sub-project: (TBD) + * @e \$Revision$ @e \$Date$ + * + **/ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ + + +#ifndef __NETWORK_ADDRESS_H__ +#define __NETWORK_ADDRESS_H__ + +/// Indicates the status of an IP address field within a structure + typedef enum { + DISABLED, ///< Disabled + ENABLED ///< Enabled + } IP_ADDRESS_STATUS; + +/// Structure for an IPv4 address + typedef struct { + UINT32 Status; ///< Indicates if the address is valid + UINT8 IpAddress[4]; ///< IPv4 address data, if enabled (xxx.xxx.xxx.xxx) + } ISCP_BMC_IPV4_ADDRESS; + +/// Structure for an IPv6 address + typedef struct { + UINT32 Status; ///< Indicates if the address is valid + UINT8 IpAddress[16]; ///< IPv6 address data, if enabled (xxxx:xxxx:xxxx:xxx:xxxx:xxxx:xxxx:xxxx) + } ISCP_BMC_IPV6_ADDRESS; + +/// Structure for any combination of an IPv4 and an IPv6 address + typedef struct { + ISCP_BMC_IPV4_ADDRESS Ipv4Address; ///< IPv4 Network Address Structure + ISCP_BMC_IPV6_ADDRESS Ipv6Address; ///< IPv6 Network Address Structure + } IP_ADDRESS_INFO; + +#endif /* __NETWORK_ADDRESS_H__ */ diff --git a/Silicon/AMD/Styx/AmdModulePkg/Common/PostCode.h b/Silicon/AMD/Styx/AmdModulePkg/Common/PostCode.h index dabd58e..06cde1c 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Common/PostCode.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Common/PostCode.h @@ -1,82 +1,82 @@ -/* $NoKeywords */
-/**
- * @file
- *
- * PostCode.h
- *
- * Contains Where's-The-Fimrware (WTF) POST code definitions.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
- *
- */
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-
-#ifndef __POSTCODE__H_
-#define __POSTCODE__H_
-
-#ifdef __cplusplus
- extern "C" {
- #endif
-
-// AMD UEFI WTF POST Codes
-#define POST_ENTER_SEC_CORE 0x200 ///< Enter SEC Phase Core
-#define POST_INIT_GIG_SEC 0x201 ///< Initialize GIC in Secure Mode
-#define POST_EXIT_SEC_CORE 0x202 ///< Exit SEC Phase Core
-#define POST_INIT_GIC_NON_SEC 0x203 ///< Initalize GIC in Non-Secure Mode
-#define POST_INIT_FV 0x204 ///< Initialize Firmware Volume
-#define POST_RE_INIT_FV 0x205 ///< Re-Initialize Firmware Volume
-#define POST_PROCESS_FV_FILE 0x206 ///< Process Firmware Volume File
-#define POST_PROCESS_FV_FILE_SECT 0x207 ///< Process Firmware Volume Sections
-#define POST_CSP_LIB_INIT_PEI 0x208 ///< Initialize CSP Library PEI Phase
-#define POST_BSP_CORE_MAIN_PRE_PEI 0x209 ///< BSP Core Main Pre-PEI
-#define POST_AP_CORE_MAIN_PRE_PEI 0x20A ///< AP Core Main Pre-PEI
-#define POST_ENTER_PEI_CORE 0x20B ///< Enter PEI Core
-#define POST_INIT_GIC_PEI 0x20C ///< Initialize PEI GIC
-#define POST_UART_INIT 0x20D ///< Initialize UART
-#define POST_UART_INIT_PORT 0x20E ///< Initiaize the UART port attributes
-#define POST_PEI_ISCP_INIT 0x20F ///< Initialize PEI ISCP
-#define POST_EXIT_PEI_CORE 0x210 ///< Exit PEI Core
-#define POST_PRE_PI_MAIN 0x211 ///< Enter Pre-DXE Main
-#define POST_BSP_CORE_MAIN_PRE_PI 0x212 ///< Enter BSP Pre-DXE Core
-#define POST_AP_CORE_MAIN_PRE_PI 0x213 ///< Enter AP Core Main Pre-DXE
-#define POST_DXE_MAIN_UEFI_DECOMP 0x214 ///< Decompress DXE
-#define POST_ENTER_DXE_CORE 0x215 ///< Enter DXE Core
-#define POST_DXE_CORE_MEM_ADD_SPACE 0x216 ///< Add Memory Space in DXE Core
-#define POST_DXE_CORE_MEM_FREE_SPACE 0x217 ///< Free Memory Space in DXE Core
-#define POST_INIT_GIC_DXE 0x218 ///< Initialize GIC in DXE phase
-#define POST_INIT_ISCP_DXE 0x219 ///< Initialize ISCP DXE
-#define POST_EXIT_DXE_CORE 0x21A ///< Exit DXE Core
-#define POST_EXIT_BOOT_SERV 0x21B ///< Exit Boot Services
-#define POST_FINAL 0x3FF ///< Final POST code
-
-
-// AMD UEFI WTF Error Codes
-#define ERROR_ISCP_TIMEOUT 0x250 ///< ISCP Timeout (no response from SCP)
-#define ERROR_PXE_DHCP_FAIL 0x251 ///< PXE DHCP Fail
-#define ERROR_PXE_DHCP_PASS 0x252 ///< PXE DHCP Pass
-#define ERROR_PCIE_TRAIN_ERROR 0x261 ///< GIONB PCIE training error
-#define ERROR_PCIE_SPEED_ERROR 0x262 ///< GIONB PCIE data rate error
-#define ERROR_PCIE_PLL_ERROR 0x263 ///< GIONB PCIE PLL error
-#define ERROR_NO_HDD_DETECTED 0x2CF ///< No HDD Detected from SATA ports
-
-/****** DO NOT WRITE BELOW THIS LINE *******/
- #ifdef __cplusplus
- }
-#endif
-#endif
+/* $NoKeywords */ +/** + * @file + * + * PostCode.h + * + * Contains Where's-The-Fimrware (WTF) POST code definitions. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $ + * + */ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ + +#ifndef __POSTCODE__H_ +#define __POSTCODE__H_ + +#ifdef __cplusplus + extern "C" { + #endif + +// AMD UEFI WTF POST Codes +#define POST_ENTER_SEC_CORE 0x200 ///< Enter SEC Phase Core +#define POST_INIT_GIG_SEC 0x201 ///< Initialize GIC in Secure Mode +#define POST_EXIT_SEC_CORE 0x202 ///< Exit SEC Phase Core +#define POST_INIT_GIC_NON_SEC 0x203 ///< Initalize GIC in Non-Secure Mode +#define POST_INIT_FV 0x204 ///< Initialize Firmware Volume +#define POST_RE_INIT_FV 0x205 ///< Re-Initialize Firmware Volume +#define POST_PROCESS_FV_FILE 0x206 ///< Process Firmware Volume File +#define POST_PROCESS_FV_FILE_SECT 0x207 ///< Process Firmware Volume Sections +#define POST_CSP_LIB_INIT_PEI 0x208 ///< Initialize CSP Library PEI Phase +#define POST_BSP_CORE_MAIN_PRE_PEI 0x209 ///< BSP Core Main Pre-PEI +#define POST_AP_CORE_MAIN_PRE_PEI 0x20A ///< AP Core Main Pre-PEI +#define POST_ENTER_PEI_CORE 0x20B ///< Enter PEI Core +#define POST_INIT_GIC_PEI 0x20C ///< Initialize PEI GIC +#define POST_UART_INIT 0x20D ///< Initialize UART +#define POST_UART_INIT_PORT 0x20E ///< Initiaize the UART port attributes +#define POST_PEI_ISCP_INIT 0x20F ///< Initialize PEI ISCP +#define POST_EXIT_PEI_CORE 0x210 ///< Exit PEI Core +#define POST_PRE_PI_MAIN 0x211 ///< Enter Pre-DXE Main +#define POST_BSP_CORE_MAIN_PRE_PI 0x212 ///< Enter BSP Pre-DXE Core +#define POST_AP_CORE_MAIN_PRE_PI 0x213 ///< Enter AP Core Main Pre-DXE +#define POST_DXE_MAIN_UEFI_DECOMP 0x214 ///< Decompress DXE +#define POST_ENTER_DXE_CORE 0x215 ///< Enter DXE Core +#define POST_DXE_CORE_MEM_ADD_SPACE 0x216 ///< Add Memory Space in DXE Core +#define POST_DXE_CORE_MEM_FREE_SPACE 0x217 ///< Free Memory Space in DXE Core +#define POST_INIT_GIC_DXE 0x218 ///< Initialize GIC in DXE phase +#define POST_INIT_ISCP_DXE 0x219 ///< Initialize ISCP DXE +#define POST_EXIT_DXE_CORE 0x21A ///< Exit DXE Core +#define POST_EXIT_BOOT_SERV 0x21B ///< Exit Boot Services +#define POST_FINAL 0x3FF ///< Final POST code + + +// AMD UEFI WTF Error Codes +#define ERROR_ISCP_TIMEOUT 0x250 ///< ISCP Timeout (no response from SCP) +#define ERROR_PXE_DHCP_FAIL 0x251 ///< PXE DHCP Fail +#define ERROR_PXE_DHCP_PASS 0x252 ///< PXE DHCP Pass +#define ERROR_PCIE_TRAIN_ERROR 0x261 ///< GIONB PCIE training error +#define ERROR_PCIE_SPEED_ERROR 0x262 ///< GIONB PCIE data rate error +#define ERROR_PCIE_PLL_ERROR 0x263 ///< GIONB PCIE PLL error +#define ERROR_NO_HDD_DETECTED 0x2CF ///< No HDD Detected from SATA ports + +/****** DO NOT WRITE BELOW THIS LINE *******/ + #ifdef __cplusplus + } +#endif +#endif diff --git a/Silicon/AMD/Styx/AmdModulePkg/Common/SocConfiguration.h b/Silicon/AMD/Styx/AmdModulePkg/Common/SocConfiguration.h index 4ca9785..02dffa1 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Common/SocConfiguration.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Common/SocConfiguration.h @@ -1,100 +1,100 @@ -/* $NoKeywords */
-/**
- * @file
- *
- * SocConfiguration.h
- *
- * Contains SoC Fuse Data structure definitions.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
- *
- */
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-
-//#########################################################################
-//#########################################################################
-//#########################################################################
-// NOTE: This file shared between SCP and UEFI, make sure all //
-// changes are reflected in both copies. //
-//#########################################################################
-//#########################################################################
-//#########################################################################
-
-#ifndef __SOC_CONFIGURATION_H_
-#define __SOC_CONFIGURATION_H_
-
-#ifdef __cplusplus
- extern "C" {
- #endif
-
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
- #include "ProcessorBind.h"
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-#define SOC_BRAND_NAME_SIZE (48)
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
- /// SOC Security Modes Enumeration
- typedef enum {
- SOC_SECURITY_MODE_BLANK = 0, ///< Security Mode Blank
- SOC_SECURITY_MODE_NOT_SECURE, ///< Security Mode Non-secure
- SOC_SECURITY_MODE_SECURE, ///< Security Mode Secure
- SOC_SECURITY_MODE_UNDEFINED, ///< Security Mode Undefined
- } SOC_SECURITY_MODES;
-
- /// SOC Configuration, i.e. fusing structure
- typedef struct {
- UINT64 SerialNumber; ///< SOC Serial Number
- SOC_SECURITY_MODES SecurityState; ///< Indicates what security mode the SOC is in.
- INT32 CpuMap; ///< Map of CPU cores in SOC.
- INT32 CpuDefaultAClock; ///< Default fused core frequency
- INT32 CpuClusterCount; ///< Number of CPU clusters in SOC.
- INT32 CpuCoreCount; ///< Number of CPU cores in SOC.
- INT32 CpuClusterBoot; ///< Primary cluster used for boot.
- INT32 CpuCoreBoot; ///< Primary core used for boot.
- INT32 CcpEnabled; ///< Indicates CCP enabled state. Zero if disabled; otherwise, enabled.
- INT32 PcieEnabled; ///< Indicates PCIe enabled state. Zero if disabled; otherwise, enabled.
- INT32 SataEnabled; ///< Indicates SATA enabled state. Zero if disabled; otherwise, enabled.
- INT32 XgeEnabled; ///< Indicates 10 gigabit Ethernet port enabled state. Zero if disabled; otherwise, enabled.
- UINT32 BrandId; ///< Brand ID
- UINT32 ConfigurationId; ///< Configuration ID
- UINT32 CpuIdModel; ///< CPU ID - Model
- UINT32 CpuIdExtModel; ///< CPU ID - Extended Model
- UINT32 CpuIdStepping; ///< CPU ID - Stepping
- UINT32 FixedErrata; ///< Fixed Errata
- UINT32 InternalRevision; ///< Internal Revision
- UINT32 ManufacturingSpecifiedId; ///< Manufacturing Specified Field
- CHAR8 BrandName[SOC_BRAND_NAME_SIZE]; ///< Null appended at end
- } SocConfiguration;
-
- #ifdef __cplusplus
- }
-#endif
-
-#endif // __SOC_CONFIGURATION_H__
+/* $NoKeywords */ +/** + * @file + * + * SocConfiguration.h + * + * Contains SoC Fuse Data structure definitions. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $ + * + */ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ + +//######################################################################### +//######################################################################### +//######################################################################### +// NOTE: This file shared between SCP and UEFI, make sure all // +// changes are reflected in both copies. // +//######################################################################### +//######################################################################### +//######################################################################### + +#ifndef __SOC_CONFIGURATION_H_ +#define __SOC_CONFIGURATION_H_ + +#ifdef __cplusplus + extern "C" { + #endif + + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ + #include "ProcessorBind.h" + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define SOC_BRAND_NAME_SIZE (48) + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ + /// SOC Security Modes Enumeration + typedef enum { + SOC_SECURITY_MODE_BLANK = 0, ///< Security Mode Blank + SOC_SECURITY_MODE_NOT_SECURE, ///< Security Mode Non-secure + SOC_SECURITY_MODE_SECURE, ///< Security Mode Secure + SOC_SECURITY_MODE_UNDEFINED, ///< Security Mode Undefined + } SOC_SECURITY_MODES; + + /// SOC Configuration, i.e. fusing structure + typedef struct { + UINT64 SerialNumber; ///< SOC Serial Number + SOC_SECURITY_MODES SecurityState; ///< Indicates what security mode the SOC is in. + INT32 CpuMap; ///< Map of CPU cores in SOC. + INT32 CpuDefaultAClock; ///< Default fused core frequency + INT32 CpuClusterCount; ///< Number of CPU clusters in SOC. + INT32 CpuCoreCount; ///< Number of CPU cores in SOC. + INT32 CpuClusterBoot; ///< Primary cluster used for boot. + INT32 CpuCoreBoot; ///< Primary core used for boot. + INT32 CcpEnabled; ///< Indicates CCP enabled state. Zero if disabled; otherwise, enabled. + INT32 PcieEnabled; ///< Indicates PCIe enabled state. Zero if disabled; otherwise, enabled. + INT32 SataEnabled; ///< Indicates SATA enabled state. Zero if disabled; otherwise, enabled. + INT32 XgeEnabled; ///< Indicates 10 gigabit Ethernet port enabled state. Zero if disabled; otherwise, enabled. + UINT32 BrandId; ///< Brand ID + UINT32 ConfigurationId; ///< Configuration ID + UINT32 CpuIdModel; ///< CPU ID - Model + UINT32 CpuIdExtModel; ///< CPU ID - Extended Model + UINT32 CpuIdStepping; ///< CPU ID - Stepping + UINT32 FixedErrata; ///< Fixed Errata + UINT32 InternalRevision; ///< Internal Revision + UINT32 ManufacturingSpecifiedId; ///< Manufacturing Specified Field + CHAR8 BrandName[SOC_BRAND_NAME_SIZE]; ///< Null appended at end + } SocConfiguration; + + #ifdef __cplusplus + } +#endif + +#endif // __SOC_CONFIGURATION_H__ diff --git a/Silicon/AMD/Styx/AmdModulePkg/Common/UartLineSettings.h b/Silicon/AMD/Styx/AmdModulePkg/Common/UartLineSettings.h index 36df534..b81f5e7 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Common/UartLineSettings.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Common/UartLineSettings.h @@ -1,97 +1,97 @@ -/**
- * @file
- *
- * Generic UART line setting values. These are shared between UEFI and the SCP.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: STYX
- * @e sub-project: (TBD)
- * @e \$Revision$ @e \$Date$
- *
- **/
-/*****************************************************************************
- *
- * Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
- *
- * This program and the accompanying materials are licensed and made available
- * under the terms and conditions of the BSD License which accompanies this
- * distribution. The full text of the license may be found at
- * http://opensource.org/licenses/bsd-license.php
- *
- * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
- * IMPLIED.
- *
- * ***************************************************************************
- **/
-
-#ifndef _UART_LINE_SETTINGS_H_
-#define _UART_LINE_SETTINGS_H_
-
-//#########################################################################
-//#########################################################################
-//#########################################################################
-// NOTE: This file shared between SCP and UEFI, make sure all //
-// changes are reflected in both copies. //
-//#########################################################################
-//#########################################################################
-//#########################################################################
-
-
-/// UART Baudrate enum
-typedef enum {
- /// This subset is defined/used in UEFI
- UART_BAUDRATE_9600 = 9600, ///< 9600 Baudrate
- UART_BAUDRATE_19200 = 19200, ///< 19200 Baudrate
- UART_BAUDRATE_38400 = 38400, ///< 38400 Baudrate
- UART_BAUDRATE_57600 = 57600, ///< 57600 Baudrate
- UART_BAUDRATE_115200 = 115200, ///< 115200 Baudrate
-
- /// These could be used within the SCP.
- UART_BAUDRATE_110 = 110, ///< 110 Baudrate
- UART_BAUDRATE_300 = 300, ///< 300 Baudrate
- UART_BAUDRATE_600 = 600, ///< 600 Baudrate
- UART_BAUDRATE_1200 = 1200, ///< 1200 Baudrate
- UART_BAUDRATE_2400 = 2400, ///< 2400 Baudrate
- UART_BAUDRATE_4800 = 4800, ///< 4800 Baudrate
- UART_BAUDRATE_14400 = 14400, ///< 14400 Baudrate
- UART_BAUDRATE_230400 = 230400, ///< 230400 Baudrate
- UART_BAUDRATE_460800 = 460800, ///< 460800 Baudrate
- UART_BAUDRATE_921600 = 921600, ///< 921600 Baudrate
-} UART_BAUDRATE;
-
-/// UART Parity enum
-typedef enum {
- DEFAULT_PARITY = 0, ///< Default Parity
- NO_PARITY, ///< No Parity
- EVEN_PARITY, ///< Even Parity
- ODD_PARITY, ///< Odd Parity
- MARK_PARITY, ///< Mark Parity
- SPACE_PARITY ///< Space Parity
-} UART_PARITY;
-
-/// UART Stop Bit enum
-typedef enum {
- UART_STOP_BIT_0 = 0, ///< No Stop Bits
- UART_STOP_BIT_1, ///< One Stop Bit
- UART_STOP_BIT_1_5, ///< One and One Half Stop bits
- UART_STOP_BIT_2 ///< Two Stop Bits
-} UART_STOP_BITS;
-
-/// UART Data Length enum
-typedef enum {
- UART_DATA_BITS_5 = 5, ///< Five Data Bits
- UART_DATA_BITS_6, ///< Six Data Bits
- UART_DATA_BITS_7, ///< Seven Data Bits
- UART_DATA_BITS_8, ///< Eight Data Bits
-} UART_DATA_BITS;
-
-/// UART Line Settings structure
-typedef struct _UART_LINE_SETTINGS {
- UART_BAUDRATE BaudRate; ///< UART Baudrate
- UART_DATA_BITS DataBits; ///< UART Data Bits
- UART_PARITY Parity; ///< UART Parity
- UART_STOP_BITS StopBits; ///< UART Stop Bits
-} UART_LINE_SETTINGS;
-
-#endif /* _UART_LINE_SETTINGS_H_ */
+/** + * @file + * + * Generic UART line setting values. These are shared between UEFI and the SCP. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: STYX + * @e sub-project: (TBD) + * @e \$Revision$ @e \$Date$ + * + **/ +/***************************************************************************** + * + * Copyright 2015 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * This program and the accompanying materials are licensed and made available + * under the terms and conditions of the BSD License which accompanies this + * distribution. The full text of the license may be found at + * http://opensource.org/licenses/bsd-license.php + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR + * IMPLIED. + * + * *************************************************************************** + **/ + +#ifndef _UART_LINE_SETTINGS_H_ +#define _UART_LINE_SETTINGS_H_ + +//######################################################################### +//######################################################################### +//######################################################################### +// NOTE: This file shared between SCP and UEFI, make sure all // +// changes are reflected in both copies. // +//######################################################################### +//######################################################################### +//######################################################################### + + +/// UART Baudrate enum +typedef enum { + /// This subset is defined/used in UEFI + UART_BAUDRATE_9600 = 9600, ///< 9600 Baudrate + UART_BAUDRATE_19200 = 19200, ///< 19200 Baudrate + UART_BAUDRATE_38400 = 38400, ///< 38400 Baudrate + UART_BAUDRATE_57600 = 57600, ///< 57600 Baudrate + UART_BAUDRATE_115200 = 115200, ///< 115200 Baudrate + + /// These could be used within the SCP. + UART_BAUDRATE_110 = 110, ///< 110 Baudrate + UART_BAUDRATE_300 = 300, ///< 300 Baudrate + UART_BAUDRATE_600 = 600, ///< 600 Baudrate + UART_BAUDRATE_1200 = 1200, ///< 1200 Baudrate + UART_BAUDRATE_2400 = 2400, ///< 2400 Baudrate + UART_BAUDRATE_4800 = 4800, ///< 4800 Baudrate + UART_BAUDRATE_14400 = 14400, ///< 14400 Baudrate + UART_BAUDRATE_230400 = 230400, ///< 230400 Baudrate + UART_BAUDRATE_460800 = 460800, ///< 460800 Baudrate + UART_BAUDRATE_921600 = 921600, ///< 921600 Baudrate +} UART_BAUDRATE; + +/// UART Parity enum +typedef enum { + DEFAULT_PARITY = 0, ///< Default Parity + NO_PARITY, ///< No Parity + EVEN_PARITY, ///< Even Parity + ODD_PARITY, ///< Odd Parity + MARK_PARITY, ///< Mark Parity + SPACE_PARITY ///< Space Parity +} UART_PARITY; + +/// UART Stop Bit enum +typedef enum { + UART_STOP_BIT_0 = 0, ///< No Stop Bits + UART_STOP_BIT_1, ///< One Stop Bit + UART_STOP_BIT_1_5, ///< One and One Half Stop bits + UART_STOP_BIT_2 ///< Two Stop Bits +} UART_STOP_BITS; + +/// UART Data Length enum +typedef enum { + UART_DATA_BITS_5 = 5, ///< Five Data Bits + UART_DATA_BITS_6, ///< Six Data Bits + UART_DATA_BITS_7, ///< Seven Data Bits + UART_DATA_BITS_8, ///< Eight Data Bits +} UART_DATA_BITS; + +/// UART Line Settings structure +typedef struct _UART_LINE_SETTINGS { + UART_BAUDRATE BaudRate; ///< UART Baudrate + UART_DATA_BITS DataBits; ///< UART Data Bits + UART_PARITY Parity; ///< UART Parity + UART_STOP_BITS StopBits; ///< UART Stop Bits +} UART_LINE_SETTINGS; + +#endif /* _UART_LINE_SETTINGS_H_ */ diff --git a/Silicon/AMD/Styx/AmdModulePkg/Common/Wtf_Reg.h b/Silicon/AMD/Styx/AmdModulePkg/Common/Wtf_Reg.h index 736edab..7c7bb70 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Common/Wtf_Reg.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Common/Wtf_Reg.h @@ -1,133 +1,133 @@ -/* $NoKeywords */
-/**
- * @file
- *
- * Wtf_Reg.h
- *
- * Contains Where's-The-Firmware (WTF) definitions and Macros.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
- *
- */
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-
-#ifndef __WTF_REG__H_
-#define __WTF_REG__H_
-
-#ifdef __cplusplus
- extern "C" {
- #endif
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-#define WTF_STATUS_REG 0xE0000000 // "Where's The Firmware" Register
-
-#define WTF_STATUS_REG_SIZE 32
-#define WTF_STATUS_ERROR_SIZE 12
-#define WTF_STATUS_POST_SIZE 10
-#define WTF_STATUS_FW_INDICATOR_SIZE 2
-#define WTF_STATUS_BT_CHKSUMFAIL_SIZE 1
-
-#define WTF_STATUS_ERROR_SHIFT 0
-#define WTF_STATUS_POST_SHIFT 12
-#define WTF_STATUS_FW_INDICATOR_SHIFT 22
-#define WTF_STATUS_BT_CHKSUMFAIL_SHIFT 31
-
-#define WTF_STATUS_ERROR_MASK 0x00000FFF
-#define WTF_STATUS_POST_MASK 0x003FF000
-#define WTF_STATUS_FW_INDICATOR_MASK 0x00C00000
-#define WTF_STATUS_BT_CHKSUMFAIL_MASK 0x80000000
-
-#define WTF_STATUS_MASK \
- (WTF_STATUS_ERROR_MASK | \
- WTF_STATUS_POST_MASK | \
- WTF_STATUS_FW_INDICATOR_MASK | \
- WTF_STATUS_BT_CHKSUMFAIL_MASK)
-
-#define WTF_STATUS_DEFAULT 0x00000000
-#define WTF_STATUS_FW_INDICATOR_UEFI 0x2
-
-#define WTF_STATUS_GET_ERROR(wtf_status) \
- ((wtf_status & WTF_STATUS_ERROR_MASK) >> WTF_STATUS_ERROR_SHIFT)
-#define WTF_STATUS_GET_POST(wtf_status) \
- ((wtf_status & WTF_STATUS_POST_MASK) >> WTF_STATUS_POST_SHIFT)
-#define WTF_STATUS_GET_FW_INDICATOR(wtf_status) \
- ((wtf_status & WTF_STATUS_FW_INDICATOR_MASK) >> WTF_STATUS_FW_INDICATOR_SHIFT)
-#define WTF_STATUS_GET_BT_CHKSUMFAIL(wtf_status) \
- ((wtf_status & WTF_STATUS_BT_CHECKSUMFAIL_MASK) >> WTF_STATUS_BT_CHECKSUMFAIL_SHIFT)
-
-#define WTF_STATUS_SET_ERROR(error) { \
- UINT32 wtf_status_reg; \
- wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
- wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_ERROR_MASK) | (error << WTF_STATUS_ERROR_SHIFT); \
- wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_FW_INDICATOR_MASK) | (WTF_STATUS_FW_INDICATOR_UEFI << WTF_STATUS_FW_INDICATOR_SHIFT); \
- MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
-}
-
-#define WTF_STATUS_SET_POST(post) { \
- UINT32 wtf_status_reg; \
- wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
- wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_POST_MASK) | (post << WTF_STATUS_POST_SHIFT); \
- wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_FW_INDICATOR_MASK) | (WTF_STATUS_FW_INDICATOR_UEFI << WTF_STATUS_FW_INDICATOR_SHIFT); \
- MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
-}
-
-#define WTF_STATUS_SET_FW_INDICATOR(fwindicator) { \
- UINT32 wtf_status_reg; \
- wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
- wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_FW_INDICATOR_MASK) | (fwindicator << WTF_STATUS_FW_INDICATOR_SHIFT); \
- MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
-}
-
-#define WTF_STATUS_SET_BT_CHKSUMFAIL(btchksmfail) { \
- UINT32 wtf_status_reg; \
- wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \
- wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_BT_CHKSUMFAIL_MASK) | (btchksmfail << WTF_STATUS_BT_CHKSUMFAIL_SHIFT); \
- MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \
-}
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-/// WTF Status Structure
-typedef
-struct _WTF_STATUS_T {
- UINT64 error : WTF_STATUS_ERROR_SIZE; ///< WTF Status Error Size
- UINT64 post : WTF_STATUS_POST_SIZE; ///< WTF Status Post Size
- UINT64 fwindicator : WTF_STATUS_FW_INDICATOR_SIZE; ///< WTF Status Firmware Indicator Size
- UINT64 reserved : 7; ///< Reserved
- UINT64 btchksmfail : WTF_STATUS_BT_CHKSUMFAIL_SIZE; ///< WTF Status Bit Checksum Fail Size
-} WTF_STATUS_T;
-
-/// WTF Status Union
-typedef
-union {
- UINT32 val : 32; ///< Value
- WTF_STATUS_T f; ///< WTF Status Structure
-} WTF_STATUS_U;
-
-
-/****** DO NOT WRITE BELOW THIS LINE *******/
-#ifdef __cplusplus
-}
-#endif
-#endif
+/* $NoKeywords */ +/** + * @file + * + * Wtf_Reg.h + * + * Contains Where's-The-Firmware (WTF) definitions and Macros. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $ + * + */ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ + +#ifndef __WTF_REG__H_ +#define __WTF_REG__H_ + +#ifdef __cplusplus + extern "C" { + #endif + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define WTF_STATUS_REG 0xE0000000 // "Where's The Firmware" Register + +#define WTF_STATUS_REG_SIZE 32 +#define WTF_STATUS_ERROR_SIZE 12 +#define WTF_STATUS_POST_SIZE 10 +#define WTF_STATUS_FW_INDICATOR_SIZE 2 +#define WTF_STATUS_BT_CHKSUMFAIL_SIZE 1 + +#define WTF_STATUS_ERROR_SHIFT 0 +#define WTF_STATUS_POST_SHIFT 12 +#define WTF_STATUS_FW_INDICATOR_SHIFT 22 +#define WTF_STATUS_BT_CHKSUMFAIL_SHIFT 31 + +#define WTF_STATUS_ERROR_MASK 0x00000FFF +#define WTF_STATUS_POST_MASK 0x003FF000 +#define WTF_STATUS_FW_INDICATOR_MASK 0x00C00000 +#define WTF_STATUS_BT_CHKSUMFAIL_MASK 0x80000000 + +#define WTF_STATUS_MASK \ + (WTF_STATUS_ERROR_MASK | \ + WTF_STATUS_POST_MASK | \ + WTF_STATUS_FW_INDICATOR_MASK | \ + WTF_STATUS_BT_CHKSUMFAIL_MASK) + +#define WTF_STATUS_DEFAULT 0x00000000 +#define WTF_STATUS_FW_INDICATOR_UEFI 0x2 + +#define WTF_STATUS_GET_ERROR(wtf_status) \ + ((wtf_status & WTF_STATUS_ERROR_MASK) >> WTF_STATUS_ERROR_SHIFT) +#define WTF_STATUS_GET_POST(wtf_status) \ + ((wtf_status & WTF_STATUS_POST_MASK) >> WTF_STATUS_POST_SHIFT) +#define WTF_STATUS_GET_FW_INDICATOR(wtf_status) \ + ((wtf_status & WTF_STATUS_FW_INDICATOR_MASK) >> WTF_STATUS_FW_INDICATOR_SHIFT) +#define WTF_STATUS_GET_BT_CHKSUMFAIL(wtf_status) \ + ((wtf_status & WTF_STATUS_BT_CHECKSUMFAIL_MASK) >> WTF_STATUS_BT_CHECKSUMFAIL_SHIFT) + +#define WTF_STATUS_SET_ERROR(error) { \ + UINT32 wtf_status_reg; \ + wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \ + wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_ERROR_MASK) | (error << WTF_STATUS_ERROR_SHIFT); \ + wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_FW_INDICATOR_MASK) | (WTF_STATUS_FW_INDICATOR_UEFI << WTF_STATUS_FW_INDICATOR_SHIFT); \ + MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \ +} + +#define WTF_STATUS_SET_POST(post) { \ + UINT32 wtf_status_reg; \ + wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \ + wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_POST_MASK) | (post << WTF_STATUS_POST_SHIFT); \ + wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_FW_INDICATOR_MASK) | (WTF_STATUS_FW_INDICATOR_UEFI << WTF_STATUS_FW_INDICATOR_SHIFT); \ + MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \ +} + +#define WTF_STATUS_SET_FW_INDICATOR(fwindicator) { \ + UINT32 wtf_status_reg; \ + wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \ + wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_FW_INDICATOR_MASK) | (fwindicator << WTF_STATUS_FW_INDICATOR_SHIFT); \ + MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \ +} + +#define WTF_STATUS_SET_BT_CHKSUMFAIL(btchksmfail) { \ + UINT32 wtf_status_reg; \ + wtf_status_reg = MmioRead32 (WTF_STATUS_REG); \ + wtf_status_reg = (wtf_status_reg & ~WTF_STATUS_BT_CHKSUMFAIL_MASK) | (btchksmfail << WTF_STATUS_BT_CHKSUMFAIL_SHIFT); \ + MmioWrite32 (WTF_STATUS_REG, wtf_status_reg); \ +} + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +/// WTF Status Structure +typedef +struct _WTF_STATUS_T { + UINT64 error : WTF_STATUS_ERROR_SIZE; ///< WTF Status Error Size + UINT64 post : WTF_STATUS_POST_SIZE; ///< WTF Status Post Size + UINT64 fwindicator : WTF_STATUS_FW_INDICATOR_SIZE; ///< WTF Status Firmware Indicator Size + UINT64 reserved : 7; ///< Reserved + UINT64 btchksmfail : WTF_STATUS_BT_CHKSUMFAIL_SIZE; ///< WTF Status Bit Checksum Fail Size +} WTF_STATUS_T; + +/// WTF Status Union +typedef +union { + UINT32 val : 32; ///< Value + WTF_STATUS_T f; ///< WTF Status Structure +} WTF_STATUS_U; + + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif diff --git a/Silicon/AMD/Styx/AmdModulePkg/Gionb/Gionb.inf b/Silicon/AMD/Styx/AmdModulePkg/Gionb/Gionb.inf index b91dc93..453993d 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Gionb/Gionb.inf +++ b/Silicon/AMD/Styx/AmdModulePkg/Gionb/Gionb.inf @@ -1,49 +1,49 @@ -#**
-# @file
-#
-# Gionb.inf
-#
-# AMD-specific Gionb module information file.
-#
-# @xrefitem bom "File Content Label" "Release Content"
-# @e project: FDK
-# @e sub-project: UEFI
-# @e version: $Revision: 325775 $ @e date: $Date: 2015-08-31 17:45:22 -0500 (Mon, 31 Aug 2015) $
-#
-#
-#*****************************************************************************
-#
-# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#***************************************************************************/
-
-[Defines]
-INF_VERSION = 0x00010015
-VERSION_STRING = 1.0
-BASE_NAME = Gionb
-MODULE_TYPE = PEIM
-FILE_GUID = 3D65D81A-6E60-436F-951A-C9878BF77390
-ENTRY_POINT = PeiInitGionb
-
-[Binaries.AARCH64]
- PE32|Gionb.efi|*
- PEI_DEPEX|Gionb.depex|*
-
-[Packages]
- Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
-
-[PatchPcd]
- gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|2|0x8B60
- gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|TRUE|0x8C7C
- gAmdModulePkgTokenSpaceGuid.PcdPcieGenMax|2|0x8ECC
- gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|1|0x8ECD
- gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1|0x8ECE
- gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1|0x8ECF
+#** +# @file +# +# Gionb.inf +# +# AMD-specific Gionb module information file. +# +# @xrefitem bom "File Content Label" "Release Content" +# @e project: FDK +# @e sub-project: UEFI +# @e version: $Revision: 325775 $ @e date: $Date: 2015-08-31 17:45:22 -0500 (Mon, 31 Aug 2015) $ +# +# +#***************************************************************************** +# +# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#***************************************************************************/ + +[Defines] +INF_VERSION = 0x00010015 +VERSION_STRING = 1.0 +BASE_NAME = Gionb +MODULE_TYPE = PEIM +FILE_GUID = 3D65D81A-6E60-436F-951A-C9878BF77390 +ENTRY_POINT = PeiInitGionb + +[Binaries.AARCH64] + PE32|Gionb.efi|* + PEI_DEPEX|Gionb.depex|* + +[Packages] + Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec + +[PatchPcd] + gAmdModulePkgTokenSpaceGuid.PcdPcieCoreConfiguration|2|0x8B60 + gAmdModulePkgTokenSpaceGuid.PcdPcieHardcodeEnumeration|TRUE|0x8C7C + gAmdModulePkgTokenSpaceGuid.PcdPcieGenMax|2|0x8ECC + gAmdModulePkgTokenSpaceGuid.PcdPciePort0Present|1|0x8ECD + gAmdModulePkgTokenSpaceGuid.PcdPciePort1Present|1|0x8ECE + gAmdModulePkgTokenSpaceGuid.PcdPciePort2Present|1|0x8ECF diff --git a/Silicon/AMD/Styx/AmdModulePkg/Include/Library/AmdNvLib.h b/Silicon/AMD/Styx/AmdModulePkg/Include/Library/AmdNvLib.h index 20a234a..7413369 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Include/Library/AmdNvLib.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Include/Library/AmdNvLib.h @@ -1,78 +1,78 @@ -/* $NoKeywords */
-/**
- * @file
- *
- * AmdNvLib.c
- *
- * Provides library calls for NV (SPI and EEPROM) access.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e version: $Revision: 306428 $ @e date: $Date: 2014-10-23 14:42:26 -0500 (Thu, 23 Oct 2014) $
- *
- */
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-
-#ifndef _AMD_NV_H_
-#define _AMD_NV_H_
-#ifdef __cplusplus
- extern "C" {
- #endif
-
- #pragma pack(1)
-
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-#define EEPROM_PAGE_SIZE 0x2000 // 8K block size
-#define EEPROM_ERASE_POLARITY 0x1 // Erase Polarity Positive (all bits ON)
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S
- *----------------------------------------------------------------------------------------
- */
-
- VOID
- AmdNvEepromRead (
- volatile UINT8 *Address,
- UINT8 *Data,
- UINT32 *Size
- );
-
- VOID
- AmdNvEepromWrite (
- volatile UINT8 *Address,
- UINT8 *Data,
- UINT32 *Size
- );
-
- VOID
- AmdNvEepromErase (
- volatile UINT8 *Address,
- UINT32 *Size
- );
-
- #pragma pack()
-
-/****** DO NOT WRITE BELOW THIS LINE *******/
- #ifdef __cplusplus
- }
-#endif
-#endif
-
+/* $NoKeywords */ +/** + * @file + * + * AmdNvLib.c + * + * Provides library calls for NV (SPI and EEPROM) access. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e version: $Revision: 306428 $ @e date: $Date: 2014-10-23 14:42:26 -0500 (Thu, 23 Oct 2014) $ + * + */ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ + +#ifndef _AMD_NV_H_ +#define _AMD_NV_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #pragma pack(1) + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define EEPROM_PAGE_SIZE 0x2000 // 8K block size +#define EEPROM_ERASE_POLARITY 0x1 // Erase Polarity Positive (all bits ON) + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S + *---------------------------------------------------------------------------------------- + */ + + VOID + AmdNvEepromRead ( + volatile UINT8 *Address, + UINT8 *Data, + UINT32 *Size + ); + + VOID + AmdNvEepromWrite ( + volatile UINT8 *Address, + UINT8 *Data, + UINT32 *Size + ); + + VOID + AmdNvEepromErase ( + volatile UINT8 *Address, + UINT32 *Size + ); + + #pragma pack() + +/****** DO NOT WRITE BELOW THIS LINE *******/ + #ifdef __cplusplus + } +#endif +#endif + diff --git a/Silicon/AMD/Styx/AmdModulePkg/Include/Library/AmdSataInitLib.h b/Silicon/AMD/Styx/AmdModulePkg/Include/Library/AmdSataInitLib.h index a5a6039..338a215 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Include/Library/AmdSataInitLib.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Include/Library/AmdSataInitLib.h @@ -1,150 +1,150 @@ -/* $NoKeywords */
-/**
- * @file
- *
- * AmdSataInitLib.h
- *
- * Public SATA PHY layer initilization and training routines for Serdes registers.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e version: $Revision: 338015 $ @e date: $Date: 2016-04-04 10:40:16 -0500 (Mon, 04 Apr 2016) $
- *
- */
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-
-#ifndef _AMD_SATA_INIT_LIB_H_
-#define _AMD_SATA_INIT_LIB_H_
-#ifdef __cplusplus
- extern "C" {
- #endif
-
- /**
- *---------------------------------------------------------------------------------------
- *
- * SataPhyInit
- *
- * Description:
- * Library call that trains the SATA PHY.
- *
- * Control flow:
- * 1. Initialize variables
- * 2. Continue to set Serdes bits while not locked
- *
- * Parameters:
- * @param[in] cmu_number Cmu block number. Port 0,1 belongs to CMU 0
- * @param[in] EvenPortGen Port Gen value for even port in given CMU
- * @param[in] OddPortGen Port Gen Value for Odd Port in given CMU
- *
- * @return VOID
- *
- *------------------------------------------------------------------------------------
- **/
- VOID
- EFIAPI
- SataPhyInit (
- IN UINT32 cmu_number,
- IN UINT32 EvenPortGen,
- IN UINT32 OddPortGen
- );
-
- /**
- *---------------------------------------------------------------------------------------
- *
- * SetCwMinSata0
- *
- * Description:
- *
- * Parameters:
- * @param[in] Portnum Port number
- *
- * @return VOID
- *
- *------------------------------------------------------------------------------------
- **/
- VOID
- EFIAPI
- SetCwMinSata0 (
- IN UINT32 Portnum
- );
-
- /**
- *---------------------------------------------------------------------------------------
- *
- * SetCwMinSata1
- *
- * Description:
- *
- * Parameters:
- * @param[in] Portnum Port number
- *
- * @return VOID
- *
- *------------------------------------------------------------------------------------
- **/
- VOID
- EFIAPI
- SetCwMinSata1 (
- IN UINT32 Portnum
- );
-
- /**
- *---------------------------------------------------------------------------------------
- *
- * SetPrdSingleSata0
- *
- * Description:
- *
- * Parameters:
- * @param[in] Portnum Port number
- *
- * @return VOID
- *
- *------------------------------------------------------------------------------------
- **/
- VOID
- EFIAPI
- SetPrdSingleSata0 (
- IN UINT32 Portnum
- );
-
- /**
- *---------------------------------------------------------------------------------------
- *
- * SetPrdSingleSata1
- *
- * Description:
- *
- * Parameters:
- * @param[in] Portnum Port number
- *
- * @return VOID
- *
- *------------------------------------------------------------------------------------
- **/
- VOID
- EFIAPI
- SetPrdSingleSata1 (
- IN UINT32 Portnum
- );
-
-/****** DO NOT WRITE BELOW THIS LINE *******/
- #ifdef __cplusplus
- }
-#endif
-#endif
-
+/* $NoKeywords */ +/** + * @file + * + * AmdSataInitLib.h + * + * Public SATA PHY layer initilization and training routines for Serdes registers. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e version: $Revision: 338015 $ @e date: $Date: 2016-04-04 10:40:16 -0500 (Mon, 04 Apr 2016) $ + * + */ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ + +#ifndef _AMD_SATA_INIT_LIB_H_ +#define _AMD_SATA_INIT_LIB_H_ +#ifdef __cplusplus + extern "C" { + #endif + + /** + *--------------------------------------------------------------------------------------- + * + * SataPhyInit + * + * Description: + * Library call that trains the SATA PHY. + * + * Control flow: + * 1. Initialize variables + * 2. Continue to set Serdes bits while not locked + * + * Parameters: + * @param[in] cmu_number Cmu block number. Port 0,1 belongs to CMU 0 + * @param[in] EvenPortGen Port Gen value for even port in given CMU + * @param[in] OddPortGen Port Gen Value for Odd Port in given CMU + * + * @return VOID + * + *------------------------------------------------------------------------------------ + **/ + VOID + EFIAPI + SataPhyInit ( + IN UINT32 cmu_number, + IN UINT32 EvenPortGen, + IN UINT32 OddPortGen + ); + + /** + *--------------------------------------------------------------------------------------- + * + * SetCwMinSata0 + * + * Description: + * + * Parameters: + * @param[in] Portnum Port number + * + * @return VOID + * + *------------------------------------------------------------------------------------ + **/ + VOID + EFIAPI + SetCwMinSata0 ( + IN UINT32 Portnum + ); + + /** + *--------------------------------------------------------------------------------------- + * + * SetCwMinSata1 + * + * Description: + * + * Parameters: + * @param[in] Portnum Port number + * + * @return VOID + * + *------------------------------------------------------------------------------------ + **/ + VOID + EFIAPI + SetCwMinSata1 ( + IN UINT32 Portnum + ); + + /** + *--------------------------------------------------------------------------------------- + * + * SetPrdSingleSata0 + * + * Description: + * + * Parameters: + * @param[in] Portnum Port number + * + * @return VOID + * + *------------------------------------------------------------------------------------ + **/ + VOID + EFIAPI + SetPrdSingleSata0 ( + IN UINT32 Portnum + ); + + /** + *--------------------------------------------------------------------------------------- + * + * SetPrdSingleSata1 + * + * Description: + * + * Parameters: + * @param[in] Portnum Port number + * + * @return VOID + * + *------------------------------------------------------------------------------------ + **/ + VOID + EFIAPI + SetPrdSingleSata1 ( + IN UINT32 Portnum + ); + +/****** DO NOT WRITE BELOW THIS LINE *******/ + #ifdef __cplusplus + } +#endif +#endif + diff --git a/Silicon/AMD/Styx/AmdModulePkg/Include/Ppi/GionbPpi.h b/Silicon/AMD/Styx/AmdModulePkg/Include/Ppi/GionbPpi.h index 85b088c..b1e1769 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Include/Ppi/GionbPpi.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Include/Ppi/GionbPpi.h @@ -1,78 +1,78 @@ -/* $NoKeywords */
-/**
- * @file
- *
- * GionbPpi.h
- *
- * GioNb Protocol-Protocol Interface header file.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
- *
- */
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-
-
-#ifndef _PEI_GIONB_PPI_H_
-#define _PEI_GIONB_PPI_H_
-
-///
-/// Global ID for the PEI_GIONB_PPI.
-///
-#define PEI_GIONB_PPI_GUID \
-{ \
- 0x24b8ebcc, 0x3871, 0x4b39, { 0xaa, 0x1a, 0xf, 0x86, 0x7d, 0xbf, 0x97, 0xc6 } \
-}
-
-///
-/// Forward declaration for the PEI_CAPSULE_PPI.
-///
-typedef struct _EFI_PEI_GIONB_PPI EFI_PEI_GIONB_PPI;
-
-/**
- *---------------------------------------------------------------------------------------
- *
- * PEI_INIT_GIONB_REGISTERS
- *
- * Description:
- * Initialize GIONB registers.
- *
- * Parameters:
- * @param[in] **PeiServices Pointer to the PEI
- * Services Table.
- *
- * @return EFI_STATUS
- *
- *---------------------------------------------------------------------------------------
- **/
-typedef
-EFI_STATUS
-(EFIAPI *PEI_INIT_GIONB_REGISTERS)(
- IN CONST EFI_PEI_SERVICES **PeiServices
- );
-
-///
-/// This PPI provides several services in PEI to initialize and configure GIO NB registers.
-///
-struct _EFI_PEI_GIONB_PPI {
- PEI_INIT_GIONB_REGISTERS GioNbEarlyInit;
-};
-
-extern EFI_GUID gPeiGionbPpiGuid;
-
-#endif // #ifndef _PEI_GIONB_PPI_H_
+/* $NoKeywords */ +/** + * @file + * + * GionbPpi.h + * + * GioNb Protocol-Protocol Interface header file. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $ + * + */ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ + + +#ifndef _PEI_GIONB_PPI_H_ +#define _PEI_GIONB_PPI_H_ + +/// +/// Global ID for the PEI_GIONB_PPI. +/// +#define PEI_GIONB_PPI_GUID \ +{ \ + 0x24b8ebcc, 0x3871, 0x4b39, { 0xaa, 0x1a, 0xf, 0x86, 0x7d, 0xbf, 0x97, 0xc6 } \ +} + +/// +/// Forward declaration for the PEI_CAPSULE_PPI. +/// +typedef struct _EFI_PEI_GIONB_PPI EFI_PEI_GIONB_PPI; + +/** + *--------------------------------------------------------------------------------------- + * + * PEI_INIT_GIONB_REGISTERS + * + * Description: + * Initialize GIONB registers. + * + * Parameters: + * @param[in] **PeiServices Pointer to the PEI + * Services Table. + * + * @return EFI_STATUS + * + *--------------------------------------------------------------------------------------- + **/ +typedef +EFI_STATUS +(EFIAPI *PEI_INIT_GIONB_REGISTERS)( + IN CONST EFI_PEI_SERVICES **PeiServices + ); + +/// +/// This PPI provides several services in PEI to initialize and configure GIO NB registers. +/// +struct _EFI_PEI_GIONB_PPI { + PEI_INIT_GIONB_REGISTERS GioNbEarlyInit; +}; + +extern EFI_GUID gPeiGionbPpiGuid; + +#endif // #ifndef _PEI_GIONB_PPI_H_ diff --git a/Silicon/AMD/Styx/AmdModulePkg/Include/Ppi/IscpPpi.h b/Silicon/AMD/Styx/AmdModulePkg/Include/Ppi/IscpPpi.h index ca59b11..12a6ed9 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Include/Ppi/IscpPpi.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Include/Ppi/IscpPpi.h @@ -1,219 +1,219 @@ -/* $NoKeywords */
-/**
- * @file
- *
- * IscpPpi.h
- *
- * Contains Intra-SoC Communication Protocol-Protocol Interface definitions.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $
- *
- */
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-
-
-#ifndef _PEI_ISCP_PPI_H_
-#define _PEI_ISCP_PPI_H_
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include <Iscp.h>
-
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-#define PEI_ISCP_PPI_GUID {\
- 0xca2c1ecd, 0xc702, 0x49b1, { 0xae, 0x24, 0x9b, 0x6f, 0xa8, 0x71, 0x3b, 0x23 } \
-}
-
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-typedef struct _EFI_PEI_ISCP_PPI EFI_PEI_ISCP_PPI;
-
-
-/// ISCP Memory Transaction
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_MEMORY_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- IN OUT AMD_MEMORY_RANGE_DESCRIPTOR *MemRangeDescriptor ///< Pointer to Memory Range Descriptor
- );
-
-
-/// ISCP Fuse Transaction
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_FUSE_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- IN OUT ISCP_FUSE_INFO *FuseInfo ///< Pointer to the Fuse Info structure
- );
-
-
-/// ISCP CPU Retrieve ID Transaction
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_CPU_RETRIEVE_ID_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- IN OUT ISCP_CPU_RESET_INFO *CpuResetInfo ///< Pointer to CPU Reset Info structure
- );
-
-
-/// ISCP CPU Reset transaction
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_CPU_RESET_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- IN OUT ISCP_CPU_RESET_INFO *CpuResetInfo ///< Pointer to CPU Reset Info structure
- );
-
-
-/// ISCP Get Real-Time-Clock Transaction
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_GET_RTC_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- IN OUT ISCP_RTC_INFO *RtcInfo ///< Pointer to the Real-Time-Clock
- );
-
-
-/// ISCP Set Real-Time-Clock Transaction
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_SET_RTC_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- IN OUT ISCP_RTC_INFO *RtcInfo ///< Pointer to the Real-Time-Clock
- );
-
-
-/// ISCP Get MAC Address Transaction
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_GET_MAC_ADDRESS_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- IN OUT ISCP_MAC_INFO *MacInfo ///< Pointer to the MAC Address info
- );
-
-
-/// ISCP Set MAC Address Transaction
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_SET_MAC_ADDRESS_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- IN OUT ISCP_MAC_INFO *MacInfo ///< Pointer to the MAC Address info
- );
-
-
-/// ISCP Update Firmware Volume Block Transaction
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_UPDATE_FV_BLOCK_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- IN CONST UINT32 Offset, ///< Offset from base of FV Block
- IN OUT UINT8 *NvData, ///< Pointer to the NV data being stored
- IN CONST UINT32 NvSize ///< Size of NV Data being stored
- );
-
-
-/// SCP Load Firmware Volume Block Transaction
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_LOAD_FV_BLOCK_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- IN CONST UINT32 Offset, ///< Offset from base of FV Block
- IN OUT UINT8 *NvData, ///< Pointer to the NV data being stored
- IN CONST UINT32 NvSize ///< Size of NV Data being stored
- );
-
-
-/// ISCP Erase Firmware Volume Block Transaction
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_ERASE_FV_BLOCK_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- IN CONST UINT32 Offset, ///< Offset from base of FV Block
- IN CONST UINT32 NvSize ///< Size of NV Data being stored
- );
-
-
-/// ISCP PCIE Reset Transaction
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_PCIE_RESET_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- IN OUT ISCP_PCIE_RESET_INFO *PcieResetInfo ///< Pointer to PCIE Reset info structure
- );
-
-
-/// ISCP Send UART Config Transaction
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_SEND_UART_CONFIG_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- IN OUT ISCP_UART_INFO *UartInfo ///< Pointer to UART Config info structure
- );
-
-/// ISCP Sata1 get Transaction
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_SATA1_GET_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- IN OUT ISCP_SATA1_RESET_INFO *Sata1ResetInfo ///< Pointer to SATA1 reset structure
- );
-
-/// ISCP BMC Present
-typedef
-EFI_STATUS
-(EFIAPI *PEI_ISCP_BMC_PRESENT_TRANSACTION)(
- IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table
- OUT ISCP_BMC_PRESENCE_INFO *BmcPresenceInfo ///< Pointer to BMC presence structure
- );
-
-/// This PPI provides several services in PEI to work with the underlying
-/// Intra-SOC Communication Protocol capabilities of the platform. These
-/// services include the ability for PEI to send/receive Firmware Setup data,
-/// retrieve memory data, retrieve fuse data, perform CPU core reset, e.g launch,
-/// retrieve OEM NVRAM transactions.
-struct _EFI_PEI_ISCP_PPI {
- PEI_ISCP_MEMORY_TRANSACTION ExecuteMemoryTransaction;
- PEI_ISCP_FUSE_TRANSACTION ExecuteFuseTransaction;
- PEI_ISCP_CPU_RETRIEVE_ID_TRANSACTION ExecuteCpuRetrieveIdTransaction;
- PEI_ISCP_CPU_RESET_TRANSACTION ExecuteCpuResetTransaction;
- PEI_ISCP_GET_RTC_TRANSACTION ExecuteGetRtcTransaction;
- PEI_ISCP_SET_RTC_TRANSACTION ExecuteSetRtcTransaction;
- PEI_ISCP_GET_MAC_ADDRESS_TRANSACTION ExecuteGetMacAddressTransaction;
- PEI_ISCP_SET_MAC_ADDRESS_TRANSACTION ExecuteSetMacAddressTransaction;
- PEI_ISCP_UPDATE_FV_BLOCK_TRANSACTION ExecuteUpdateFvBlock;
- PEI_ISCP_LOAD_FV_BLOCK_TRANSACTION ExecuteLoadNvBlock;
- PEI_ISCP_ERASE_FV_BLOCK_TRANSACTION ExecuteEraseNvBlock;
- PEI_ISCP_PCIE_RESET_TRANSACTION ExecutePcieResetTransaction;
- PEI_ISCP_SEND_UART_CONFIG_TRANSACTION ExecuteSendUartConfigTransaction;
- PEI_ISCP_SATA1_GET_TRANSACTION ExecuteSata1GetTransaction;
- PEI_ISCP_BMC_PRESENT_TRANSACTION ExecuteBmcPresentTransaction;
-};
-
-extern EFI_GUID gPeiIscpPpiGuid;
-
-#endif // #ifndef _PEI_ISCP_PPI_H_
+/* $NoKeywords */ +/** + * @file + * + * IscpPpi.h + * + * Contains Intra-SoC Communication Protocol-Protocol Interface definitions. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e version: $Revision: 334098 $ @e date: $Date: 2016-01-08 14:21:15 -0600 (Fri, 08 Jan 2016) $ + * + */ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ + + +#ifndef _PEI_ISCP_PPI_H_ +#define _PEI_ISCP_PPI_H_ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include <Iscp.h> + + +/*---------------------------------------------------------------------------------------- + * D E F I N I T I O N S A N D M A C R O S + *---------------------------------------------------------------------------------------- + */ +#define PEI_ISCP_PPI_GUID {\ + 0xca2c1ecd, 0xc702, 0x49b1, { 0xae, 0x24, 0x9b, 0x6f, 0xa8, 0x71, 0x3b, 0x23 } \ +} + + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +typedef struct _EFI_PEI_ISCP_PPI EFI_PEI_ISCP_PPI; + + +/// ISCP Memory Transaction +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_MEMORY_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + IN OUT AMD_MEMORY_RANGE_DESCRIPTOR *MemRangeDescriptor ///< Pointer to Memory Range Descriptor + ); + + +/// ISCP Fuse Transaction +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_FUSE_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + IN OUT ISCP_FUSE_INFO *FuseInfo ///< Pointer to the Fuse Info structure + ); + + +/// ISCP CPU Retrieve ID Transaction +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_CPU_RETRIEVE_ID_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + IN OUT ISCP_CPU_RESET_INFO *CpuResetInfo ///< Pointer to CPU Reset Info structure + ); + + +/// ISCP CPU Reset transaction +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_CPU_RESET_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + IN OUT ISCP_CPU_RESET_INFO *CpuResetInfo ///< Pointer to CPU Reset Info structure + ); + + +/// ISCP Get Real-Time-Clock Transaction +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_GET_RTC_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + IN OUT ISCP_RTC_INFO *RtcInfo ///< Pointer to the Real-Time-Clock + ); + + +/// ISCP Set Real-Time-Clock Transaction +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_SET_RTC_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + IN OUT ISCP_RTC_INFO *RtcInfo ///< Pointer to the Real-Time-Clock + ); + + +/// ISCP Get MAC Address Transaction +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_GET_MAC_ADDRESS_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + IN OUT ISCP_MAC_INFO *MacInfo ///< Pointer to the MAC Address info + ); + + +/// ISCP Set MAC Address Transaction +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_SET_MAC_ADDRESS_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + IN OUT ISCP_MAC_INFO *MacInfo ///< Pointer to the MAC Address info + ); + + +/// ISCP Update Firmware Volume Block Transaction +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_UPDATE_FV_BLOCK_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + IN CONST UINT32 Offset, ///< Offset from base of FV Block + IN OUT UINT8 *NvData, ///< Pointer to the NV data being stored + IN CONST UINT32 NvSize ///< Size of NV Data being stored + ); + + +/// SCP Load Firmware Volume Block Transaction +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_LOAD_FV_BLOCK_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + IN CONST UINT32 Offset, ///< Offset from base of FV Block + IN OUT UINT8 *NvData, ///< Pointer to the NV data being stored + IN CONST UINT32 NvSize ///< Size of NV Data being stored + ); + + +/// ISCP Erase Firmware Volume Block Transaction +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_ERASE_FV_BLOCK_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + IN CONST UINT32 Offset, ///< Offset from base of FV Block + IN CONST UINT32 NvSize ///< Size of NV Data being stored + ); + + +/// ISCP PCIE Reset Transaction +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_PCIE_RESET_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + IN OUT ISCP_PCIE_RESET_INFO *PcieResetInfo ///< Pointer to PCIE Reset info structure + ); + + +/// ISCP Send UART Config Transaction +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_SEND_UART_CONFIG_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + IN OUT ISCP_UART_INFO *UartInfo ///< Pointer to UART Config info structure + ); + +/// ISCP Sata1 get Transaction +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_SATA1_GET_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + IN OUT ISCP_SATA1_RESET_INFO *Sata1ResetInfo ///< Pointer to SATA1 reset structure + ); + +/// ISCP BMC Present +typedef +EFI_STATUS +(EFIAPI *PEI_ISCP_BMC_PRESENT_TRANSACTION)( + IN CONST EFI_PEI_SERVICES **PeiServices, ///< Pointer to the PEI Services Table + OUT ISCP_BMC_PRESENCE_INFO *BmcPresenceInfo ///< Pointer to BMC presence structure + ); + +/// This PPI provides several services in PEI to work with the underlying +/// Intra-SOC Communication Protocol capabilities of the platform. These +/// services include the ability for PEI to send/receive Firmware Setup data, +/// retrieve memory data, retrieve fuse data, perform CPU core reset, e.g launch, +/// retrieve OEM NVRAM transactions. +struct _EFI_PEI_ISCP_PPI { + PEI_ISCP_MEMORY_TRANSACTION ExecuteMemoryTransaction; + PEI_ISCP_FUSE_TRANSACTION ExecuteFuseTransaction; + PEI_ISCP_CPU_RETRIEVE_ID_TRANSACTION ExecuteCpuRetrieveIdTransaction; + PEI_ISCP_CPU_RESET_TRANSACTION ExecuteCpuResetTransaction; + PEI_ISCP_GET_RTC_TRANSACTION ExecuteGetRtcTransaction; + PEI_ISCP_SET_RTC_TRANSACTION ExecuteSetRtcTransaction; + PEI_ISCP_GET_MAC_ADDRESS_TRANSACTION ExecuteGetMacAddressTransaction; + PEI_ISCP_SET_MAC_ADDRESS_TRANSACTION ExecuteSetMacAddressTransaction; + PEI_ISCP_UPDATE_FV_BLOCK_TRANSACTION ExecuteUpdateFvBlock; + PEI_ISCP_LOAD_FV_BLOCK_TRANSACTION ExecuteLoadNvBlock; + PEI_ISCP_ERASE_FV_BLOCK_TRANSACTION ExecuteEraseNvBlock; + PEI_ISCP_PCIE_RESET_TRANSACTION ExecutePcieResetTransaction; + PEI_ISCP_SEND_UART_CONFIG_TRANSACTION ExecuteSendUartConfigTransaction; + PEI_ISCP_SATA1_GET_TRANSACTION ExecuteSata1GetTransaction; + PEI_ISCP_BMC_PRESENT_TRANSACTION ExecuteBmcPresentTransaction; +}; + +extern EFI_GUID gPeiIscpPpiGuid; + +#endif // #ifndef _PEI_ISCP_PPI_H_ diff --git a/Silicon/AMD/Styx/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h b/Silicon/AMD/Styx/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h index 50db778..baa3809 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Include/Protocol/AmdIscpDxeProtocol.h @@ -1,308 +1,308 @@ -/* $NoKeywords */
-/**
- * @file
- *
- * AmdIscpDxeProtocol.h
- *
- * Contains Intra-SoC Communication DXE Protocol definitions.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e version: $Revision: 337020 $ @e date: $Date: 2016-03-02 11:49:34 -0600 (Wed, 02 Mar 2016) $
- *
- */
-/*****************************************************************************
-*
-* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
-*
-* This program and the accompanying materials are licensed and made available
-* under the terms and conditions of the BSD License which accompanies this
-* distribution. The full text of the license may be found at
-* http://opensource.org/licenses/bsd-license.php
-*
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
-* IMPLIED.
-*
-***************************************************************************/
-
-#ifndef __AMD_ISCP_DXE_PROTOCOL__H_
-#define __AMD_ISCP_DXE_PROTOCOL__H_
-
-/*----------------------------------------------------------------------------------------
- * M O D U L E S U S E D
- *----------------------------------------------------------------------------------------
- */
-#include <Iscp.h>
-
-
-/*----------------------------------------------------------------------------------------
- * G U I D D E F I N I T I O N
- *----------------------------------------------------------------------------------------
- */
-#define AMD_ISCP_DXE_PROTOCOL_GUID {\
- 0x5c794c8, 0x6aef, 0x4450, 0x91, 0x78, 0xca, 0x70, 0x53, 0x75, 0xbd, 0x91 \
-}
-
-/*----------------------------------------------------------------------------------------
- * E X T E R N S
- *----------------------------------------------------------------------------------------
- */
-extern EFI_GUID gAmdIscpDxeProtocolGuid;
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S A N D S T R U C T U R E S
- *----------------------------------------------------------------------------------------
- */
-typedef struct _AMD_ISCP_DXE_PROTOCOL AMD_ISCP_DXE_PROTOCOL;
-
- /// HEST Notification type
- typedef enum {
- HEST_NOTIFY_POLLED = 0, ///< Polled
- HEST_NOTIFY_GPIO = 7, ///< GPIO-Signal
- } HEST_NOTIFY_TYPE;
-
- /// Trusted Firmware Generic Error Source structure
- typedef struct {
- UINT32 IscpVersion; ///< Version of BERT Region structure
- UINT8 SourceGUID[16]; ///< ACPI v6.0: Table 18-331 [Section Type]
- UINT64 ErrorStatusPhysAddr; ///< ACPI v6.0: Table 18-329 [Error Status Address]
- UINT32 ErrorStatusLength; ///< ACPI v6.0: Table 18-329 [Error Status Block Length]
- HEST_NOTIFY_TYPE NotificationType; ///< ACPI v6.0: Table 18-332 [Type]
- } ISCP_TFW_GENERIC_ERROR_SOURCE;
-
-/// CPU Core Reset Prototype
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_CPU_CORE_RESET) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN OUT ISCP_CPU_RESET_INFO *CpuResetInfo ///< Pointer to CPU Reset Info structure
- );
-
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_CPU_RETRIEVE_ID) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN OUT ISCP_CPU_RESET_INFO *CpuResetInfo ///< Pointer to CPU Reset Info structure
- );
-
-/// ISCP call to get MAC Address
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_GET_MAC_ADDRESS) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN OUT ISCP_MAC_INFO *MacInfo ///< Pointer to the Firmware MAC Address structure
- );
-
-
-/// ISCP call to set MAC Address
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_SET_MAC_ADDRESS) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN OUT ISCP_MAC_INFO *MacInfo ///< Pointer to the Firmware MAC Address structure
- );
-
-
-/// ISCP call to get Real-Time-Clock
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_GET_RTC) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN OUT ISCP_RTC_INFO *RtcInfo ///< Pointer to the Real-Time-Clock structure
- );
-
-
-/// ISCP call to set Real-Time-Clock
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_SET_RTC) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN OUT ISCP_RTC_INFO *RtcInfo ///< Pointer to the Real-Time-Clock structure
- );
-
-
-/// Update Firmware Volume Block into SPI from local memory
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_UPDATE_FV_BLOCK_DXE) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN CONST UINT32 Offset, ///< Offset to base of Firmware Volume Block
- IN OUT UINT8 *NvData, ///< Pointer to data being stored in FV Block
- IN CONST UINT32 NvSize ///< Size of data being stored FV Block
- );
-
-
-/// Load Firmware Volume Block from SPI into local memory
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_LOAD_FV_BLOCK_DXE) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN CONST UINT32 Offset, ///< Offset to base of Firmware Volume Block
- IN OUT UINT8 *NvData, ///< Pointer to data being stored in FV Block
- IN CONST UINT32 NvSize ///< Size of data being retrieved from FV Block
- );
-
-
-/// Erase Firmware Volume Block Prototype
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_ERASE_FV_BLOCK_DXE) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN CONST UINT32 Offset, ///< Offset to base of Firmware Volume Block
- IN CONST UINT32 NvSize ///< Size of data being erased
- );
-
-
-/// Update EEPROM Block from local memory prototype
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_UPDATE_EEPROM_BLOCK_DXE) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN CONST UINT32 Offset, ///< Offset to base of EEPROM Block
- IN OUT UINT8 *Data, ///< Pointer to data being stored in EEPROM Block
- IN CONST UINT32 Size ///< Size of data being stored EEPROM Block
- );
-
-
-/// Load EEPROM Block into local memory prototype
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_LOAD_EEPROM_BLOCK_DXE) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN CONST UINT32 Offset, ///< Offset to base of EEPROM Block
- IN OUT UINT8 *Data, ///< Pointer to data being stored in EEPROM Block
- IN CONST UINT32 Size ///< Size of data being retrieved from EEPROM Block
- );
-
-
-/// Erase EEPROM Block prototype
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_ERASE_EEPROM_BLOCK_DXE) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN CONST UINT32 Offset, ///< Offset to base of EEPROM Block
- IN CONST UINT32 Size ///< Size of data being erased
- );
-
-
-/// Issue ISCP Doorbell command
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_GET_BMC_IP_ADDRESS) (
- IN AMD_ISCP_DXE_PROTOCOL *This,
- IN OUT ISCP_BMC_IP_ADDRESS_INFO *BmcIpAddressInfo
- );
-
-/// Issue ISCP command to retrieve SMBIOS info
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_SMBIOS_INFO) (
- IN AMD_ISCP_DXE_PROTOCOL *This,
- IN OUT ISCP_SMBIOS_INFO *SmbiosInfo
- );
-
-/// Issue ISCP command to issue SoC shutdown command
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_SOC_SHUTDOWN) (
- IN AMD_ISCP_DXE_PROTOCOL *This
- );
-
-/// Issue ISCP command to issue SoC reset command
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_SOC_RESET) (
- IN AMD_ISCP_DXE_PROTOCOL *This
- );
-
-/// ISCP call to set Memory Set up Nodes
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_MEM_SETUP) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN OUT MEM_SETUP_VAR *SetupInfo ///< Pointer to the Firmware MAC Address structure
- );
-
-/// Issue Override Command
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_OVERRIDE_CMD) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN ISCP_OVERRIDE_CMD_INFO *OverrideCmdInfo ///< Pointer to the Overrride Command structure
- );
-
-/// Issue Sata1 get state
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_SATA1_GET) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN OUT ISCP_SATA1_RESET_INFO *Sata1ResetInfo ///< Pointer to the SATA1 reset structure
- );
-
-/// Issue Sata1 set state
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_SATA1_SET) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- IN ISCP_SATA1_RESET_INFO *Sata1ResetInfo ///< Pointer to the SATA1 reset structure
- );
-
-/// Issue BMC presence check
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_BMC_PRESENT) (
- IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL
- OUT ISCP_BMC_PRESENCE_INFO *BmcPresenceInfo ///< Pointer to BMC presence structure
- );
-
-/// Register Boot Error Region
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_RETRIEVE_BERT_RECORD) (
- IN AMD_ISCP_DXE_PROTOCOL *This,
- IN OUT ISCP_BERT_REGION_INFO *BertRegionInfo
- );
-
-/// Register generic hardware error soure
-typedef
-EFI_STATUS
-(EFIAPI *AMD_EXECUTE_REGISTER_ERROR_SOURCE) (
- IN AMD_ISCP_DXE_PROTOCOL *This,
- IN ISCP_TFW_GENERIC_ERROR_SOURCE *GenericErrorSource
- );
-
-
-/*----------------------------------------------------------------------------------------
- * P R O T O C O L S T R U C T U R E
- *----------------------------------------------------------------------------------------
- */
-/// ISCP DXE Protocol Structure
-struct _AMD_ISCP_DXE_PROTOCOL {
- AMD_EXECUTE_CPU_CORE_RESET AmdExecuteCpuCoreReset; ///< Execute CPU Core Reset
- AMD_EXECUTE_CPU_RETRIEVE_ID AmdExecuteCpuRetrieveId; ///< Execute CPU Retrieve ID
- AMD_EXECUTE_GET_MAC_ADDRESS AmdExecuteGetMacAddress; ///< Execute Get MAC Address
- AMD_EXECUTE_SET_MAC_ADDRESS AmdExecuteSetMacAddress; ///< Execute Set MAC Address
- AMD_EXECUTE_GET_RTC AmdExecuteGetRtc; ///< Execute Get Real-Time-Clock Time
- AMD_EXECUTE_SET_RTC AmdExecuteSetRtc; ///< Execute Set Real-Time-Clock Time
- AMD_EXECUTE_UPDATE_FV_BLOCK_DXE AmdExecuteUpdateFvBlockDxe; ///< Execute Update FV Block Data on the SPI device
- AMD_EXECUTE_LOAD_FV_BLOCK_DXE AmdExecuteLoadFvBlockDxe; ///< Execute Load FV Block Data from the SPI device
- AMD_EXECUTE_ERASE_FV_BLOCK_DXE AmdExecuteEraseFvBlockDxe; ///< Execute Erase FV Block Data on the SPI device
- AMD_EXECUTE_UPDATE_EEPROM_BLOCK_DXE AmdExecuteUpdateEepromBlockDxe; ///< Execute Update EEPROM Data on the EEPROM device
- AMD_EXECUTE_LOAD_EEPROM_BLOCK_DXE AmdExecuteLoadEepromBlockDxe; ///< Execute Load EEPROM Data on the EEPROM device
- AMD_EXECUTE_ERASE_EEPROM_BLOCK_DXE AmdExecuteEraseEepromBlockDxe; ///< Execute Erase EEPROM Data on the EEPROM device
- AMD_EXECUTE_GET_BMC_IP_ADDRESS AmdExecuteGetBmcIpAddress; ///< Execute Get BMC IP Address
- AMD_EXECUTE_SMBIOS_INFO AmdExecuteSmbiosInfoDxe; ///< Execute SMBIOS info
- AMD_EXECUTE_SOC_SHUTDOWN AmdExecuteSocShutdownDxe; ///< Execute SoC Shutdown
- AMD_EXECUTE_SOC_RESET AmdExecuteSocResetDxe; ///< Execute SoC Reset
- AMD_EXECUTE_MEM_SETUP AmdExecuteMemSetup; ///< Execute Set MAC Address
- AMD_EXECUTE_OVERRIDE_CMD AmdExecuteOverrideCmd; ///< Execute Override Command
- AMD_EXECUTE_SATA1_GET AmdExecuteSata1Get; ///< Execute Sata1 get state
- AMD_EXECUTE_SATA1_SET AmdExecuteSata1Set; ///< Execute Sata1 set state
- AMD_EXECUTE_BMC_PRESENT AmdExecuteBmcPresent; ///< Execute BMC presence check
- AMD_EXECUTE_RETRIEVE_BERT_RECORD AmdExecuteRetrieveBertRecord; ///< Execute Retrieve Boot Error Record
- AMD_EXECUTE_REGISTER_ERROR_SOURCE AmdExecuteRegisterErrorSource; ///< Execute Register Generic Hardware Error Source
-};
-
-#endif //_AMD_ISCP_DXE_PROTOCOL_H_
+/* $NoKeywords */ +/** + * @file + * + * AmdIscpDxeProtocol.h + * + * Contains Intra-SoC Communication DXE Protocol definitions. + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e version: $Revision: 337020 $ @e date: $Date: 2016-03-02 11:49:34 -0600 (Wed, 02 Mar 2016) $ + * + */ +/***************************************************************************** +* +* Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +* IMPLIED. +* +***************************************************************************/ + +#ifndef __AMD_ISCP_DXE_PROTOCOL__H_ +#define __AMD_ISCP_DXE_PROTOCOL__H_ + +/*---------------------------------------------------------------------------------------- + * M O D U L E S U S E D + *---------------------------------------------------------------------------------------- + */ +#include <Iscp.h> + + +/*---------------------------------------------------------------------------------------- + * G U I D D E F I N I T I O N + *---------------------------------------------------------------------------------------- + */ +#define AMD_ISCP_DXE_PROTOCOL_GUID {\ + 0x5c794c8, 0x6aef, 0x4450, 0x91, 0x78, 0xca, 0x70, 0x53, 0x75, 0xbd, 0x91 \ +} + +/*---------------------------------------------------------------------------------------- + * E X T E R N S + *---------------------------------------------------------------------------------------- + */ +extern EFI_GUID gAmdIscpDxeProtocolGuid; + +/*---------------------------------------------------------------------------------------- + * T Y P E D E F S A N D S T R U C T U R E S + *---------------------------------------------------------------------------------------- + */ +typedef struct _AMD_ISCP_DXE_PROTOCOL AMD_ISCP_DXE_PROTOCOL; + + /// HEST Notification type + typedef enum { + HEST_NOTIFY_POLLED = 0, ///< Polled + HEST_NOTIFY_GPIO = 7, ///< GPIO-Signal + } HEST_NOTIFY_TYPE; + + /// Trusted Firmware Generic Error Source structure + typedef struct { + UINT32 IscpVersion; ///< Version of BERT Region structure + UINT8 SourceGUID[16]; ///< ACPI v6.0: Table 18-331 [Section Type] + UINT64 ErrorStatusPhysAddr; ///< ACPI v6.0: Table 18-329 [Error Status Address] + UINT32 ErrorStatusLength; ///< ACPI v6.0: Table 18-329 [Error Status Block Length] + HEST_NOTIFY_TYPE NotificationType; ///< ACPI v6.0: Table 18-332 [Type] + } ISCP_TFW_GENERIC_ERROR_SOURCE; + +/// CPU Core Reset Prototype +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_CPU_CORE_RESET) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN OUT ISCP_CPU_RESET_INFO *CpuResetInfo ///< Pointer to CPU Reset Info structure + ); + +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_CPU_RETRIEVE_ID) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN OUT ISCP_CPU_RESET_INFO *CpuResetInfo ///< Pointer to CPU Reset Info structure + ); + +/// ISCP call to get MAC Address +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_GET_MAC_ADDRESS) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN OUT ISCP_MAC_INFO *MacInfo ///< Pointer to the Firmware MAC Address structure + ); + + +/// ISCP call to set MAC Address +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_SET_MAC_ADDRESS) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN OUT ISCP_MAC_INFO *MacInfo ///< Pointer to the Firmware MAC Address structure + ); + + +/// ISCP call to get Real-Time-Clock +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_GET_RTC) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN OUT ISCP_RTC_INFO *RtcInfo ///< Pointer to the Real-Time-Clock structure + ); + + +/// ISCP call to set Real-Time-Clock +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_SET_RTC) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN OUT ISCP_RTC_INFO *RtcInfo ///< Pointer to the Real-Time-Clock structure + ); + + +/// Update Firmware Volume Block into SPI from local memory +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_UPDATE_FV_BLOCK_DXE) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN CONST UINT32 Offset, ///< Offset to base of Firmware Volume Block + IN OUT UINT8 *NvData, ///< Pointer to data being stored in FV Block + IN CONST UINT32 NvSize ///< Size of data being stored FV Block + ); + + +/// Load Firmware Volume Block from SPI into local memory +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_LOAD_FV_BLOCK_DXE) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN CONST UINT32 Offset, ///< Offset to base of Firmware Volume Block + IN OUT UINT8 *NvData, ///< Pointer to data being stored in FV Block + IN CONST UINT32 NvSize ///< Size of data being retrieved from FV Block + ); + + +/// Erase Firmware Volume Block Prototype +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_ERASE_FV_BLOCK_DXE) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN CONST UINT32 Offset, ///< Offset to base of Firmware Volume Block + IN CONST UINT32 NvSize ///< Size of data being erased + ); + + +/// Update EEPROM Block from local memory prototype +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_UPDATE_EEPROM_BLOCK_DXE) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN CONST UINT32 Offset, ///< Offset to base of EEPROM Block + IN OUT UINT8 *Data, ///< Pointer to data being stored in EEPROM Block + IN CONST UINT32 Size ///< Size of data being stored EEPROM Block + ); + + +/// Load EEPROM Block into local memory prototype +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_LOAD_EEPROM_BLOCK_DXE) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN CONST UINT32 Offset, ///< Offset to base of EEPROM Block + IN OUT UINT8 *Data, ///< Pointer to data being stored in EEPROM Block + IN CONST UINT32 Size ///< Size of data being retrieved from EEPROM Block + ); + + +/// Erase EEPROM Block prototype +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_ERASE_EEPROM_BLOCK_DXE) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN CONST UINT32 Offset, ///< Offset to base of EEPROM Block + IN CONST UINT32 Size ///< Size of data being erased + ); + + +/// Issue ISCP Doorbell command +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_GET_BMC_IP_ADDRESS) ( + IN AMD_ISCP_DXE_PROTOCOL *This, + IN OUT ISCP_BMC_IP_ADDRESS_INFO *BmcIpAddressInfo + ); + +/// Issue ISCP command to retrieve SMBIOS info +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_SMBIOS_INFO) ( + IN AMD_ISCP_DXE_PROTOCOL *This, + IN OUT ISCP_SMBIOS_INFO *SmbiosInfo + ); + +/// Issue ISCP command to issue SoC shutdown command +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_SOC_SHUTDOWN) ( + IN AMD_ISCP_DXE_PROTOCOL *This + ); + +/// Issue ISCP command to issue SoC reset command +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_SOC_RESET) ( + IN AMD_ISCP_DXE_PROTOCOL *This + ); + +/// ISCP call to set Memory Set up Nodes +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_MEM_SETUP) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN OUT MEM_SETUP_VAR *SetupInfo ///< Pointer to the Firmware MAC Address structure + ); + +/// Issue Override Command +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_OVERRIDE_CMD) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN ISCP_OVERRIDE_CMD_INFO *OverrideCmdInfo ///< Pointer to the Overrride Command structure + ); + +/// Issue Sata1 get state +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_SATA1_GET) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN OUT ISCP_SATA1_RESET_INFO *Sata1ResetInfo ///< Pointer to the SATA1 reset structure + ); + +/// Issue Sata1 set state +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_SATA1_SET) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + IN ISCP_SATA1_RESET_INFO *Sata1ResetInfo ///< Pointer to the SATA1 reset structure + ); + +/// Issue BMC presence check +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_BMC_PRESENT) ( + IN AMD_ISCP_DXE_PROTOCOL *This, ///< Pointer to AMD_ISCP_DXE_PROTOCOL + OUT ISCP_BMC_PRESENCE_INFO *BmcPresenceInfo ///< Pointer to BMC presence structure + ); + +/// Register Boot Error Region +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_RETRIEVE_BERT_RECORD) ( + IN AMD_ISCP_DXE_PROTOCOL *This, + IN OUT ISCP_BERT_REGION_INFO *BertRegionInfo + ); + +/// Register generic hardware error soure +typedef +EFI_STATUS +(EFIAPI *AMD_EXECUTE_REGISTER_ERROR_SOURCE) ( + IN AMD_ISCP_DXE_PROTOCOL *This, + IN ISCP_TFW_GENERIC_ERROR_SOURCE *GenericErrorSource + ); + + +/*---------------------------------------------------------------------------------------- + * P R O T O C O L S T R U C T U R E + *---------------------------------------------------------------------------------------- + */ +/// ISCP DXE Protocol Structure +struct _AMD_ISCP_DXE_PROTOCOL { + AMD_EXECUTE_CPU_CORE_RESET AmdExecuteCpuCoreReset; ///< Execute CPU Core Reset + AMD_EXECUTE_CPU_RETRIEVE_ID AmdExecuteCpuRetrieveId; ///< Execute CPU Retrieve ID + AMD_EXECUTE_GET_MAC_ADDRESS AmdExecuteGetMacAddress; ///< Execute Get MAC Address + AMD_EXECUTE_SET_MAC_ADDRESS AmdExecuteSetMacAddress; ///< Execute Set MAC Address + AMD_EXECUTE_GET_RTC AmdExecuteGetRtc; ///< Execute Get Real-Time-Clock Time + AMD_EXECUTE_SET_RTC AmdExecuteSetRtc; ///< Execute Set Real-Time-Clock Time + AMD_EXECUTE_UPDATE_FV_BLOCK_DXE AmdExecuteUpdateFvBlockDxe; ///< Execute Update FV Block Data on the SPI device + AMD_EXECUTE_LOAD_FV_BLOCK_DXE AmdExecuteLoadFvBlockDxe; ///< Execute Load FV Block Data from the SPI device + AMD_EXECUTE_ERASE_FV_BLOCK_DXE AmdExecuteEraseFvBlockDxe; ///< Execute Erase FV Block Data on the SPI device + AMD_EXECUTE_UPDATE_EEPROM_BLOCK_DXE AmdExecuteUpdateEepromBlockDxe; ///< Execute Update EEPROM Data on the EEPROM device + AMD_EXECUTE_LOAD_EEPROM_BLOCK_DXE AmdExecuteLoadEepromBlockDxe; ///< Execute Load EEPROM Data on the EEPROM device + AMD_EXECUTE_ERASE_EEPROM_BLOCK_DXE AmdExecuteEraseEepromBlockDxe; ///< Execute Erase EEPROM Data on the EEPROM device + AMD_EXECUTE_GET_BMC_IP_ADDRESS AmdExecuteGetBmcIpAddress; ///< Execute Get BMC IP Address + AMD_EXECUTE_SMBIOS_INFO AmdExecuteSmbiosInfoDxe; ///< Execute SMBIOS info + AMD_EXECUTE_SOC_SHUTDOWN AmdExecuteSocShutdownDxe; ///< Execute SoC Shutdown + AMD_EXECUTE_SOC_RESET AmdExecuteSocResetDxe; ///< Execute SoC Reset + AMD_EXECUTE_MEM_SETUP AmdExecuteMemSetup; ///< Execute Set MAC Address + AMD_EXECUTE_OVERRIDE_CMD AmdExecuteOverrideCmd; ///< Execute Override Command + AMD_EXECUTE_SATA1_GET AmdExecuteSata1Get; ///< Execute Sata1 get state + AMD_EXECUTE_SATA1_SET AmdExecuteSata1Set; ///< Execute Sata1 set state + AMD_EXECUTE_BMC_PRESENT AmdExecuteBmcPresent; ///< Execute BMC presence check + AMD_EXECUTE_RETRIEVE_BERT_RECORD AmdExecuteRetrieveBertRecord; ///< Execute Retrieve Boot Error Record + AMD_EXECUTE_REGISTER_ERROR_SOURCE AmdExecuteRegisterErrorSource; ///< Execute Register Generic Hardware Error Source +}; + +#endif //_AMD_ISCP_DXE_PROTOCOL_H_ diff --git a/Silicon/AMD/Styx/AmdModulePkg/Include/Protocol/AmdRasApeiProtocol.h b/Silicon/AMD/Styx/AmdModulePkg/Include/Protocol/AmdRasApeiProtocol.h index 94f4f26..8a0346f 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Include/Protocol/AmdRasApeiProtocol.h +++ b/Silicon/AMD/Styx/AmdModulePkg/Include/Protocol/AmdRasApeiProtocol.h @@ -1,86 +1,86 @@ -/* $NoKeywords: $ */
-/**
- * @file
- *
- * AMD RAS APEI Protocol
- *
- * AMD Ras Interface Protocol GUID initialization
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: FDK
- * @e sub-project: UEFI
- * @e \$Revision: 281924 $ @e \$Date: 2014-01-02 13:57:19 -0600 (Thu, 02 Jan 2014) $
- */
-/*****************************************************************************
- *
- * Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
- *
- * This program and the accompanying materials are licensed and made available
- * under the terms and conditions of the BSD License which accompanies this
- * distribution. The full text of the license may be found at
- * http://opensource.org/licenses/bsd-license.php
- *
- * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
- * IMPLIED.
- *
- ***************************************************************************/
-
-#ifndef _AMD_RAS_APEI_PROTOCOL_H_
-#define _AMD_RAS_APEI_PROTOCOL_H_
-
-#include "AmdApei.h"
-
-//
-// GUID definition
-//
-#define AMD_RAS_APEI_PROTOCOL_GUID \
- { 0xe9dbcc60, 0x8f93, 0x47ed, 0x84, 0x78, 0x46, 0x78, 0xf1, 0x9f, 0x73, 0x4a }
-// {E9DBCC60-8F93-47ed-8478-4678F19F734A}
-
-extern EFI_GUID gAmdRasApeiProtocolGuid;
-
-// current PPI revision
-#define AMD_RAS_APEI_REV 0x01
-
-/*----------------------------------------------------------------------------------------
- * P R O T O T Y P E S O F L O C A L F U N C T I O N S
- *----------------------------------------------------------------------------------------
- */
-typedef struct _AMD_RAS_APEI_PROTOCOL AMD_RAS_APEI_PROTOCOL;
-
-/// APEI Interface data pointer
-typedef
-struct _AMD_APEI_INTERFACE {
- APEI_DRIVER_PRIVATE_DATA *ApeiPrivData;
-} AMD_APEI_INTERFACE;
-
-
-/// APEI add Boot error record
-typedef
-EFI_STATUS
-(EFIAPI *AMD_ADD_BOOT_ERROR_RECORD_ENTRY) (
- IN UINT8 *ErrorRecord,
- IN UINT32 RecordLen,
- IN UINT8 ErrorType,
- IN UINT8 SeverityType
-);
-
-/// APEI add HEST error source
-typedef
-EFI_STATUS
-(EFIAPI *ADD_HEST_ERROR_SOURCE_ENTRY) (
- IN UINT8 *pErrorRecord,
- IN UINT32 RecordLen
-);
-
-
-/// RAS APEI Protocol Structure
-typedef struct _AMD_RAS_APEI_PROTOCOL {
- AMD_APEI_INTERFACE *AmdApeiInterface; /// APEI Interface
- AMD_ADD_BOOT_ERROR_RECORD_ENTRY AddBootErrorRecordEntry; /// Boot error record to be added
- ADD_HEST_ERROR_SOURCE_ENTRY AddHestErrorSourceEntry; /// HEST error source to be added
-} AMD_RAS_APEI_PROTOCOL;
-
-
-#endif //_AMD_RAS_APEI_PROTOCOL_H_
+/* $NoKeywords: $ */ +/** + * @file + * + * AMD RAS APEI Protocol + * + * AMD Ras Interface Protocol GUID initialization + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: FDK + * @e sub-project: UEFI + * @e \$Revision: 281924 $ @e \$Date: 2014-01-02 13:57:19 -0600 (Thu, 02 Jan 2014) $ + */ +/***************************************************************************** + * + * Copyright 2013 - 2016 ADVANCED MICRO DEVICES, INC. All Rights Reserved. + * + * This program and the accompanying materials are licensed and made available + * under the terms and conditions of the BSD License which accompanies this + * distribution. The full text of the license may be found at + * http://opensource.org/licenses/bsd-license.php + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR + * IMPLIED. + * + ***************************************************************************/ + +#ifndef _AMD_RAS_APEI_PROTOCOL_H_ +#define _AMD_RAS_APEI_PROTOCOL_H_ + +#include "AmdApei.h" + +// +// GUID definition +// +#define AMD_RAS_APEI_PROTOCOL_GUID \ + { 0xe9dbcc60, 0x8f93, 0x47ed, 0x84, 0x78, 0x46, 0x78, 0xf1, 0x9f, 0x73, 0x4a } +// {E9DBCC60-8F93-47ed-8478-4678F19F734A} + +extern EFI_GUID gAmdRasApeiProtocolGuid; + +// current PPI revision +#define AMD_RAS_APEI_REV 0x01 + +/*---------------------------------------------------------------------------------------- + * P R O T O T Y P E S O F L O C A L F U N C T I O N S + *---------------------------------------------------------------------------------------- + */ +typedef struct _AMD_RAS_APEI_PROTOCOL AMD_RAS_APEI_PROTOCOL; + +/// APEI Interface data pointer +typedef +struct _AMD_APEI_INTERFACE { + APEI_DRIVER_PRIVATE_DATA *ApeiPrivData; +} AMD_APEI_INTERFACE; + + +/// APEI add Boot error record +typedef +EFI_STATUS +(EFIAPI *AMD_ADD_BOOT_ERROR_RECORD_ENTRY) ( + IN UINT8 *ErrorRecord, + IN UINT32 RecordLen, + IN UINT8 ErrorType, + IN UINT8 SeverityType +); + +/// APEI add HEST error source +typedef +EFI_STATUS +(EFIAPI *ADD_HEST_ERROR_SOURCE_ENTRY) ( + IN UINT8 *pErrorRecord, + IN UINT32 RecordLen +); + + +/// RAS APEI Protocol Structure +typedef struct _AMD_RAS_APEI_PROTOCOL { + AMD_APEI_INTERFACE *AmdApeiInterface; /// APEI Interface + AMD_ADD_BOOT_ERROR_RECORD_ENTRY AddBootErrorRecordEntry; /// Boot error record to be added + ADD_HEST_ERROR_SOURCE_ENTRY AddHestErrorSourceEntry; /// HEST error source to be added +} AMD_RAS_APEI_PROTOCOL; + + +#endif //_AMD_RAS_APEI_PROTOCOL_H_ diff --git a/Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpDxe.inf b/Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpDxe.inf index 4cb7bb2..555acbf 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpDxe.inf +++ b/Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpDxe.inf @@ -1,47 +1,47 @@ -# $NoKeywords */
-#
-# @file
-#
-# IscpDxe.inf
-#
-# AMD-specific DXE-Phase Intra-SoC Communication Protocol module information file.
-#
-# @xrefitem bom "File Content Label" "Release Content"
-# @e project: FDK
-# @e sub-project: UEFI
-# @e version: $Revision: 323117 $ @e date: $Date: 2015-07-22 15:39:01 -0500 (Wed, 22 Jul 2015) $
-#
-#
-#*****************************************************************************
-#
-# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#***************************************************************************/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = IscpDxe
- FILE_GUID = 2FC9C0DD-1CB9-44E1-874F-C63B751F34B3
- MODULE_TYPE = DXE_RUNTIME_DRIVER
- VERSION_STRING = 1.0
- ENTRY_POINT = IscpInitEntryPoint
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = AARCH64
-#
-#
-
-[Binaries.AARCH64]
- PE32|IscpDxe.efi|*
- DXE_DEPEX|IscpDxe.depex|*
-
+# $NoKeywords */ +# +# @file +# +# IscpDxe.inf +# +# AMD-specific DXE-Phase Intra-SoC Communication Protocol module information file. +# +# @xrefitem bom "File Content Label" "Release Content" +# @e project: FDK +# @e sub-project: UEFI +# @e version: $Revision: 323117 $ @e date: $Date: 2015-07-22 15:39:01 -0500 (Wed, 22 Jul 2015) $ +# +# +#***************************************************************************** +# +# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#***************************************************************************/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = IscpDxe + FILE_GUID = 2FC9C0DD-1CB9-44E1-874F-C63B751F34B3 + MODULE_TYPE = DXE_RUNTIME_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = IscpInitEntryPoint + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# +# + +[Binaries.AARCH64] + PE32|IscpDxe.efi|* + DXE_DEPEX|IscpDxe.depex|* + diff --git a/Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpPei.inf b/Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpPei.inf index 98fd81c..4f31aaa 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpPei.inf +++ b/Silicon/AMD/Styx/AmdModulePkg/Iscp/IscpPei.inf @@ -1,45 +1,45 @@ -#**
-# @file
-#
-# IscpPei.inf
-#
-# AMD-specific PEI-Phase Intra-SoC Communication Protocol module information file.
-#
-# @xrefitem bom "File Content Label" "Release Content"
-# @e project: FDK
-# @e sub-project: UEFI
-# @e version: $Revision: 321113 $ @e date: $Date: 2015-06-19 10:25:47 -0500 (Fri, 19 Jun 2015) $
-#
-#
-#*****************************************************************************
-#
-# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#***************************************************************************/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = IscpPei
- FILE_GUID = 4C4C6624-DDDA-4C49-B542-DAFF4CBF2F20
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- ENTRY_POINT = PeiInitIscp
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = AARCH64
-#
-#
-
-[Binaries.AARCH64]
- PE32|IscpPei.efi|*
- PEI_DEPEX|IscpPei.depex
+#** +# @file +# +# IscpPei.inf +# +# AMD-specific PEI-Phase Intra-SoC Communication Protocol module information file. +# +# @xrefitem bom "File Content Label" "Release Content" +# @e project: FDK +# @e sub-project: UEFI +# @e version: $Revision: 321113 $ @e date: $Date: 2015-06-19 10:25:47 -0500 (Fri, 19 Jun 2015) $ +# +# +#***************************************************************************** +# +# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#***************************************************************************/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = IscpPei + FILE_GUID = 4C4C6624-DDDA-4C49-B542-DAFF4CBF2F20 + MODULE_TYPE = PEIM + VERSION_STRING = 1.0 + ENTRY_POINT = PeiInitIscp + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = AARCH64 +# +# + +[Binaries.AARCH64] + PE32|IscpPei.efi|* + PEI_DEPEX|IscpPei.depex diff --git a/Silicon/AMD/Styx/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf b/Silicon/AMD/Styx/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf index 3a16cd1..218a7f5 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf +++ b/Silicon/AMD/Styx/AmdModulePkg/Library/AmdSataInitLib/AmdSataInitLib.inf @@ -1,49 +1,49 @@ -# $NoKeywords */
-#
-# @file
-#
-# AmdSataInitLib.inf
-#
-# AMD-specific SATA Library Initialization information file.
-#
-# @xrefitem bom "File Content Label" "Release Content"
-# @e project: FDK
-# @e sub-project: UEFI
-# @e version: $Revision: 294189 $ @e date: $Date: 2014-05-29 19:25:20 -0500 (Thu, 29 May 2014) $
-#
-#
-#*****************************************************************************
-#
-# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#***************************************************************************/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = AmdSataInit
- FILE_GUID = 15336efd-ab12-512E-cca1-2584695123a0
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = AmdSataInit
-
-[Binaries.AARCH64]
- LIB|AmdSataInit.lib|*
-
-[Packages]
- Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
-
-[FixedPcd]
- gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen1
- gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen2
- gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen3
- gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen1
- gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen2
- gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen3
+# $NoKeywords */ +# +# @file +# +# AmdSataInitLib.inf +# +# AMD-specific SATA Library Initialization information file. +# +# @xrefitem bom "File Content Label" "Release Content" +# @e project: FDK +# @e sub-project: UEFI +# @e version: $Revision: 294189 $ @e date: $Date: 2014-05-29 19:25:20 -0500 (Thu, 29 May 2014) $ +# +# +#***************************************************************************** +# +# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#***************************************************************************/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AmdSataInit + FILE_GUID = 15336efd-ab12-512E-cca1-2584695123a0 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = AmdSataInit + +[Binaries.AARCH64] + LIB|AmdSataInit.lib|* + +[Packages] + Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec + +[FixedPcd] + gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen1 + gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen2 + gAmdModulePkgTokenSpaceGuid.PcdSATA0AlignPGen3 + gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen1 + gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen2 + gAmdModulePkgTokenSpaceGuid.PcdSATA1AlignPGen3 diff --git a/Silicon/AMD/Styx/AmdModulePkg/SnpDxe/SnpDxePort0.inf b/Silicon/AMD/Styx/AmdModulePkg/SnpDxe/SnpDxePort0.inf index d2bb67e..c042105 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/SnpDxe/SnpDxePort0.inf +++ b/Silicon/AMD/Styx/AmdModulePkg/SnpDxe/SnpDxePort0.inf @@ -1,48 +1,48 @@ -# $NoKeywords */
-#
-# @file
-#
-# SnpDxePort0.inf
-#
-# Ethernet port 0 driver module information file.
-#
-# @xrefitem bom "File Content Label" "Release Content"
-# @e project: FDK
-# @e sub-project: UEFI
-# @e version: $Revision: 294189 $ @e date: $Date: 2014-05-29 17:25:20 -0700 (Thu, 29 May 2014) $
-#
-#
-#*****************************************************************************
-#
-# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#***************************************************************************/
-
-[Defines]
- INF_VERSION = 0x00010005
- VERSION_STRING = 1.0
- BASE_NAME = SnpDxePort0
- MODULE_TYPE = UEFI_DRIVER
- FILE_GUID = 25ac458a-cf60-476e-861a-211c757657a6
- ENTRY_POINT = UefiMain
-
-[Binaries.AARCH64]
- PE32|SnpDxePort0.efi
- DEPEX|SnpDxePort0.depex
-
-[Packages]
- Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
-
-[PatchPcd]
- gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp
- gAmdModulePkgTokenSpaceGuid.PcdXgbeRev
- gAmdModulePkgTokenSpaceGuid.PcdEthMacA
- gAmdModulePkgTokenSpaceGuid.PcdEthMacB
+# $NoKeywords */ +# +# @file +# +# SnpDxePort0.inf +# +# Ethernet port 0 driver module information file. +# +# @xrefitem bom "File Content Label" "Release Content" +# @e project: FDK +# @e sub-project: UEFI +# @e version: $Revision: 294189 $ @e date: $Date: 2014-05-29 17:25:20 -0700 (Thu, 29 May 2014) $ +# +# +#***************************************************************************** +# +# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#***************************************************************************/ + +[Defines] + INF_VERSION = 0x00010005 + VERSION_STRING = 1.0 + BASE_NAME = SnpDxePort0 + MODULE_TYPE = UEFI_DRIVER + FILE_GUID = 25ac458a-cf60-476e-861a-211c757657a6 + ENTRY_POINT = UefiMain + +[Binaries.AARCH64] + PE32|SnpDxePort0.efi + DEPEX|SnpDxePort0.depex + +[Packages] + Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec + +[PatchPcd] + gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp + gAmdModulePkgTokenSpaceGuid.PcdXgbeRev + gAmdModulePkgTokenSpaceGuid.PcdEthMacA + gAmdModulePkgTokenSpaceGuid.PcdEthMacB diff --git a/Silicon/AMD/Styx/AmdModulePkg/SnpDxe/SnpDxePort1.inf b/Silicon/AMD/Styx/AmdModulePkg/SnpDxe/SnpDxePort1.inf index c980569..e0f9001 100644 --- a/Silicon/AMD/Styx/AmdModulePkg/SnpDxe/SnpDxePort1.inf +++ b/Silicon/AMD/Styx/AmdModulePkg/SnpDxe/SnpDxePort1.inf @@ -1,48 +1,48 @@ -# $NoKeywords */
-#
-# @file
-#
-# SnpDxePort1.inf
-#
-# Ethernet port 1 driver module information file.
-#
-# @xrefitem bom "File Content Label" "Release Content"
-# @e project: FDK
-# @e sub-project: UEFI
-# @e version: $Revision: 294189 $ @e date: $Date: 2014-05-29 17:25:20 -0700 (Thu, 29 May 2014) $
-#
-#
-#*****************************************************************************
-#
-# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#***************************************************************************/
-
-[Defines]
- INF_VERSION = 0x00010005
- VERSION_STRING = 1.0
- BASE_NAME = SnpDxePort1
- MODULE_TYPE = UEFI_DRIVER
- FILE_GUID = 92ea3d06-5990-4436-b4e1-07a02f4a98a9
- ENTRY_POINT = UefiMain
-
-[Binaries.AARCH64]
- PE32|SnpDxePort1.efi
- DEPEX|SnpDxePort1.depex
-
-[Packages]
- Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec
-
-[PatchPcd]
- gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp
- gAmdModulePkgTokenSpaceGuid.PcdXgbeRev
- gAmdModulePkgTokenSpaceGuid.PcdEthMacA
- gAmdModulePkgTokenSpaceGuid.PcdEthMacB
+# $NoKeywords */ +# +# @file +# +# SnpDxePort1.inf +# +# Ethernet port 1 driver module information file. +# +# @xrefitem bom "File Content Label" "Release Content" +# @e project: FDK +# @e sub-project: UEFI +# @e version: $Revision: 294189 $ @e date: $Date: 2014-05-29 17:25:20 -0700 (Thu, 29 May 2014) $ +# +# +#***************************************************************************** +# +# Copyright (c) 2015 - 2016, AMD Inc. All rights reserved.<BR> +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#***************************************************************************/ + +[Defines] + INF_VERSION = 0x00010005 + VERSION_STRING = 1.0 + BASE_NAME = SnpDxePort1 + MODULE_TYPE = UEFI_DRIVER + FILE_GUID = 92ea3d06-5990-4436-b4e1-07a02f4a98a9 + ENTRY_POINT = UefiMain + +[Binaries.AARCH64] + PE32|SnpDxePort1.efi + DEPEX|SnpDxePort1.depex + +[Packages] + Silicon/AMD/Styx/AmdModulePkg/AmdModulePkg.dec + +[PatchPcd] + gAmdModulePkgTokenSpaceGuid.PcdXgbeUseMacFromIscp + gAmdModulePkgTokenSpaceGuid.PcdXgbeRev + gAmdModulePkgTokenSpaceGuid.PcdEthMacA + gAmdModulePkgTokenSpaceGuid.PcdEthMacB diff --git a/Silicon/AMD/Styx/License.txt b/Silicon/AMD/Styx/License.txt index ff85835..25655fa 100644 --- a/Silicon/AMD/Styx/License.txt +++ b/Silicon/AMD/Styx/License.txt @@ -1,25 +1,25 @@ -Copyright (c) 2013 - 2016, AMD Inc. All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-
-1. Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in
- the documentation and/or other materials provided with the
- distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
+Copyright (c) 2013 - 2016, AMD Inc. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +POSSIBILITY OF SUCH DAMAGE. |