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-rw-r--r--AlderLakeFspBinPkg/IoT/AlderLakePS/Fsp.bsf34
-rw-r--r--AlderLakeFspBinPkg/IoT/AlderLakePS/Fsp.fdbin1302528 -> 1302528 bytes
-rw-r--r--AlderLakeFspBinPkg/IoT/AlderLakePS/Include/FspmUpd.h76
-rw-r--r--AlderLakeFspBinPkg/IoT/AlderLakePS/Include/FspsUpd.h14
4 files changed, 72 insertions, 52 deletions
diff --git a/AlderLakeFspBinPkg/IoT/AlderLakePS/Fsp.bsf b/AlderLakeFspBinPkg/IoT/AlderLakePS/Fsp.bsf
index caf8182..f2fce30 100644
--- a/AlderLakeFspBinPkg/IoT/AlderLakePS/Fsp.bsf
+++ b/AlderLakeFspBinPkg/IoT/AlderLakePS/Fsp.bsf
@@ -28,8 +28,8 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x02
Skip 87 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartDebugEnable 1 bytes $_DEFAULT_ = 0x00
- $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x02
- $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode 1 bytes $_DEFAULT_ = 0x02
+ $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartNumber 1 bytes $_DEFAULT_ = 0x00
+ $gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartMode 1 bytes $_DEFAULT_ = 0x01
Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_PcdSerialIoUartBaudRate 4 bytes $_DEFAULT_ = 115200
$gPlatformFspPkgTokenSpaceGuid_PcdPciExpressBaseAddress 8 bytes $_DEFAULT_ = 0xC0000000
@@ -157,7 +157,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_UserBd 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_DisableMrcRetrainingOnRtcPowerLoss 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_DdrFreqLimit 2 bytes $_DEFAULT_ = 0
- $gPlatformFspPkgTokenSpaceGuid_SaGv 1 bytes $_DEFAULT_ = 0x00
+ $gPlatformFspPkgTokenSpaceGuid_SaGv 1 bytes $_DEFAULT_ = 0x05
$gPlatformFspPkgTokenSpaceGuid_MemTestOnWarmBoot 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_DdrSpeedControl 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_RMT 1 bytes $_DEFAULT_ = 0x00
@@ -226,7 +226,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_PcieMultipleSegmentEnabled 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_SaIpuEnable 1 bytes $_DEFAULT_ = 0x1
$gPlatformFspPkgTokenSpaceGuid_IpuLaneUsed 8 bytes $_DEFAULT_ = 0x04, 0x01, 0x02, 0x04, 0x04, 0x04, 0x00, 0x00
- $gPlatformFspPkgTokenSpaceGuid_CsiSpeed 8 bytes $_DEFAULT_ = 0x2, 0x2, 0x2, 0x2, 0x2, 0x2, 0x0, 0x0
+ $gPlatformFspPkgTokenSpaceGuid_CsiSpeed 8 bytes $_DEFAULT_ = 0x2, 0x1, 0x2, 0x2, 0x2, 0x2, 0x0, 0x0
$gPlatformFspPkgTokenSpaceGuid_ImguClkOutEn 6 bytes $_DEFAULT_ = 0x1, 0x1, 0x1, 0x1, 0x0, 0x0
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpEnableMask 4 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLinkDownGpios 1 bytes $_DEFAULT_ = 0x0
@@ -485,7 +485,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_PchHdaIDispCodecDisconnect 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_CnviDdrRfim 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_PcdDebugInterfaceFlags 1 bytes $_DEFAULT_ = 0x32
- $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber 1 bytes $_DEFAULT_ = 0x2
+ $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugControllerNumber 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugAutoFlow 1 bytes $_DEFAULT_ = 0x0
Skip 3 bytes
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugBaudRate 4 bytes $_DEFAULT_ = 115200
@@ -712,7 +712,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_CpuPcie3Rtd3Gpio 96 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_Avx2VoltageScaleFactor 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_Avx512VoltageScaleFactor 1 bytes $_DEFAULT_ = 0x00
- $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode 1 bytes $_DEFAULT_ = 0x02
+ $gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode 1 bytes $_DEFAULT_ = 0x01
Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugRxPinMux 4 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugTxPinMux 4 bytes $_DEFAULT_ = 0x0
@@ -759,6 +759,8 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_EccErrInjAddress 8 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_EccErrInjMask 8 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_EccErrInjCount 4 bytes $_DEFAULT_ = 0xF
+ $gPlatformFspPkgTokenSpaceGuid_EccErrInjMcSelect 1 bytes $_DEFAULT_ = 0x1
+ Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_FreqLimitMixedConfig 2 bytes $_DEFAULT_ = 0x0000
$gPlatformFspPkgTokenSpaceGuid_FirstDimmBitMask 1 bytes $_DEFAULT_ = 0x0A
$gPlatformFspPkgTokenSpaceGuid_SagvSwitchFactorIA 1 bytes $_DEFAULT_ = 0x1E
@@ -849,7 +851,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartCtsPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartRxPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartTxPinMuxPolicy 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
- $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber 1 bytes $_DEFAULT_ = 0x02
+ $gPlatformFspPkgTokenSpaceGuid_SerialIoDebugUartNumber 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDbg2 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoI2cMode 8 bytes $_DEFAULT_ = 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
$gPlatformFspPkgTokenSpaceGuid_PchSerialIoI2cSdaPinMux 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
@@ -975,10 +977,12 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_GnaEnable 1 bytes $_DEFAULT_ = 0x1
$gPlatformFspPkgTokenSpaceGuid_IomTypeCPortPadCfg 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x06,0x11,0x00,0x04,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_CpuUsb3OverCurrentPin 8 bytes $_DEFAULT_ = 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF
+ $gPlatformFspPkgTokenSpaceGuid_EnTcssUsbOcCurrentCrb 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_D3ColdEnable 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_ITbtPcieTunnelingForUsb4 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_SkipFspGop 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_TcCstateLimit 1 bytes $_DEFAULT_ = 0x0A
+ Skip 3 bytes
$gPlatformFspPkgTokenSpaceGuid_VbtSize 4 bytes $_DEFAULT_ = 0x00000000
$gPlatformFspPkgTokenSpaceGuid_LidStatus 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_IomStayInTCColdSeconds 1 bytes $_DEFAULT_ = 0x32
@@ -1286,7 +1290,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_CpuRootportUsedForHybridStorage 1 bytes $_DEFAULT_ = 0xFF
$gPlatformFspPkgTokenSpaceGuid_PchRootportUsedForCpuAttach 1 bytes $_DEFAULT_ = 0xFF
$gPlatformFspPkgTokenSpaceGuid_PchAcpiL6dPmeHandling 1 bytes $_DEFAULT_ = 0x0
- Skip 1 bytes
+ Skip 5 bytes
$gPlatformFspPkgTokenSpaceGuid_BgpdtHash 32 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_BiosGuardAttr 4 bytes $_DEFAULT_ = 0xFFFFFFFF
Skip 4 bytes
@@ -1522,7 +1526,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_PchPmDisableEnergyReport 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_SataTestMode 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PchXhciOcLock 1 bytes $_DEFAULT_ = 0x01
- $gPlatformFspPkgTokenSpaceGuid_PmcLpmS0ixSubStateEnableMask 1 bytes $_DEFAULT_ = 0x3
+ $gPlatformFspPkgTokenSpaceGuid_PmcLpmS0ixSubStateEnableMask 1 bytes $_DEFAULT_ = 0x9
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLtrMaxSnoopLatency 8 bytes $_DEFAULT_ = 0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpLtrMaxNoSnoopLatency 8 bytes $_DEFAULT_ = 0x0F,0x10,0x0F,0x10,0x0F,0x10,0x0F,0x10
$gPlatformFspPkgTokenSpaceGuid_CpuPcieRpSnoopLatencyOverrideMode 4 bytes $_DEFAULT_ = 0x02, 0x02, 0x02, 0x02
@@ -1591,6 +1595,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_L2QosEnumerationEn 1 bytes $_DEFAULT_ = 0x0
Skip 3 bytes
$gPlatformFspPkgTokenSpaceGuid_MemorySize 4 bytes $_DEFAULT_ = 0x00
+ $gPlatformFspPkgTokenSpaceGuid_CpuPcieFixGen1Trn 4 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00
EndStruct
@@ -2370,6 +2375,12 @@ List &gPlatformFspPkgTokenSpaceGuid_PprRunOnce
Selection 1 , "Enable"
EndList
+List &gPlatformFspPkgTokenSpaceGuid_EccErrInjMcSelect
+ Selection 0 , "MC0 Only"
+ Selection 1 , "MC1 Only"
+ Selection 2 , "Both MC0 and MC1"
+EndList
+
List &gPlatformFspPkgTokenSpaceGuid_Lp5BankMode
Selection 0 , "Auto"
Selection 1 , "8 Bank Mode"
@@ -3616,6 +3627,8 @@ Page "Memory Reference Code"
EditNum $gPlatformFspPkgTokenSpaceGuid_EccErrInjCount, "EccErrInjCount", HEX,
Help "Number of transactions between ECC error injection"
"Valid range: 0x0 ~ 0xFFFFFFFF"
+ Combo $gPlatformFspPkgTokenSpaceGuid_EccErrInjMcSelect, "EccErrInjMcSelect", &gPlatformFspPkgTokenSpaceGuid_EccErrInjMcSelect,
+ Help "Select which Memory Controller to inject ECC errors. 0=MC0 Only, 1=MC1 Only, 2=Both"
EditNum $gPlatformFspPkgTokenSpaceGuid_FreqLimitMixedConfig, "Frequency Limit for 2DPC Mixed or non-POR Config", DEC,
Help "Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto (default), otherwise a frequency in MT/s"
"Valid range: 0 ~ 10000"
@@ -4795,6 +4808,9 @@ Page "System Agent (Post-Mem)"
EditNum $gPlatformFspPkgTokenSpaceGuid_MemorySize, "MemorySize", HEX,
Help "MemorySize value"
"Valid range: 0x00 ~ 0xFFFFFFFF"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_CpuPcieFixGen1Trn, "CpuPcieFixGen1Trn", HEX,
+ Help "Per CPU PCIe RP (byte index = RpIndex). 0=Disable (default), 1=Apply Dekel/XL710 Gen1 training fix (clear R_PCIE_ACGR3S2 BIT4 then 25ms delay)."
+ "Valid range: 0x00 ~ 0xFF"
EndPage
Page "PCH (Pre-Mem)"
diff --git a/AlderLakeFspBinPkg/IoT/AlderLakePS/Fsp.fd b/AlderLakeFspBinPkg/IoT/AlderLakePS/Fsp.fd
index 8ba3a8e..9ee2480 100644
--- a/AlderLakeFspBinPkg/IoT/AlderLakePS/Fsp.fd
+++ b/AlderLakeFspBinPkg/IoT/AlderLakePS/Fsp.fd
Binary files differ
diff --git a/AlderLakeFspBinPkg/IoT/AlderLakePS/Include/FspmUpd.h b/AlderLakeFspBinPkg/IoT/AlderLakePS/Include/FspmUpd.h
index 2113272..8ad8780 100644
--- a/AlderLakeFspBinPkg/IoT/AlderLakePS/Include/FspmUpd.h
+++ b/AlderLakeFspBinPkg/IoT/AlderLakePS/Include/FspmUpd.h
@@ -4021,191 +4021,197 @@ typedef struct {
**/
UINT32 EccErrInjCount;
-/** Offset 0x0B34 - Frequency Limit for 2DPC Mixed or non-POR Config
+/** Offset 0x0B34 - EccErrInjMcSelect
+ Select which Memory Controller to inject ECC errors. 0=MC0 Only, 1=MC1 Only, 2=Both
+ 0:MC0 Only, 1:MC1 Only, 2:Both MC0 and MC1
+**/
+ UINT8 EccErrInjMcSelect;
+
+/** Offset 0x0B35
+**/
+ UINT8 UnusedUpdSpace5;
+
+/** Offset 0x0B36 - Frequency Limit for 2DPC Mixed or non-POR Config
Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto (default), otherwise a
frequency in MT/s
**/
UINT16 FreqLimitMixedConfig;
-/** Offset 0x0B36 - First Dimm BitMask
+/** Offset 0x0B38 - First Dimm BitMask
Defines which DIMM should be populated first on a 2DPC board. Bit0: MC0 DIMM0, Bit1:
MC0 DIMM1, Bit2: MC1 DIMM0, Bit3: MC1 DIMM1. For each MC, the first DIMM to be
populated should be set to '1'
**/
UINT8 FirstDimmBitMask;
-/** Offset 0x0B37 - SAGV Switch Factor IA DDR BW
+/** Offset 0x0B39 - SAGV Switch Factor IA DDR BW
SAGV Switch Factor IA DDR BW: IA DDR load percentage when system switch to high
SAGV point from 1 to 50%.
**/
UINT8 SagvSwitchFactorIA;
-/** Offset 0x0B38 - SAGV Switch Factor GT DDR BW
+/** Offset 0x0B3A - SAGV Switch Factor GT DDR BW
SAGV Switch Factor GT DDR BW: GT DDR load percentage when system switch to high
SAGV point from 1 to 50%.
**/
UINT8 SagvSwitchFactorGT;
-/** Offset 0x0B39 - SAGV Switch Factor IO DDR BW
+/** Offset 0x0B3B - SAGV Switch Factor IO DDR BW
SAGV Switch Factor IO DDR BW: IO DDR load percentage when system switch to high
SAGV point from 1 to 50%.
**/
UINT8 SagvSwitchFactorIO;
-/** Offset 0x0B3A - SAGV Switch Factor IA and GT Stall
+/** Offset 0x0B3C - SAGV Switch Factor IA and GT Stall
SAGV Switch Factor IA and GT Stall: IA and GT percentage when system switch to high
SAGV point from 1 to 50%.
**/
UINT8 SagvSwitchFactorStall;
-/** Offset 0x0B3B - Threshold For Switch Down
+/** Offset 0x0B3D - Threshold For Switch Down
SAGV heuristics down control: Duration in ms of low activity after which SAGV will
switch down, from 1 to 50ms.
**/
UINT8 SagvHeuristicsDownControl;
-/** Offset 0x0B3C - Threshold For Switch Up
+/** Offset 0x0B3E - Threshold For Switch Up
SAGV heuristics up control: Duration in ms of low activity after which SAGV will
switch up, from 1 to 50ms.
**/
UINT8 SagvHeuristicsUpControl;
-/** Offset 0x0B3D
+/** Offset 0x0B3F
**/
UINT8 Rsvd31;
-/** Offset 0x0B3E - Frequency Limit for Mixed 2DPC DDR5 1 Rank 8GB and 8GB
+/** Offset 0x0B40 - Frequency Limit for Mixed 2DPC DDR5 1 Rank 8GB and 8GB
Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency
in MT/s, default is 2000
**/
UINT16 FreqLimitMixedConfig_1R1R_8GB;
-/** Offset 0x0B40 - Frequency Limit for Mixed 2DPC DDR5 1 Rank 16GB and 16GB
+/** Offset 0x0B42 - Frequency Limit for Mixed 2DPC DDR5 1 Rank 16GB and 16GB
Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency
in MT/s, default is 2000
**/
UINT16 FreqLimitMixedConfig_1R1R_16GB;
-/** Offset 0x0B42 - Frequency Limit for Mixed 2DPC DDR5 1 Rank 8GB and 16GB
+/** Offset 0x0B44 - Frequency Limit for Mixed 2DPC DDR5 1 Rank 8GB and 16GB
Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency
in MT/s, default is 2000
**/
UINT16 FreqLimitMixedConfig_1R1R_8GB_16GB;
-/** Offset 0x0B44 - Frequency Limit for Mixed 2DPC DDR5 2 Rank
+/** Offset 0x0B46 - Frequency Limit for Mixed 2DPC DDR5 2 Rank
Frequency Limit for 2DPC Mixed or non-POR Config. 0: Auto, otherwise a frequency
in MT/s, default is 2000
**/
UINT16 FreqLimitMixedConfig_2R2R;
-/** Offset 0x0B46 - DMI Hw Eq Gen3 CoeffList Cm
+/** Offset 0x0B48 - DMI Hw Eq Gen3 CoeffList Cm
PCH_DMI_EQ_PARAM. Coefficient C-1.
**/
UINT8 PchDmiHwEqGen3CoeffListCm[8];
-/** Offset 0x0B4E - DMI Hw Eq Gen3 CoeffList Cp
+/** Offset 0x0B50 - DMI Hw Eq Gen3 CoeffList Cp
PCH_DMI_EQ_PARAM. Coefficient C+1.
**/
UINT8 PchDmiHwEqGen3CoeffListCp[8];
-/** Offset 0x0B56 - LCT Command eyewidth
+/** Offset 0x0B58 - LCT Command eyewidth
LCT Command eyewidth. 0: Auto, otherwise eyewidth , default is 96
**/
UINT16 LctCmdEyeWidth;
-/** Offset 0x0B58 - For LPDDR Only: Throttler CKEMin Timer
+/** Offset 0x0B5A - For LPDDR Only: Throttler CKEMin Timer
For LPDDR Only: Timer value for CKEMin, range[255;0]. Reqd min of SC_ROUND_T + BYTE_LENGTH
(4). Dfault is 0x00
**/
UINT8 ThrtCkeMinTmrLpddr;
-/** Offset 0x0B59 - First ECC Dimm BitMask
+/** Offset 0x0B5B - First ECC Dimm BitMask
Defines which ECC DIMM should be populated first on a 2DPC board. Bit0: MC0 DIMM0,
Bit1: MC0 DIMM1, Bit2: MC1 DIMM0, Bit3: MC1 DIMM1. For each MC, the first DIMM
to be populated should be set to '1'
**/
UINT8 FirstDimmBitMaskEcc;
-/** Offset 0x0B5A - LP5 Bank Mode
+/** Offset 0x0B5C - LP5 Bank Mode
LP5 Bank Mode. 0: Auto, 1: 8 Bank Mode, 2: 16 Bank Mode, 3: BG Mode, default is 0
0:Auto, 1:8 Bank Mode, 2:16 Bank Mode, 3:BG Mode
**/
UINT8 Lp5BankMode;
-/** Offset 0x0B5B - Write DS Training
+/** Offset 0x0B5D - Write DS Training
Enable/Disable Write DS Training
$EN_DIS
**/
UINT8 WRDS;
-/** Offset 0x0B5C - SAM Overlaoding
+/** Offset 0x0B5E - SAM Overlaoding
Enable: copy the sagv frequency point. Disable: not copy.
$EN_DIS
**/
UINT8 OverloadSAM;
-/** Offset 0x0B5D - Time Measure
+/** Offset 0x0B5F - Time Measure
Time Measure: 0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 MrcTimeMeasure;
-/** Offset 0x0B5E - Dfe Gain
+/** Offset 0x0B60 - Dfe Gain
Dfe Gain. 0:0 default value, 1: 1, 2: 2, 3: 3, 9: -1, 10: -2, 11: -3
0:0, 1:1, 2:2, 3:3, 9:-1, 10:-2, 11:-3
**/
UINT8 DfeGain;
-/** Offset 0x0B5F - CsPiStartHighinEct
+/** Offset 0x0B61 - CsPiStartHighinEct
Cs Pi Start with High value in Ect: 0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 CsPiStartHighinEct;
-/** Offset 0x0B60 - Use user provided power weights, and channel power floor values
+/** Offset 0x0B62 - Use user provided power weights, and channel power floor values
Enables/Disable Use user provided power weights and channel power floor values
$EN_DIS
**/
UINT8 UserPowerWeightsEn;
-/** Offset 0x0B61 - DisableFGRAndPBRWA
+/** Offset 0x0B63 - DisableFGRAndPBRWA
Disable FGR And PBR WA: 0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DisableFGRAndPBRWA;
-/** Offset 0x0B62 - McParity
+/** Offset 0x0B64 - McParity
CMI/MC Parity Control: 1(Default)=Enable
$EN_DIS
**/
UINT8 McParity;
-/** Offset 0x0B63 - IbeccParity
+/** Offset 0x0B65 - IbeccParity
In-Band ECC Parity Control: 1(Default)=Enable
$EN_DIS
**/
UINT8 IbeccParity;
-/** Offset 0x0B64 - LowerBasicMemTestSize
+/** Offset 0x0B66 - LowerBasicMemTestSize
Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 LowerBasicMemTestSize;
-/** Offset 0x0B65 - DisableSagvReorder
+/** Offset 0x0B67 - DisableSagvReorder
Disable Sagv reorder on warm boot: 0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DisableSagvReorder;
-/** Offset 0x0B66
+/** Offset 0x0B68
**/
UINT8 Rsvd32[4];
-/** Offset 0x0B6A
-**/
- UINT8 UnusedUpdSpace5[2];
-
/** Offset 0x0B6C
**/
UINT8 ReservedFspmUpd2[4];
diff --git a/AlderLakeFspBinPkg/IoT/AlderLakePS/Include/FspsUpd.h b/AlderLakeFspBinPkg/IoT/AlderLakePS/Include/FspsUpd.h
index 1e17d48..0407e70 100644
--- a/AlderLakeFspBinPkg/IoT/AlderLakePS/Include/FspsUpd.h
+++ b/AlderLakeFspBinPkg/IoT/AlderLakePS/Include/FspsUpd.h
@@ -4704,17 +4704,15 @@ typedef struct {
**/
UINT32 MemorySize;
-/** Offset 0x10F8
+/** Offset 0x10F8 - CpuPcieFixGen1Trn
+ Per CPU PCIe RP (byte index = RpIndex). 0=Disable (default), 1=Apply Dekel/XL710
+ Gen1 training fix (clear R_PCIE_ACGR3S2 BIT4 then 25ms delay).
**/
- UINT8 Rsvd40[2];
+ UINT8 CpuPcieFixGen1Trn[4];
-/** Offset 0x10FA
+/** Offset 0x10FC
**/
- UINT8 UnusedUpdSpace12[5];
-
-/** Offset 0x10FF
-**/
- UINT8 ReservedFspsUpd[1];
+ UINT8 ReservedFspsUpd[4];
} FSP_S_CONFIG;
/** Fsp S UPD Configuration
generated by cgit v1.2.3 (git 2.39.0) at 2026-11-10 15:47:58 +0300