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-rw-r--r--BirchStreamFspBinPkg/ap/Fsp.fdbin0 -> 5763072 bytes
-rw-r--r--BirchStreamFspBinPkg/ap/Include/CxlNodeHob.h102
-rw-r--r--BirchStreamFspBinPkg/ap/Include/FspAcpiHobs.h53
-rw-r--r--BirchStreamFspBinPkg/ap/Include/FspEdpcParam.h71
-rw-r--r--BirchStreamFspBinPkg/ap/Include/FspErrorInfoHob.h87
-rw-r--r--BirchStreamFspBinPkg/ap/Include/FspExtMemoryPprHob.h70
-rw-r--r--BirchStreamFspBinPkg/ap/Include/FspExtSystemMemoryMapHob.h161
-rw-r--r--BirchStreamFspBinPkg/ap/Include/FspGlobals.h61
-rw-r--r--BirchStreamFspBinPkg/ap/Include/FspUpd.h50
-rw-r--r--BirchStreamFspBinPkg/ap/Include/FspmUpd.h1866
-rw-r--r--BirchStreamFspBinPkg/ap/Include/FspsUpd.h249
-rw-r--r--BirchStreamFspBinPkg/ap/Include/FsptUpd.h101
-rw-r--r--BirchStreamFspBinPkg/ap/Include/IioPcieConfigUpd.h300
-rw-r--r--BirchStreamFspBinPkg/ap/Include/IioUniversalDataHob.h219
-rw-r--r--BirchStreamFspBinPkg/ap/Include/MemoryMapDataHob.h359
-rw-r--r--BirchStreamFspBinPkg/ap/Include/PrevBootErrSrcHob.h86
-rw-r--r--BirchStreamFspBinPkg/ap/Include/SystemInfoHob.h271
-rw-r--r--BirchStreamFspBinPkg/sp/Fsp.fdbin0 -> 5763072 bytes
-rw-r--r--BirchStreamFspBinPkg/sp/Include/CxlNodeHob.h102
-rw-r--r--BirchStreamFspBinPkg/sp/Include/FspAcpiHobs.h53
-rw-r--r--BirchStreamFspBinPkg/sp/Include/FspEdpcParam.h71
-rw-r--r--BirchStreamFspBinPkg/sp/Include/FspErrorInfoHob.h87
-rw-r--r--BirchStreamFspBinPkg/sp/Include/FspExtMemoryPprHob.h70
-rw-r--r--BirchStreamFspBinPkg/sp/Include/FspExtSystemMemoryMapHob.h161
-rw-r--r--BirchStreamFspBinPkg/sp/Include/FspGlobals.h61
-rw-r--r--BirchStreamFspBinPkg/sp/Include/FspUpd.h50
-rw-r--r--BirchStreamFspBinPkg/sp/Include/FspmUpd.h1866
-rw-r--r--BirchStreamFspBinPkg/sp/Include/FspsUpd.h249
-rw-r--r--BirchStreamFspBinPkg/sp/Include/FsptUpd.h101
-rw-r--r--BirchStreamFspBinPkg/sp/Include/IioPcieConfigUpd.h300
-rw-r--r--BirchStreamFspBinPkg/sp/Include/IioUniversalDataHob.h219
-rw-r--r--BirchStreamFspBinPkg/sp/Include/MemoryMapDataHob.h359
-rw-r--r--BirchStreamFspBinPkg/sp/Include/PrevBootErrSrcHob.h86
-rw-r--r--BirchStreamFspBinPkg/sp/Include/SystemInfoHob.h271
34 files changed, 8212 insertions, 0 deletions
diff --git a/BirchStreamFspBinPkg/ap/Fsp.fd b/BirchStreamFspBinPkg/ap/Fsp.fd
new file mode 100644
index 0000000..123c9d3
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Fsp.fd
Binary files differ
diff --git a/BirchStreamFspBinPkg/ap/Include/CxlNodeHob.h b/BirchStreamFspBinPkg/ap/Include/CxlNodeHob.h
new file mode 100644
index 0000000..5f6afc2
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/CxlNodeHob.h
@@ -0,0 +1,102 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _CXL_NODE_HOB_
+#define _CXL_NODE_HOB_
+
+#define CXL_NODE_HOB_GUID { 0xdd8ae009, 0xda5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } }
+
+#ifndef MAX_IIO_STACK
+#define MAX_IIO_STACK 16
+#endif
+
+#ifndef MAX_CXL_HDM_RANGES
+#define MAX_CXL_HDM_RANGES 0x2 // Maximum number of CXL HDM ranges per CXL end device.
+#endif
+
+#ifndef MAX_CXL_PER_SOCKET
+#define MAX_CXL_PER_SOCKET MAX_IIO_STACK
+#endif
+
+#define CXL_NODE_ATTR_MEM BIT0
+#define CXL_NODE_ATTR_PERSISTENT BIT1
+#define CXL_NODE_ATTR_MEM_HW_INIT BIT2
+#define CXL_NODE_ATTR_ACCELERATOR BIT3
+#define CXL_NODE_ATTR_HOT_PLUGGABLE BIT4
+
+typedef UINT32 CXL_NODE_ATTR;
+
+#pragma pack(1)
+
+//
+// CDAT DSEMTS EFI Memory Type and Attribute
+//
+typedef enum {
+ CxlEfiConventionalMemory = 0x0,
+ CxlEfiConventionalMemorySp = 0x1,
+ CxlEfiReservedMemoryType = 0x2,
+ MaxCxlEfiMemType
+} CXL_EFI_MEM_TYPE;
+
+typedef struct {
+ UINT32 RdLatency;
+ UINT32 WrLatency;
+ UINT32 RdBandwidth;
+ UINT32 WrBandwidth;
+} CXL_PERF_DATA;
+
+typedef struct {
+ UINT64 SerialNumber;
+ UINT16 VendorId;
+ CXL_NODE_ATTR Attr;
+ UINT32 Address;
+ UINT32 Size;
+ UINT8 Ways;
+ UINT8 SocketBitmap;
+ BOOLEAN AcpiSratSpMemFlag;
+ CXL_EFI_MEM_TYPE EfiMemType;
+ CXL_PERF_DATA InitiatorPerfData; // Performance data between device egress and initiator.
+ CXL_PERF_DATA TargetPerfData; // Performance data of entire target memory region.
+ CXL_PERF_DATA InitiatorTargetPerfData; // performance data between initiator and the device memory.
+} CXL_NODE_INFO;
+
+typedef struct {
+ UINT8 CxlNodeCount;
+ //
+ // CXL node info for UEFI memory map and ACPI tables construction
+ //
+ CXL_NODE_INFO CxlNodeInfo[MAX_IIO_STACK * MAX_CXL_HDM_RANGES];
+} CXL_NODE_SOCKET;
+
+#pragma pack()
+
+#endif //#ifndef _CXL_NODE_HOB_
diff --git a/BirchStreamFspBinPkg/ap/Include/FspAcpiHobs.h b/BirchStreamFspBinPkg/ap/Include/FspAcpiHobs.h
new file mode 100644
index 0000000..7150e5e
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/FspAcpiHobs.h
@@ -0,0 +1,53 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSP_ACPI_HOBS__
+#define __FSP_ACPI_HOBS__
+
+//Typecast HOB pointer to APEI table structure of ACPI version 6.2
+#define FSP_RAS_ACPI_HOB_GUID { 0x826785ee, 0xa8e0, 0x4d8f, { 0x82, 0x6f, 0x54, 0x29, 0x2c, 0xe7, 0x6f, 0xe6 } }
+
+//Typecast HOB pointer to ACPI CXL CEDT table structure
+#define FSP_CXL_CEDT_ACPI_HOB_GUID { 0x5CB7A12A, 0x8B2D, 0x485A, { 0xB7, 0x04, 0xC0, 0x52, 0x49, 0x56, 0x81, 0xE7 } }
+
+// Typecast HOB pointer to MEM_TRAINING_DATA_HOB_HEADER.
+// User with NDA clearance should refer to RC code for latest structure definition.
+#define FSP_MEM_TRAINING_DATA_HOB_GUID { 0x7e8b89e2, 0x8b84, 0x4cb3, { 0x86, 0x8f, 0x10, 0xb6, 0x78, 0x71, 0xa2, 0xc0 }}
+
+// Typecast HOB pointer to EWL_PRIVATE_DATA.
+// User with NDA clearance should refer to RC code for latest structure definition.
+#define FSP_EWL_ID_HOB_GUID { 0xd8e05800, 0x5e, 0x4462, { 0xaa, 0x3d, 0x9c, 0x6b, 0x47, 0x4, 0x92, 0xb } };
+
+//Typecast HOB pointer to RAS_ACPI_PARAM_HOB_DATA;
+#define RAS_ACPI_PARAM_HOB_GUID {0x594dfe5c, 0x7a87, 0x49dc, { 0x8f, 0x33, 0xea, 0x83, 0x4d, 0x6f, 0x18, 0x90 } }
+
+#endif // __FSP_ACPI_HOBS__
diff --git a/BirchStreamFspBinPkg/ap/Include/FspEdpcParam.h b/BirchStreamFspBinPkg/ap/Include/FspEdpcParam.h
new file mode 100644
index 0000000..ce694e9
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/FspEdpcParam.h
@@ -0,0 +1,71 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSP_EDPC_PARAM__
+#define __FSP_EDPC_PARAM__
+
+#pragma pack(1)
+typedef struct {
+ UINT8 Segment;
+ UINT8 Bus;
+ UINT8 Device;
+ UINT8 Function;
+} EDPC_DEV_INFO;
+
+typedef struct {
+ //
+ // There are three possible statuses of Valid infomation
+ // EPDC_INFO_VALID, EDPC_INFO_NOTIFIED, EDPC_INFO_CLEARED
+ //
+ UINT8 Valid;
+ EDPC_DEV_INFO EdpcTrigger;
+ EDPC_DEV_INFO EdpcRootPort;
+ UINT8 NotifyType;
+} EDPC_INFO;
+
+typedef struct {
+ UINT16 OsNativeAerSupport;
+ UINT16 Reserved;
+ UINT64 Reserved1[400];
+ EDPC_INFO EdpcInfo;
+ UINT64 EmcaL1DirAddr;
+ UINT8 EmcaEn;
+ UINT8 ElogEn;
+ UINT8 WheaEnabled;
+ UINT8 WheaSupportEn;
+ UINT64 ReadAckAddress;
+ UINT64 OobReadAckAddress;
+ UINT32 SoftwareSmi;
+} RAS_ACPI_PARAM;
+
+#pragma pack()
+#endif // __FSP_EDPC_PARAM__
diff --git a/BirchStreamFspBinPkg/ap/Include/FspErrorInfoHob.h b/BirchStreamFspBinPkg/ap/Include/FspErrorInfoHob.h
new file mode 100644
index 0000000..6b418c5
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/FspErrorInfoHob.h
@@ -0,0 +1,87 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _FSP_ERROR_INFO_HOB_H_
+#define _FSP_ERROR_INFO_HOB_H_
+
+///
+/// GUID value indicating the FSP error information.
+///
+#define FSP_ERROR_INFO_HOB_GUID { 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 } }
+
+#define FSP_ERROR_INFO_STATUS_CODE_TYPE (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED)
+///
+/// FSP Error Information Block.
+///
+#pragma pack(1)
+typedef struct {
+ ///
+ /// GUID HOB header.
+ ///
+ EFI_HOB_GUID_TYPE GuidHob;
+
+ ///
+ /// ReportStatusCode () type identifier.
+ ///
+ EFI_STATUS_CODE_TYPE Type;
+
+ ///
+ /// ReportStatusCode () value.
+ ///
+ EFI_STATUS_CODE_VALUE Value;
+
+ ///
+ /// ReportStatusCode () Instance number.
+ ///
+ UINT32 Instance;
+
+ ///
+ /// Optional GUID which may be used to identify
+ /// which internal component of the FSP was
+ /// executing at the time of the error.
+ ///
+ EFI_GUID CallerId;
+
+ ///
+ /// GUID identifying the nature of the fatal error.
+ ///
+ EFI_GUID ErrorType;
+
+ ///
+ /// EFI_STATUS code describing the error encountered.
+ ///
+ UINT32 Status;
+} FSP_ERROR_INFO_HOB;
+
+#pragma pack()
+
+#endif //_FSP_ERROR_INFO_H_
diff --git a/BirchStreamFspBinPkg/ap/Include/FspExtMemoryPprHob.h b/BirchStreamFspBinPkg/ap/Include/FspExtMemoryPprHob.h
new file mode 100644
index 0000000..97e3710
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/FspExtMemoryPprHob.h
@@ -0,0 +1,70 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _FSP_EXT_MEMORY_PPR_HOB_H_
+#define _FSP_EXT_MEMORY_PPR_HOB_H_
+
+#include "FspGlobals.h"
+
+#define FSP_EXT_MEMORY_PPR_HOB_GUID { 0x3956C6DA, 0x35B6, 0x4036, { 0x93, 0xE4, 0xB1, 0x51, 0x38, 0x60, 0x21, 0x1E } }
+
+#pragma pack(1)
+
+typedef struct FspExtPprAddr {
+ UINT8 Status;
+ UINT8 ErrorType;
+ UINT8 Socket;
+ UINT8 MemoryController;
+ UINT8 Channel;
+ UINT8 Dimm;
+ UINT8 Bank;
+ UINT32 Row;
+ UINT8 Rank;
+} FSP_EXT_PPR_ADDR;
+
+typedef struct FspExtPprDdrInfo {
+ UINT8 Count;
+ FSP_EXT_PPR_ADDR PprAddresses[FSP_MAX_PPR_ADDR_ENTRIES_DDR];
+} FSP_EXT_DDR_PPR_INFO;
+
+typedef struct FspExtMemoryPprData {
+ FSP_EXT_DDR_PPR_INFO DdrPprInfo;
+} FSP_EXT_MEMORY_PPR_DATA;
+
+typedef struct FspExtMemoryPprHob {
+ FSP_EXT_HEADER Header;
+ FSP_EXT_MEMORY_PPR_DATA Data;
+} FSP_EXT_MEMORY_PPR_HOB;
+
+#pragma pack()
+
+#endif // _FSP_EXT_MEMORY_PPR_HOB_H_
diff --git a/BirchStreamFspBinPkg/ap/Include/FspExtSystemMemoryMapHob.h b/BirchStreamFspBinPkg/ap/Include/FspExtSystemMemoryMapHob.h
new file mode 100644
index 0000000..066015e
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/FspExtSystemMemoryMapHob.h
@@ -0,0 +1,161 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
+#define _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
+
+#include "FspGlobals.h"
+
+#define FSP_EXT_SYSTEM_MEMORY_MAP_HOB_GUID { 0xDF310DE8, 0x579F, 0x419C, { 0xB6, 0xAB, 0x4D, 0x4B, 0xE7, 0xCA, 0xB0, 0x83 } }
+
+#pragma pack(1)
+
+typedef struct FspDimmDevice {
+ UINT8 Present;
+ BOOLEAN Enabled;
+ UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
+ UINT8 NumRanks; // Number of ranks on dimm
+ UINT8 NumPackageRanks; // Number of Package ranks on dimm
+ // For DDR5 NumRanks and NumPackageRanks same
+ // For MRDIMM NumRanks and NumPackageRanks may differ
+ UINT8 ActKeyByte2; // Actual module type reported by SPD
+ UINT16 DimmSize;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT8 SerialNumber[FSP_DIMM_MAX_SERIALNUMBER_LEN]; // Serial Number
+ UINT8 PartNumber[FSP_DIMM_MAX_PARTNUMBER_LEN]; // Part Number
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT16 FisVersion; // Firmware Interface Specification version
+ INT32 CommonTck;
+ UINT16 SpdRegVen; // Register Vendor ID in SPD
+ UINT8 DataWidth;
+} FSP_EXT_DIMM_DEVICE;
+
+typedef struct FspExtMemoryDimmDeviceInfo {
+ UINT8 Count;
+ FSP_EXT_DIMM_DEVICE Dimms[FSP_MAX_DIMM];
+} FSP_EXT_DIMM_DEVICE_INFO;
+
+typedef struct FspMemoryChannelDevice {
+ UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled
+ UINT8 Features; // Bit mask of features to enable or disable
+ UINT8 MaxDimm; // Number of DIMM
+ UINT8 ChFailed;
+ UINT8 NgnChFailed;
+ UINT8 Is4BitEccDimmPresent; // 4-bit Ecc dimm present indicator
+ UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+ UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+ FSP_EXT_DIMM_DEVICE_INFO DimmInfo;
+} FSP_EXT_MEMORY_CHANNEL_DEVICE;
+
+typedef struct FspMemoryController {
+ UINT8 ImcEnabled;
+ UINT32 MemSize;
+} FSP_EXT_MEMORY_CONTROLLER;
+
+typedef struct FspExtMemoryChannelDeviceInfo {
+ UINT8 Count;
+ FSP_EXT_MEMORY_CHANNEL_DEVICE Devices[FSP_MAX_CH];
+} FSP_EXT_MEMORY_CHANNEL_DEVICE_INFO;
+
+typedef struct FspExtMemoryControllerInfo {
+ UINT8 Count;
+ UINT8 NumChPerMC;
+ FSP_EXT_MEMORY_CONTROLLER MemControllers[FSP_MAX_IMC];
+} FSP_EXT_MEMORY_CONTROLLER_INFO;
+
+typedef struct FspMemoryMapSocket {
+ UINT8 SocketEnabled;
+ UINT32 IioStackBitmap;
+ UINT32 SktTotMemMapSPA; // Total memory mapped to SPA
+ FSP_EXT_MEMORY_CONTROLLER_INFO MemoryControllerInfo;
+ FSP_EXT_MEMORY_CHANNEL_DEVICE_INFO MemoryChannelDeviceInfo;
+} FSP_EXT_MEMORY_MAP_SOCKET;
+
+typedef struct FspExtMemMapSocketInfo {
+ UINT8 Count;
+ FSP_EXT_MEMORY_MAP_SOCKET Sockets[FSP_MAX_SOCKET];
+} FSP_EXT_MEMORY_MAP_SOCKET_INFO;
+
+typedef struct FspMemoryMapElement {
+ UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
+ UINT8 NodeId; // Node ID of the HA Owning the memory
+ UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
+ UINT8 ClusterId; // Logical cluster Id of SNC cluster - only 0 in UMA clustering and all2all
+ UINT32 BaseAddress; // Base Address of the element in 64MB chunks
+ UINT32 ElementSize; // Size of this memory element in 64MB chunks
+} FSP_EXT_MEMORY_MAP_ELEMENT;
+
+typedef struct FspExtMemMapElementInfo {
+ UINT8 Count;
+ FSP_EXT_MEMORY_MAP_ELEMENT Elements[FSP_MAX_MEMORY_MAP_ELEMENTS];
+} FSP_EXT_MEMORY_MAP_ELEMENT_INFO;
+
+typedef struct FspExtRasInfo {
+ UINT8 SystemRasType;
+ UINT8 RasModesEnabled; // RAS modes that are enabled
+ UINT16 ExRasModesEnabled; // Extended RAS modes that are enabled
+} FSP_EXT_RAS_INFO;
+
+typedef struct FspExtMemoryConfigurationInfo {
+ UINT32 LowMemBase; // Mem base in 64MB units for below 4GB mem.
+ UINT32 LowMemSize; // Mem size in 64MB units for below 4GB mem.
+ UINT32 HighMemBase; // Mem base in 64MB units for above 4GB mem.
+ UINT32 HighMemSize; // Mem size in 64MB units for above 4GB mem.
+ UINT32 MmiohBase; // MMIOH base in 64MB granularity
+ UINT32 MemSize; // Total physical memory size
+ UINT16 MemFreq;
+ UINT8 MemMode; // 0 - Independent, 1 - Lockstep
+ UINT8 VolMemMode; // 0 - 1LM, 1 - 2LM
+ UINT16 DramType;
+ UINT8 DdrVoltage; // Mem Frequency
+ UINT8 ErrorCorrectionType;
+} FSP_EXT_MEMORY_CONFIGURATION_INFO;
+
+typedef struct FspExtSystemMemoryMapData {
+ FSP_EXT_MEMORY_CONFIGURATION_INFO MemoryConfigurationInfo;
+ FSP_EXT_RAS_INFO RasInfo;
+ FSP_EXT_MEMORY_MAP_ELEMENT_INFO MemoryMapElementInfo;
+ FSP_EXT_MEMORY_MAP_SOCKET_INFO MemoryMapSocketInfo;
+} FSP_EXT_SYSTEM_MEMORY_MAP_DATA;
+
+typedef struct FspExtSystemMemoryMapDataHob{
+ FSP_EXT_HEADER Header;
+ FSP_EXT_SYSTEM_MEMORY_MAP_DATA Data;
+} FSP_EXT_SYSTEM_MEMORY_MAP_HOB;
+
+#pragma pack()
+
+#endif // _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
diff --git a/BirchStreamFspBinPkg/ap/Include/FspGlobals.h b/BirchStreamFspBinPkg/ap/Include/FspGlobals.h
new file mode 100644
index 0000000..c8df3ac
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/FspGlobals.h
@@ -0,0 +1,61 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _FSP_EXT_GLOBALS_
+#define _FSP_EXT_GLOBALS_
+
+#define FSP_MAX_SOCKET MAX_SOCKET
+#define FSP_MAX_IMC MAX_IMC
+#define FSP_MAX_MC_CH MAX_MC_CH
+#define FSP_MAX_DIMM MAX_DIMM
+#define FSP_DIMM_MAX_SERIALNUMBER_LEN NGN_MAX_SERIALNUMBER_STRLEN
+#define FSP_DIMM_MAX_PARTNUMBER_LEN NGN_MAX_PARTNUMBER_STRLEN
+#define FSP_MAX_CH ((FSP_MAX_IMC)*(FSP_MAX_MC_CH))
+#define FSP_MAX_MEMORY_MAP_ELEMENTS 150
+
+#define MEM_64MB_TO_BYTES(Size64M) ((UINT64)(Size64M) << 26)
+#define MEM_64MB_TO_KBYTES(Size64M) ((UINT64)(Size64M) << 16)
+#define MEM_64MB_TO_MBYTES(Size64M) ((UINT64)(Size64M) << 6)
+#define MEM_64MB_TO_GBYTES(Size64M) ((Size64M) >> 4)
+#define MEM_BYTES_TO_64MB(SizeB) ((SizeB) >> 26)
+#define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16)
+#define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6)
+
+#define FSP_MAX_PPR_ADDR_ENTRIES_DDR MAX_PPR_ADDR_ENTRIES_DDR
+
+typedef struct FspExtHeader {
+ UINT64 Magic;
+ UINT32 DataLength;
+ UINT32 CheckSum;
+} FSP_EXT_HEADER;
+
+#endif // _FSP_EXT_GLOBALS_
diff --git a/BirchStreamFspBinPkg/ap/Include/FspUpd.h b/BirchStreamFspBinPkg/ap/Include/FspUpd.h
new file mode 100644
index 0000000..cbee351
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/FspUpd.h
@@ -0,0 +1,50 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include <FspEas.h>
+
+#pragma pack(1)
+
+#define FSPT_UPD_SIGNATURE 0x545F445055524E47 /* 'GNRUPD_T' */
+
+#define FSPM_UPD_SIGNATURE 0x4D5F445055524E47 /* 'GNRUPD_M' */
+
+#define FSPS_UPD_SIGNATURE 0x535F445055524E47 /* 'GNRUPD_S' */
+
+#define FSPI_UPD_SIGNATURE 0x495F445055524E47 /* 'GNRUPD_I' */
+
+#pragma pack()
+
+#endif
diff --git a/BirchStreamFspBinPkg/ap/Include/FspmUpd.h b/BirchStreamFspBinPkg/ap/Include/FspmUpd.h
new file mode 100644
index 0000000..86c40eb
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/FspmUpd.h
@@ -0,0 +1,1866 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPM_UPD_H__
+#define __FSPM_UPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+typedef struct {
+
+/** Customer Revision
+ The Customer can set this revision string for their own purpose.
+**/
+ UINT8 CustomerRevision[32];
+
+/** Bus Ratio
+ Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO
+**/
+ UINT8 BusRatio[8];
+
+/** Legacy VGA Soc
+ Socket that claims the legacy VGA range
+**/
+ UINT8 LegacyVgaSoc;
+
+/** Legacy VGA Stack
+ Stack that claims the legacy VGA range
+**/
+ UINT8 LegacyVgaStack;
+
+/** Pcie P2P Performance Mode
+ Determine if to enable PCIe P2P Performance Mode
+ $EN_DIS
+**/
+ UINT8 P2pRelaxedOrdering;
+
+/** UPI Debug Print Level
+ UPI Debug Print Level Bitmask. 0- Disable, 1- Fatal, 2- Warning, 4- Summary, 8-
+ Detail, <b>0xF- All(Default)</b>
+ 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All
+**/
+ UINT8 DebugPrintLevel;
+
+/** NumaEn
+ Enable or Disable Numa
+ $EN_DIS
+**/
+ UINT8 NumaEn;
+
+/** SNC Enable
+ Enable or Disable SNC
+ 0x0:Disable, 0x1:Enable, 0x0F:Auto
+**/
+ UINT8 SncEn;
+
+/** IODC Mode
+ IODC Mode. 0- Disable, <b>1- Auto(Default)</b>, 2- Push, 3- AllocFlow, 4- NonAlloc, 5- WCILF
+ 0:Disable, 1:Auto, 2:Push, 3:AllocFlow, 4:NonAlloc, 5:WCILF
+**/
+ UINT8 IoDcMode;
+
+/** Degrade Precedence
+ Setup Degrade Precedence
+ 0:Topology, 1:Feature
+**/
+ UINT8 DegradePrecedence;
+
+/** Degrade 4 Socket Preference
+ Setup Degrade 4 Socket Preference
+ 0:Fully Connect, 1:Dual Link Ring
+**/
+ UINT8 Degrade4SPreference;
+
+/** Directory Mode
+ Enable or Disable Directory Mode
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 DirectoryModeEn;
+
+/** XPT Prefetch Enable
+ Enable or Disable XPT Prefetch
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 XptPrefetchEn;
+
+/** KTI Prefetch Enable
+ Enable or Disable KTI Prefetch
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 KtiPrefetchEn;
+
+/** XPT Remote Prefetch Enable
+ Enable or Disable XPT Remote Prefetch Enable
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 XptRemotePrefetchEn;
+
+/** Distress QoS Mode
+ Distress QoS. <b>0- Mode 0(Default)</b>, 2- Mode 2
+ 0:Mode 0, 2:Mode 2
+**/
+ UINT8 DistressQoS;
+
+/** KTI Link Speed Mode
+ Choose KTI Link Speed Mode
+ 0:Slow, 1:Full
+**/
+ UINT8 KtiLinkSpeedMode;
+
+/** KTI Link Speed
+ Setup KTI Link Speed - 2- 160GT, 3- 200GT, 4- 240GT, <b>0x7F- Max KTI Link Speed
+ (Default)</b>, 0x8F- Frequency Per Link
+ 2:160GT, 3:200GT, 4:240GT, 0x7F:Max KTI Link Speed, 0x8F:Frequency Per Link
+**/
+ UINT8 KtiLinkSpeed;
+
+/** KTI Link L0p
+ Enable or Disable KTI Link L0p
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 KtiLinkL0pEn;
+
+/** KTI Link L1
+ Enable or Disable KTI Link L1
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 KtiLinkL1En;
+
+/** Kti Link Speed Per Port
+ Setup KTI Link Speed to be allocated for each port, 2:160GT, 2:200GT, 3:240GT, 0X7f:Max
+ KTI Link Speed
+**/
+ UINT8 KtiLinkSpeedPerPort[48];
+
+/** DfxL0p Enable
+ Indicates the DfxL0p Enable to be allocated for each port, 0:Disable, 1:Enable
+**/
+ UINT8 DfxL0pEnable[48];
+
+/** DfxL1 Enable
+ Indicates the DfxL1 Enable to be allocated for each port, 0:Disable, 1:Enable
+**/
+ UINT8 DfxL1Enable[48];
+
+/** KTI Failover
+ Enable or Disable KTI Failover
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 KtiFailoverEn;
+
+/** KTI CRC Mode
+ Select KTI CRC Mode
+ 0:16bit, 1:32bit, 2:Auto
+**/
+ UINT8 KtiCrcMode;
+
+/** KTI CPU Socket Hotplug
+ Enable or Disable KTI CPU Socket Hotplug
+ $EN_DIS
+**/
+ UINT8 KtiCpuSktHotPlugEn;
+
+/** KTI CPU Socket HotPlug Topology
+ Select KTI CPU Socket HotPlug Topology
+ 0:4Socket, 1:8Socket
+**/
+ UINT8 KtiCpuSktHotPlugTopology;
+
+/** KTI SKU Mismatch Check
+ Enable or Disable KTI SKU Mismatch Check
+ $EN_DIS
+**/
+ UINT8 KtiSkuMismatchCheck;
+
+/** Sdsi Contrl Ib Lock
+ Enable or Disable Sdsi Contrl Ib Lock
+ $EN_DIS
+**/
+ UINT8 SdsiCtrlIbLock;
+
+/** TOR Threshold - Loctorem threshold Normal
+ Select TOR Threshold - Loctorem threshold Normal
+ 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
+**/
+ UINT8 TorThresLoctoremNorm;
+
+/** TOR threshold - Loctorem threshold empty
+ Select TOR threshold - Loctorem threshold empty
+ 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
+**/
+ UINT8 TorThresLoctoremEmpty;
+
+/** HA A to S directory optimization
+ Enable or Disable HA A to S directory optimization
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 StaleAtoSOptEn;
+
+/** LLC Deadline Allocation
+ Enable or Disable LLC Deadline Allocation
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 LLCDeadLineAlloc;
+
+/** MBA BW Calibration Profiles
+ Choice of MBA BW throttling curve
+ 0:Linear BW shaping, 1:Biased BW shaping, 2:Legacy BW shaping, 3:Auto
+**/
+ UINT8 MbeBWCalChoice;
+
+/** PMM MBA BW downscale
+ PMM BW downscaling vs the baseline Total memory BW profile. Eg- picking 1/2x results
+ in scaling PMM BW throttling in a 2:1 ratio vs. DDR throttling.
+ 0:PMM BW throttling in a 1/1 ratio vs. DDR throttling, 1:2/1 ratio, 2:4/1 ratio,
+ 3:8/1 ratio
+**/
+ UINT8 PmmMbaBWDownscale;
+
+/** CXL (Type3) MBA BW downscale
+ CXL (Type3) BW downscaling vs the baseline Total memory BW profile. Eg- picking
+ 1/2x results in scaling CXL (Type3) BW throttling in a 2:1 ratio vs. DDR throttling.
+ 0:CXL BW throttling in a 1/1 ratio vs. DDR throttling, 1:2/1 ratio, 2:4/1 ratio,
+ 3:8/1 ratio
+**/
+ UINT8 CxlMbaBWDownscale;
+
+/** Remote Target MBA BW downscale
+ Remote Target BW downscaling vs the baseline Total memory BW profile. Eg- picking
+ 1/2x results in scaling Remote Target BW throttling in a 2:1 ratio vs. DDR throttling.
+ 0:Remote Target BW throttling in a 1/1 ratio vs. DDR throttling, 1:2/1 ratio, 2:4/1
+ ratio, 3:8/1 ratio
+**/
+ UINT8 RemoteTargetMbaBWDownscale;
+
+/** Split Lock
+ Enable or Disable Split Lock
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 SplitLock;
+
+/** MMCFG Base Address
+ Setup MMCFG Base Address
+ 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 0xFF:Auto
+**/
+ UINT32 mmCfgBase;
+
+/** MMCFG Size
+ Select MMCFG Size
+ 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 0xFF:Auto
+**/
+ UINT32 mmCfgSize;
+
+/** MMIO High Base Address
+ MMIO High Base Address
+ 0:56T, 1:40T, 2:32T, 3:24T, 4:16T, 5:4T, 6:2T, 7:1T, 8:512G, 9:3584T, 10:30T, 11:60T,
+ 12:88T, 13:120T, 14:248T, 255:AUTO
+**/
+ UINT32 mmiohBase;
+
+/** CPU Physical Address Limit
+ CPU Physical Address Limit
+ $EN_DIS
+**/
+ UINT8 CpuPaLimit;
+
+/** MMIO High Size
+ MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space per CPU.
+ 0:1GB, 1:4GB, 2:16GB, 3:64GB, 4:256GB, 5:1024GB, 6:32GB, 255:AUTO
+**/
+ UINT32 mmiohSize;
+
+/** DCA
+ Enable or Disable DCA
+ $EN_DIS
+**/
+ UINT8 dcaEn;
+
+/** BoardTypeBitmask
+ BoardTypeBitmask
+**/
+ UINT32 BoardTypeBitmask;
+
+/** S3mClkSetupPtr
+ Pointer to clk setup variable data
+**/
+ UINT64 S3mClkSetupPtr;
+
+/** AllLanesPtr
+ Pointer to array of ALL_LANES_EPARAM_LINK_INFO
+**/
+ UINT64 AllLanesPtr;
+
+/** PerLanePtr
+ Pointer to array of PER_LANE_EPARAM_LINK_INFO
+**/
+ UINT64 PerLanePtr;
+
+/** AllLanesSizeOfTable
+ Number of elements in AllLanesPtr array.
+**/
+ UINT32 AllLanesSizeOfTable;
+
+/** PerLaneSizeOfTable
+ Number of elements in PerLanePtr array.
+**/
+ UINT32 PerLaneSizeOfTable;
+
+/** WaitTimeForPSBP
+ Enable or Disable WaitTimeForPSBP
+**/
+ UINT32 WaitTimeForPSBP;
+
+/** KtiInEnableMktme
+ Enable or Disable KtiInEnableMktme
+ $EN_DIS
+**/
+ UINT8 KtiInEnableMktme;
+
+/** HIOP STACK DISABLE
+ Enables/Disables given HIOP STACK. Default is AUTO no stack is disabled. 1 - The
+ stacks indicated by the bit locations are disabled. 0 - The stacks indicated by
+ the bit locations are not modified. The stack order is abstracted each bit 0 =
+ stack 0 ... bit n = stack n. The bit setting for each stack can be overriden by
+ BIOS based on part-knob compatibility. The array size must be MAX_SOCKET(Maximum:8) x UINT32.
+**/
+ UINT32 StackDisableBitMap[8];
+
+/** Processor VmxEnable Function
+ Enable(Default) or Disable Processor VmxEnable Function
+ $EN_DIS
+**/
+ UINT8 VmxEnable;
+
+/** Smm Relocation
+ Enable(Default)/Disable Smm Relocation
+ $EN_DIS
+**/
+ UINT8 SmmRelocationEnable;
+
+/** Processor HyperThreading Function
+ Enables Logical processor, 0- ALL LPs, 1- Single LP, 2- Two LPs
+ 0:ALL LPs, 1:Single LP, 2:Two LPs
+**/
+ UINT8 ProcessorLpEnable;
+
+/** Processor Safer Mode Extensions Function
+ Enable or Disable(Default) Processor Safer Mode Extensions Function
+ $EN_DIS
+**/
+ UINT8 ProcessorSmxEnable;
+
+/** Uncore Freq Control Compute
+ Mode 0: Power Limited Ordered Throttling Mode 1: Power Limited Proportional Throttling
+ 0:Mode 0, 1:Mode 1
+**/
+ UINT8 UncoreFreqCtrl;
+
+/** Uncore Freq Ratio Compute
+ 0: Set dynamic Uncore frequency range from max and min fused values. Otherwise Uncore
+ will run at a constant frequency ratio, the UFS algorithm will be disabled, but
+ physical limits may still reduce frequency. NOTE: The user input will be clipped
+ to the range accordingly during boot.
+**/
+ UINT8 UncoreFreqRatio;
+
+/** Uncore Freq Control IO
+ Mode 0: Power Limited Ordered Throttling Mode 1: Power Limited Proportional Throttling
+ 0:Mode 0, 1:Mode 1
+**/
+ UINT8 UncoreFreqCtrlIo;
+
+/** Uncore Freq Ratio IO
+ 0: Set dynamic Uncore frequency range from max and min fused values. Otherwise Uncore
+ will run at a constant frequency ratio, the UFS algorithm will be disabled, but
+ physical limits may still reduce frequency. NOTE: The user input will be clipped
+ to the range accordingly during boot.
+**/
+ UINT8 UncoreFreqRatioIo;
+
+/** DDR frequency limit
+ Select DDR frequency limit, <b>0x00- Auto(Default)</b>, 0x01:DDR_3200, 0x03:DDR_3600,
+ 0x05:DDR_4000, 0x07:DDR_4400, 0x08:DDR_4800, 0x09:DDR_5200, 0x0A:DDR_5600, 0x0B:DDR_6000,
+ 0x0C:DDR_6400
+**/
+ UINT8 HostDdrFreqLimit;
+
+/** DDR Over Clock Enable
+ DDR Over Clock Enable, 0- Disable, 1- Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 DdrOverClockEnable;
+
+/** Advanced Debug Function
+ Select Advanced Debug Function, 0- Disable, 1- Enable, 2- Auto
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 DfxAdvDebugJumper;
+
+/** Memory Serial Debug Message Level
+ Select Memory Serial Debug Message Level, 0- Disable, 1- Minimum, 2- Normal, 3-
+ Maximum, <b>4- Auto(Default)</b>, 5- Fixed PCD
+ 0:Disable, 1:Minimum, 2:Normal, 3:Maximum, 4:Auto, 5:Fixed PCD
+**/
+ UINT8 serialDebugMsgLvl;
+
+/** IIO IioPE0Bifurcation
+ IioPE0Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPE0Bifurcation[8];
+
+/** IIO IioPE1Bifurcation
+ IioPE1Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPE1Bifurcation[8];
+
+/** IIO IioPE2Bifurcation
+ IioPE2Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPE2Bifurcation[8];
+
+/** IIO IioPE3Bifurcation
+ IioPE3Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPE3Bifurcation[8];
+
+/** IIO IioPE4Bifurcation
+ IioPE4Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPE4Bifurcation[8];
+
+/** IIO IioPE5Bifurcation
+ IioPE5Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPE5Bifurcation[8];
+
+/** IIO IioPEaBifurcation
+ IioPEaBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPEaBifurcation[8];
+
+/** IIO IioPEbBifurcation
+ IioPEbBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPEbBifurcation[8];
+
+/** IIO IioPEcBifurcation
+ IioPEcBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPEcBifurcation[8];
+
+/** IIO IioPEdBifurcation
+ IioPEdBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPEdBifurcation[8];
+
+/** Toggle Msi Bypass
+ Msi Bypass: 0- Disable, 1- Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 CtrlMsiBypassEn;
+
+/** IIO Msi Bypass Enabled Ptr
+ Pointer to array of Msi Bypass Enabled settings Per Stack
+**/
+ UINT32 IioMsiBypassEnabledPtr;
+
+/** IIO Msi Bypass Enabled entry Number
+ Number of elements in IioMsiBypassEnabledPtr array, stack number as unit.
+**/
+ UINT32 IioMsiBypassEnabledNumber;
+
+/** IIO PCIE MaxPayload Ptr
+ Pointer to array of PCIE MaxPayload settings Per Port
+**/
+ UINT32 IioPcieMaxPayloadPtr;
+
+/** IIO PCIE MaxPayload entry Number
+ Number of elements in PcieMaxPayloadPtr array, port number as unit.
+**/
+ UINT32 IioPcieMaxPayloadNumber;
+
+/** IIO Board settings Hob Ptr
+ Pointer to array of IIO_BOARD_SETTINGS_HOB
+**/
+ UINT32 IioBoardSettingsHobPtr;
+
+/** IIO Board Settings Hob length
+ The IIO Board Settings Hob Length.
+**/
+ UINT32 IioBoardSettingsHobLength;
+
+/** Iio Setup Knobs pointer
+ : Iio Setup Knobs pointer
+**/
+ UINT64 IioSetupKnobsPtr;
+
+/** Iio Setup Knobs Size
+ : Iio Setup Knobs Size
+**/
+ UINT64 IioSetupKnobsSize;
+
+/** Iio SocketConfig Setup Knobs pointer
+ : Iio SocketConfig Setup Knobs pointer
+**/
+ UINT64 IioSocketConfigSetupKnobsPtr;
+
+/** Iio SocketConfig Setup Knobs Size
+ : Iio SocketConfig Setup Knobs Size
+**/
+ UINT64 IioSocketConfigSetupKnobsSize;
+
+/** IIO DeEmphasis Array Ptr
+ Pointer to array of DeEmphasis
+**/
+ UINT32 DeEmphasisPtr;
+
+/** IIO DeEmphasis Array Number
+ Number of elements in DeEmphasis array.
+**/
+ UINT32 DeEmphasisNumber;
+
+/** IIO PCIe Common Clock Array Ptr
+ Pointer to array of PCIe Common Clock
+**/
+ UINT32 PcieCommonClockPtr;
+
+/** IIO PCIe Common Clock Array Number
+ Number of elements in PCIe Common Clock array.
+**/
+ UINT32 PcieCommonClockNumber;
+
+/** IIO Cpm Enable Array Ptr
+ Pointer to array of Cpm Enable, which points to array Socket[MAX_SOCKET].Ioat[MAX_IIO_IOAT_PER_SOCKET].CpmEn
+**/
+ UINT32 IioCpmEnPtr;
+
+/** IIO Hqm Enable Array Ptr
+ Pointer to array of Hqm Enable, which points to array Socket[MAX_SOCKET].Ioat[MAX_IIO_IOAT_PER_SOCKET].HqmEn
+**/
+ UINT32 IioHqmEnPtr;
+
+/** Gen5LinkDegradation
+ Enable or disable Gen5 link degradation.
+ 0:Disable, 1:Enable
+**/
+ UINT8 Gen5LinkDegradation;
+
+/** PcieHotPlugEnable
+ Enable or disable Pcie hot plug enable feature
+ 0:Disable, 1:Enable
+**/
+ UINT8 PcieHotPlugEnable;
+
+/** DelayAfterPCIeLinkTraining
+ Custom delay after PCI-E link training on IIO ports
+**/
+ UINT16 DelayAfterPCIeLinkTraining;
+
+/** MSR Lock Control
+ Enable - MSR 3Ah and CSR 80h will be locked in FSP. Power Good reset is needed to
+ remove lock bits
+ 0:Disable, 1:Enable
+**/
+ UINT8 ProcessorMsrLockControl;
+
+/** Lock Chipset
+ Lock or Unlock chipset in FSP
+ 0:Disable, 1:Enable
+**/
+ UINT8 LockChipset;
+
+/** DFX Ev Mode
+ When Enabled, Expose IIO DFX devices and other CPU devices like PMON in FSP
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 DfxEvMode;
+
+/** DFX Disable Bios Done
+ When Enabled, suppresses notifying processor via MSR 151h that boot initialization
+ is finished in FSP
+ 0:Disable, 1:Enable
+**/
+ UINT8 DfxDisableBiosDone;
+
+/** PciBusResConfigPtr
+ Pointer to array of socket PCI bus resource.
+**/
+ UINT32 PciBusResConfigPtr;
+
+/** PciBaseLimitsResConfigPtr
+ Pointer to array of socket PCI IO/MMIO resource.
+**/
+ UINT32 PciBaseLimitsResConfigPtr;
+
+/** PCH PCIE PLL Ssc
+**/
+ UINT8 PchPciePllSsc;
+
+/** PchDciEn
+ Enable or <b>Disable(Default)</b> PCH DCI
+ 0:Disable, 1:Enable
+**/
+ UINT8 PchDciEn;
+
+/** MeUmaEnable
+ Enable or disable ME UMA feature
+ 0:Disable, 1:Enable
+**/
+ UINT8 MeUmaEnable;
+
+/** SerialIoUartDebugEnable
+ <b>Enable(Default)</b> or Disable SerialIo Uart debug library in FSP.
+ 0:Disable, 1:Enable
+**/
+ UINT8 SerialIoUartDebugEnable;
+
+/** ISA Serial Base selection
+ Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8
+ 0x2F8:0x2F8, 0x3F8:0x3F8
+**/
+ UINT16 SerialIoUartDebugIoBase;
+
+/** promoteMrcWarnings
+ Determines if MRC warnings are promoted to system level in FSP.
+ $EN_DIS
+**/
+ UINT8 promoteMrcWarnings;
+
+/** promoteWarnings
+ Determines if warnings are promoted to system level in FSP.
+ $EN_DIS
+**/
+ UINT8 promoteWarnings;
+
+/** serialDebugMsgLvlTrainResults
+ Enabled = set to display the training results. Training results also get displayed
+ if debug messages is set to Maximum in FSP.
+ $EN_DIS
+**/
+ UINT8 serialDebugMsgLvlTrainResults;
+
+/** Enhanced Log Parsing
+ Enables additional output in debug log for easier machine parsing in FSP.
+ $EN_DIS
+**/
+ UINT8 logParsing;
+
+/** MemTest
+ Enable - Enables memory test during normal boot. Disable - Disables this feature in FSP.
+ $EN_DIS
+**/
+ UINT8 HwMemTest;
+
+/** MemTest Loops
+ Number of memory test loops during normal boot, set to 0 to run memtest infinitely in FSP.
+**/
+ UINT16 MemTestLoops;
+
+/** Adv MemTest Options
+ This option is a bit mask[19:0]- All 0 = disabled- bit-0=XMATS8, bit-1=XMATS16,
+ bit-2=Reserved, bit-3=Reserved, bit-4=WCMATS8, bit-5=WCMCH8, bit-6=Reserved, bit-7=MARCHCM64,
+ bit-8=Reserved, bit-9=Reserved, bit-10=Reserved, bit-11=TWR, bit-12=DATARET, bit-13=MATS8TC1,
+ bit-14=MATS8TC2, bit-15=MATS8TC3, bit-16=SK-HYNIX, bit-17=SAMSUNG, bit-18=MICRON-RMW,
+ bit-19=SCRAM_X2 in FSP.
+**/
+ UINT32 AdvMemTestOptions;
+
+/** SmartTestKey
+ Number of SmartTest Key
+**/
+ UINT32 SmartTestKey;
+
+/** Adv MemTest Pause
+ Specify a pause delay between 0 to 255 in units of msec. This is a time period where
+ refresh is disabled between write and read sequences in FSP.
+**/
+ UINT8 AdvMemTestCondPause;
+
+/** Adv MemTest tREFI
+ Specify tREFI (refresh rate) timing between 1850 to 7800 in nsec.
+**/
+ UINT16 AdvMemTestCondTrefi;
+
+/** Adv MemTest tWR
+ Specify tWR timing between 48 to 96 in units of tCK in FSP.
+**/
+ UINT8 AdvMemTestCondTwr;
+
+/** Adv MemTest PMIC VDD Level
+ Specify PMIC VDD level in units of mV in FSP.
+**/
+ UINT16 AdvMemTestCondPmicVdd;
+
+/** Adv MemTest Conditions
+ Auto = set test conditions based on test type; Manual = specify global test conditions;
+ Disable = Do not apply test conditions in FSP.
+ 0:Disable, 1:Auto, 2:Manual
+**/
+ UINT8 AdvMemTestCondition;
+
+/** Adv MemTest Reset Failure Tracking List
+ Enable/disable Reset of the Row Failure Tracking List after each Adv MemTest option.
+ Useful for testing performance of multiple options in FSP.
+ $EN_DIS
+**/
+ UINT8 AdvMemTestResetList;
+
+/** MemTest On Cold Fast Boot
+ Enable - Enables memory test during cold fast boot. Disable - Disables this feature in FSP.
+ $EN_DIS
+**/
+ UINT8 MemTestOnColdFastBoot;
+
+/** Attempt Fast Boot
+ Enable - Portions of memory reference code will be skipped when possible to increase
+ boot speed on warm boots. Disable - Disables this feature in FSP.
+ $EN_DIS
+**/
+ UINT8 AttemptFastBoot;
+
+/** MemTest On Cold Fast Boot
+ Enable - Enables memory test during cold fast boot. Disable - Disables this feature in FSP.
+ $EN_DIS
+**/
+ UINT8 AttemptFastBootCold;
+
+/** Multithreaded Memory Training
+ Selects the number of processor sockets to train in parallel. 0 - All sockets operate
+ in parallel. 1 - At any time only one socket is executing. 2 - At any time only
+ two socket are executing. 4 - At any time only four socket are executing in FSP.
+ 0:All Processor Sockets, 1:One Socket at a Time (No Multithreading), 2:Two Sockets
+ at a Time, 4:Four Sockets at a Time
+**/
+ UINT8 AllowedSocketsInParallel;
+
+/** Auto-Reset on mem Training Error
+ Enable/Disable Auto-Reset on mem Training Error in FSP.
+ $EN_DIS
+**/
+ UINT8 AutoResetOnMemErr;
+
+/** Rank Margin Tool
+ Enable/Disable two types of rank margin in FSP.
+ 0:Normal RMT & Turnaround RMT Disabled, 1:Normal RMT Enabled, 2:Turnaround RMT Enabled,
+ 3:Normal RMT & Turnaround RMT Enabled, 4:Auto RMT Enable/Disabled
+**/
+ UINT8 EnableRMT;
+
+/** RMT on Fast Cold Boot
+ Enable/Disable the Rank Margin Tool on a Fast Cold Boot in FSP.
+ $EN_DIS
+**/
+ UINT8 EnableRMTonFCB;
+
+/** Execute Jedecinit before RMT
+ Execute Jedecinit before Rank Margin Tool in FSP.
+ $EN_DIS
+**/
+ UINT8 JedecInitBeforeRMT;
+
+/** Backside Margining
+ Enable/Disable margin test on the register or buffer backside in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTBacksideMargining;
+
+/** CmdAll
+ Step size of CmdAll. Auto- 1. Supported values- 1,2,4,8 in FSP.
+ 1:1, 2:2, 4:4, 8:8
+**/
+ UINT8 RMTCmdAll;
+
+/** RMT Debug Messages
+ Enable/Disable the RMT debug messages in FSP.
+ 2:Disable, 5:Enable
+**/
+ UINT8 RMTDebugMessages;
+
+/** RMT Display Tables
+ Enable/Disable displaying results as tables in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTDisplayTables;
+
+/** RMT Loop Count
+ Exponential loop count for single rank test in FSP.
+**/
+ UINT8 RMTLoopCount;
+
+/** Test Signal Bit Mask For RMT
+ Test signal bit mask for RMT in FSP.
+**/
+ UINT32 TestSignalBitMaskRMT;
+
+/** RMT Per Bit Margining
+ Enable/Disable Per Bit Margining in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTPerBitMargining;
+
+/** RMT Per CA Lane Margining
+ Enable/Disable Per CA Lane Margining in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTPerCaLaneMargining;
+
+/** RMT Per CS Lane Margining
+ Enable/Disable Per CS Lane Margining in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTPerCsLaneMargining;
+
+/** RMT Display Plots
+ Enable/Disable the display of per-bit results as plots in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTPerDisplayPlots;
+
+/** RMT RxDqs
+ Step size of RxDqs. Auto- 1. Supported values- 1,2,4,8 in FSP.
+ 1:Auto, 2:2, 4:4, 8:8
+**/
+ UINT8 RMTRxDqs;
+
+/** RMT RxVref
+ Step size of RxVref. Auto- 1. Supported values- 1,2,4,8 in FSP.
+ 1:Auto, 2:2, 4:4, 8:8
+**/
+ UINT8 RMTRxVref;
+
+/** Dfx RMT Scrambler
+ Enable or Disable scrambler during RMT test in FSP.
+ $EN_DIS
+**/
+ UINT8 DfxScrambleEnRMT;
+
+/** RMT Step Size Override
+ Enable or Disable overriding the default step sizes in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTStepSizeOverride;
+
+/** RMT TxDq
+ Step size of TxDq. Auto- 1. Supported values- 1,2,4,8 in FSP.
+ 1:Auto, 2:2, 4:4, 8:8
+**/
+ UINT8 RMTTxDq;
+
+/** RMT TxVref
+ Step size of TxVref. Auto- 1. Supported values- 1,2,4,8 in FSP.
+ 1:Auto, 2:2, 4:4, 8:8
+**/
+ UINT8 RMTTxVref;
+
+/** DDR5 ECS
+ Disable: Disable ECS/Result collection. Enable: Enable ECS without Result Collection.
+ Enable ECS with Result Collection: Enable ECS/Result Collection.
+ 0:Disable, 1:Enable, 2:Enable ECS with Result Collection
+**/
+ UINT8 ErrorCheckScrub;
+
+/** Runtime PPR/Row Sparing
+ Enable/Disable Runtime PPR / Row Sparing.
+ $EN_DIS
+**/
+ UINT8 RtRowSparing;
+
+/** Mca Bank Warm Boot Clear Errors
+ Enable/Disable Mca Bank Warm Boot Clear Errors.
+ $EN_DIS
+**/
+ UINT8 McBankWarmBootClearError;
+
+/** RasStateVarPtr
+ Pointer to array of RAS_STATE_VARIABLE_DATA
+**/
+ UINT32 RasStateVarPtr;
+
+/** Enforce Memory POR
+ Enforce POR (0x0) - Enforces Plan Of Record restrictions for DDR5 frequency and
+ voltage programming. Enforce Stretch Goals (0x1) - Enforce DDR memory frequency
+ stretch goal. <b>Disable (0x2 - Default)</b> - Disables this feature and user is
+ able to run at higher frequencies, specified in the DDR Frequency Limit field (limited
+ by processor support).
+ 0:POR, 1:Enforce Stretch Goals, 2:Disabled
+**/
+ UINT8 EnforceDdrMemoryFreqPor;
+
+/** Enforce Population POR
+ Enable Memory Population POR Enforcement. Selecting Enforce Validated Populations
+ will only allow populations that have been validated in FSP.
+ $EN_DIS
+**/
+ UINT8 EnforcePopulationPor;
+
+/** DDR PPR Type
+ Selects DDR Post Package Repair Type - 2- Hard PPR, <b>1- Soft PPR (Default)</b>,
+ 0- Disabled.
+ 0:Disabled, 2:Hard PPR, 1:Soft PPR
+**/
+ UINT8 pprType;
+
+/** pprAddrVariablePtr
+ Pointer to array of PPR_ADDR_VARIABLE
+**/
+ UINT32 PprAddrVariablePtr;
+
+/** BDAT ACPI Table
+ Enable / Disable publishing BDAT ACPI Table in FSP.
+ $EN_DIS
+**/
+ UINT8 bdatEn;
+
+/** Allow Memory Test Correctable Error
+ Enable - Logs error and allows correctable errors during memory test(DIMM Rank not
+ removed). Disable - Logs error and removes DIMM Rank. Auto - Sets it to the MRC
+ default setting; current default is Enable in FSP.
+ $EN_DIS
+**/
+ UINT8 allowCorrectableMemTestError;
+
+/** SlotPerChannel
+ Slot number per channel, default value is 2
+ 1:Slot1, 2:Slot2
+**/
+ UINT8 SlotPerChannel;
+
+/** Memory I/O Health Check
+ Memory I/O Health Check - 0- Auto, 1- Manual, <b>2- Disable (Default)</b>. Select
+ option Auto for default values. Manual for new values. Disable for disabling feature in FSP.
+ 0:Auto, 1:Manual, 2:Disable
+**/
+ UINT8 MemIOHealthCheck;
+
+/** Memory I/O Health Turnaround Test
+ Memory I/O Health Turnaround Test - 1- Enable, <b>0- Disable (Default)</b>. Select
+ Disable for disabling feature in FSP. Enable for enabling feature in FSP.
+ 0:Disable, 1:Enable
+**/
+ UINT8 MemIOHealthTurnaroundTest;
+
+/** Memory I/O Health Check Loop Count
+ CPGC Test Loop Count for Memory IO Health Test.
+**/
+ UINT8 MemIOLoopCount;
+
+/** RxDqsDelay Left Edge
+ Offset for RxDqsDelay Left Edge in FSP.
+**/
+ UINT8 CriticalRxDqsDelayLeftEdge;
+
+/** RxDqsDelay Right Edge
+ Offset for RxDqsDelay Right in FSP.
+**/
+ UINT8 CriticalRxDqsDelayRightEdge;
+
+/** RxVref Left Edge
+ Offset for RxVref Left Edge in FSP.
+**/
+ UINT8 CriticalRxVrefLeftEdge;
+
+/** RxVref Right Edge
+ Offset for RxVref Right Edge in FSP.
+**/
+ UINT8 CriticalRxVrefRightEdge;
+
+/** TxDqDelay Left Edge
+ Offset for TxDqDelay Left Edge in FSP.
+**/
+ UINT8 CriticalTxDqDelayLeftEdge;
+
+/** TxDqDelay Right Edge
+ Offset for TxDqDelay Right Edge in FSP.
+**/
+ UINT8 CriticalTxDqDelayRightEdge;
+
+/** TxVref Left Edge
+ Offset for TxDqDelay Left Edge in FSP.
+**/
+ UINT8 CriticalTxVrefLeftEdge;
+
+/** TxVref Right Edge
+ Offset for TxDqDelay Right Edge in FSP.
+**/
+ UINT8 CriticalTxVrefRightEdge;
+
+/** Reboot On Critical Failure
+ Reboot System on Critical failure to do Memory Training in FSP.
+ $EN_DIS
+**/
+ UINT8 ResetOnCriticalError;
+
+/** Number of Times to Reboot and Retrain
+ Number of times to Reboot System on Critical failure to do Memory Training in FSP.
+**/
+ UINT8 CriticalRetries;
+
+/** Telemetry RxDqsDelay Left Edge
+ Offset for Telemetry RxDqsDelay Left Edge in FSP.
+**/
+ UINT8 TelemetryRxDqsDelayLeftEdge;
+
+/** Telemetry RxDqsDelay Right Edge
+ Offset for Telemetry RxDqsDelay Right Edge in FSP.
+**/
+ UINT8 TelemetryRxDqsDelayRightEdge;
+
+/** Telemetry RxVref Left Edge
+ Offset for Telemetry RxDqsDelay Left Edge in FSP.
+**/
+ UINT8 TelemetryRxVrefLeftEdge;
+
+/** Telemetry RxVref Right Edge
+ Offset for Telemetry RxDqsDelay Right Edge in FSP.
+**/
+ UINT8 TelemetryRxVrefRightEdge;
+
+/** Telemetry TxDqDelay Left Edge
+ Offset for Telemetry TxDqDelay Left Edge in FSP.
+**/
+ UINT8 TelemetryTxDqDelayLeftEdge;
+
+/** Telemetry TxDqDelay Right Edge
+ Offset for Telemetry TxDqDelay Right Edge in FSP.
+**/
+ UINT8 TelemetryTxDqDelayRightEdge;
+
+/** Telemetry TxVref Left Edge
+ Offset for Telemetry TxDqDelay Left Edge in FSP.
+**/
+ UINT8 TelemetryTxVrefLeftEdge;
+
+/** Telemetry TxVref Right Edge
+ Offset for Telemetry TxDqDelay Right Edge in FSP.
+**/
+ UINT8 TelemetryTxVrefRightEdge;
+
+/** Telemetry CaTiming Left Edge
+ Offset for Telemetry CaTiming Left Edge in FSP.
+**/
+ UINT8 TelemetryCaTimingLeftEdge;
+
+/** Telemetry CaTiming Right Edge
+ Offset for Telemetry CaTiming Right Edge in FSP.
+**/
+ UINT8 TelemetryCaTimingRightEdge;
+
+/** Telemetry CtlTiming Left Edge
+ Offset for Telemetry CtlTiming Left Edge in FSP.
+**/
+ UINT8 TelemetryCtlTimingLeftEdge;
+
+/** Telemetry CtlTiming Right Edge
+ Offset for Telemetry CtlTiming Right Edge in FSP.
+**/
+ UINT8 TelemetryCtlTimingRightEdge;
+
+/** Telemetry CaVref Left Edge
+ Offset for Telemetry CaVref Left Edge in FSP.
+**/
+ UINT8 TelemetryCaVrefLeftEdge;
+
+/** Telemetry CaVref Right Edge
+ Offset for Telemetry CaVref Right Edge in FSP.
+**/
+ UINT8 TelemetryCaVrefRightEdge;
+
+/** Critical CaTiming Left Edge
+ Offset for Critical CaTiming Left Edge in FSP.
+**/
+ UINT8 CriticalCaTimingLeftEdge;
+
+/** Critical CaTiming Right Edge
+ Offset for Critical CaTiming Right Edge in FSP.
+**/
+ UINT8 CriticalCaTimingRightEdge;
+
+/** Critical CtlTiming Left Edge
+ Offset for Critical CtlTiming Left Edge in FSP.
+**/
+ UINT8 CriticalCtlTimingLeftEdge;
+
+/** Critical CtlTiming Right Edge
+ Offset for Critical CtlTiming Right Edge in FSP.
+**/
+ UINT8 CriticalCtlTimingRightEdge;
+
+/** Critical CaVref Left Edge
+ Offset for Critical CaVref Left Edge in FSP.
+**/
+ UINT8 CriticalCaVrefLeftEdge;
+
+/** Critical CaVref Right Edge
+ Offset for Critical CaVref Right Edge in FSP.
+**/
+ UINT8 CriticalCaVrefRightEdge;
+
+/** Intel(R) Flat Memory Mode Support
+ Enable or disable Intel(R) Flat Memory Mode support.
+ 0:Disable, 1:Enable
+**/
+ UINT8 Flat2lmSupport;
+
+/** Dynamic ECC Mode Selection
+ Enable/Disable Dynamic ECC Mode Selection in FSP.
+ $EN_DIS
+**/
+ UINT8 DynamicEccModeSel;
+
+/** Leaky bucket high bit
+ Leaky bucket high bit" (0x1 - 0x29)
+**/
+ UINT8 leakyBktHi;
+
+/** Leaky bucket time window based interface Hour
+ Leaky bucket time window based interface Hour" (0 - 24)
+**/
+ UINT16 leakyBktHour;
+
+/** Leaky bucket low bit
+ Leaky bucket low bit" (0x1 - 0x29)
+**/
+ UINT8 leakyBktLo;
+
+/** Leaky bucket time window based interface Minute
+ Leaky bucket time window based interface Minute" (0 - 60)
+**/
+ UINT8 leakyBktMinute;
+
+/** Leaky bucket time window based interface
+ Enable/Disable leaky bucket time window based interface
+ 0:Disable, 1:Enable
+**/
+ UINT8 leakyBktTimeWindow;
+
+/** Memory Patrol Scrub
+ Enable/Disable Patrol Scrub
+ 0:Disable, 2:Enable at End of POST
+**/
+ UINT8 PatrolScrub;
+
+/** Memory Patrol Scrub Notify
+ Memory Patrol Scrub - <b>0:Disable (Default)</b>, 1:Enable at ReadyToBootFsp().
+ 0:Disable, 1:Enable at ReadyToBootFsp()
+**/
+ UINT8 PatrolScrubNotify;
+
+/** Patrol Scrub Interval
+ Patrol Scrub Interval in FSP.
+**/
+ UINT8 PatrolScrubDuration;
+
+/** Patrol Scrub Address Mode
+ Selects the address mode between <b>System Physical Address (0x1 - Default)</b>
+ or Reverse Address (0x0) in FSP.
+ 0:Reverse Address, 1:System Physical Address
+**/
+ UINT8 PatrolScrubAddrMode;
+
+/** Memory Thermal Throttling Mode
+ Memory Configure Memory Thermal Throttling Mode in FSP.
+ 0:Disable, 2:CLTT, 3:CLTT with PECI
+**/
+ UINT8 thermalthrottlingsupport;
+
+/** Memory Correctable Error Threshold
+ Memory Correctable Error Threshold (1 - 32767) used for sparing and leaky bucket in FSP.
+**/
+ UINT16 spareErrTh;
+
+/** WR CRC feature Control
+ Enable/Disable Write CRC in FSP.
+ $EN_DIS
+**/
+ UINT8 WrCRC;
+
+/** DDR 2x Refresh Enable
+ Enable/Disable 2x Refresh. Auto = dynamically selected.
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 RefreshMode;
+
+/** Adaptive Refresh Management Level
+ Selects Adaptive Refresh Management(ARFM) Level when refresh management(RFM) is
+ required. 0:Default - RAAIMT, RAAMMT, RAADEC; 1:Level A - RAAIMT-A, RAAMMT-A, RAADEC-A;
+ 2:Level B - RAAIMT-B, RAAMMT-B, RAADEC-B; 3:Level C - RAAIMT-C, RAAMMT-C, RAADEC-C
+ 0:Default - RAAIMT or RAAMMT or RAADEC, 1:Level A - RAAIMT-A or RAAMMT-A or RAADEC-A,
+ 2:Level B - RAAIMT-B or RAAMMT-B or RAADEC-B, 3:Level C - RAAIMT-C or RAAMMT-C
+ or RAADEC-C
+**/
+ UINT8 AdaptiveRefreshMgmtLevel;
+
+/** CXL Hetero Support
+ Enable/Disable (Default) DDR CXL Heterogeneous Interleave in FSP.
+ $EN_DIS
+**/
+ UINT8 CxlHeteroSupport;
+
+/** MEMHOT INPUT Control
+ Enable/Disable MEMHOT INPUT in FSP.
+ $EN_DIS
+**/
+ UINT8 MemHotIn;
+
+/** MEMHOT OUTPUT Mode
+ MEMHOT OUTPUT Mode in FSP.
+ 0:Disable, 1:Enable only temphi, 2:Enable only temphi and mid, 3:Enable only temphi
+ mid and low
+**/
+ UINT8 MemhotOutputOnlyOpt;
+
+/** DfxPmicSecureMode
+ 0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode.
+ 0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode
+**/
+ UINT8 DfxPmicSecureMode;
+
+/** SpdPrintEn
+ Enable/Disable SPD Print
+ $EN_DIS
+**/
+ UINT8 SpdPrintEn;
+
+/** Force PPR On All Dram For UCE
+ Enable/Disable force PPR on all dram for UCE.
+ 0:Disable, 1:Enable
+**/
+ UINT8 ForcePprOnAllDramUce;
+
+/** CXL Header Bypass
+ Enable/Disable the CXL header bypass in FSP.
+ 0:Disable, 1:Enable
+**/
+ UINT8 DfxCxlHeaderBypass;
+
+/** CXL Security Level
+ CXL Security Level<br>\n
+ 0- Fully Trusted - CXL Device can get access on CXL.$ for host-attached and device
+ attached memory ranges in the WB address space.<br>\n
+ 1- Partially Trusted - CXL Device can get access on CXL.$ for device attached memory
+ ranges only;<br>\n
+ 2- Untrusted - All requests on CXL.$ will be aborted by the Host.<br>\n
+ <b>3- Auto - Currently identical to Fully Trusted. (Default)</b>
+ 0:Fully Trusted, 1:Partially Trusted, 2:Untrusted, 3:Auto
+**/
+ UINT8 DfxCxlSecLvl;
+
+/** CXL VID
+ CXL VID on SPR B0. Auto(Default) and Enable is 0x1E98. Disable is 0x8086
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 DfxCxlVid;
+
+/** Warm-Reset Elimination
+ When enabled, BIOS will attempt to skip warm-reset on the cold-reset path. Auto:
+ platform or silicon RC policy determines feature status
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 DfxWarmResetEliminationEn;
+
+/** IIO DFX CxlDebugMode Ptr
+ Pointer to array of CxlDebugMode settings Per Port, 0x00000000 indicates Dfx CXL
+ Debug mode Disable.
+**/
+ UINT32 DfxCxlDebugModePtr;
+
+/** IIO DFX CxlDebugMode Number
+ Number of elements in DfxCxlDebugModePtr array, port number as unit, should be set
+ along with DfxCxlDebugModePtr.
+**/
+ UINT32 DfxCxlDebugModeNumber;
+
+/** Processor Package C State
+ Package C State 0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention)
+ state, 7: No Limit, <b>0xFF: Auto (Default)</b>
+ 0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention) state,
+ 7: No Limit, 0xFF: Auto
+**/
+ UINT8 CpuPmPackageCState;
+
+/** Enhanced Intel SpeedStep(R) Tech
+ Enable(Default)/Disable Enhanced Intel SpeedStep(R) Tech
+ $EN_DIS
+**/
+ UINT8 CpuPmEistEnable;
+
+/** C1E
+ Enable(Default)/Disable C1E
+ $EN_DIS
+**/
+ UINT8 CpuPmC1eEnable;
+
+/** Intel SST-PP
+ Intel SST-PP Select allows user to choose level.\n
+ AUTO: Choose lowest level hardware supported.
+ 0xFF: AUTO (default), 0: Level 0, 1: Level 1, 2: Level 2, 3: Level 3, 4: Level 4
+**/
+ UINT8 CpuPmSstPpLevel;
+
+/** Intel SST-BF
+ SST-BF - <b>0: Disable (Default)</b>, 1: Enabled.
+ $EN_DIS
+**/
+ UINT8 CpuPmProcessorSstBfSetting;
+
+/** Core Disable Bitmask for Socket 0 - Compute Die 0
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0 - Compute Die
+ 0.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt0Die0;
+
+/** Core Disable Bitmask for Socket 0 - Compute Die 1
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0 - Compute Die
+ 1.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt0Die1;
+
+/** Core Disable Bitmask for Socket 0 - Compute Die 2
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0 - Compute Die
+ 2.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt0Die2;
+
+/** Core Disable Bitmask for Socket 1 - Compute Die 0
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1 - Compute Die
+ 0.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt1Die0;
+
+/** Core Disable Bitmask for Socket 1 - Compute Die 1
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1 - Compute Die
+ 1.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt1Die1;
+
+/** Core Disable Bitmask for Socket 1 - Compute Die 2
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1 - Compute Die
+ 2.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt1Die2;
+
+/** Processor Dynamic Intel Speed Select (ISS) Function
+ Enable or Disable(Default) Processor Dynamic Intel Speed Select (ISS) Function
+ $EN_DIS
+**/
+ UINT8 CpuPmDynamicIss;
+
+/** BIOS Region Base
+ Pointer to the location of the BIOS Region
+**/
+ UINT32 BiosRegionBase;
+
+/** BIOS Region Size
+ The size of the BIOS Region in bytes
+**/
+ UINT32 BiosRegionSize;
+
+/** Platform Data Area Base
+ Pointer to the location of the Platform Data Area
+**/
+ UINT32 PlatformDataAreaBase;
+
+/** Platform Data Area Size
+ The size of the Platform Data Area in bytes
+**/
+ UINT32 PlatformDataAreaSize;
+
+/** N/A
+**/
+ UINT8 ReservedMemoryInitUpd[16];
+
+/** Enable TME
+ Enable TME
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableTme;
+
+/** Enable TME CR
+ Enable TME CR
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableTmeCR;
+
+/** Enable MKTME
+ Enable MKTME
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableMktme;
+
+/** Enable Global Integrity
+ Enable Global Integrity
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableGlobalIntegrity;
+
+/** Select TME Crypto Algorithm
+ Enable Global Integrity
+ 0:Algo1,1:Algo2, 2:Algo3
+**/
+ UINT16 SecurityCctTmeCryptoAlg;
+
+/** Enable TDX
+ : Enable TDX
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableTdx;
+
+/** Enable TDX Connect
+ : Enable TDX Connect
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableTdxConnect;
+
+/** TDX Physical PCIe Port Disable Bitmap
+ TDX Physical PCIe Port Disable Bitmap
+**/
+ UINT16 SecurityCctTdxPhysicalPciePortDisableBitmap[8];
+
+/** Key Split
+ : Key Split
+**/
+ UINT8 SecurityCctKeySplit;
+
+/** Enable TDX SEAM Loader
+ : Enable TDX SEAM Loader
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableTdxSeamldr;
+
+/** Enabne SGX
+ : Enable SGX
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableSgx;
+
+/** Dfx Sgx CMCS Payload
+ Dfx Sgx CMCS Payload
+**/
+ UINT64 SecurityCctDfxSgxCmcsPayload[16];
+
+/** SGX QoS
+ : SGX QoS
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxQoS;
+
+/** SGX Auto Registration Agent
+ : SGX Auto Registration Agent
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxAutoRegistrationAgent;
+
+/** SGX Package Info In Band Access
+ : SGX Package Info In Band Access
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxPackageInfoInBandAccess;
+
+/** EPOCH Update
+ : EPOCH Update
+ 3:EpochDeactived, 0:EpochActived, 1:NewRandomEpoch, 2:ManualEpoch
+**/
+ UINT8 SecurityCctEpochUpdate;
+
+/** SGX EPOCH 0
+ : SGX EPOCH 0
+**/
+ UINT64 SecurityCctSgxEpoch0;
+
+/** SGX EPOCH 1
+ : SGX EPOCH 1
+**/
+ UINT64 SecurityCctSgxEpoch1;
+
+/** SGX LeWr
+ : SGX LeWr
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxLeWr;
+
+/** SGX Le Public Key Hash 0
+ : SGX Le Public Key Hash 0
+**/
+ UINT64 SecurityCctSgxLePubKeyHash0;
+
+/** SGX Le Public Key Hash 1
+ : SGX Le Public Key Hash 1
+**/
+ UINT64 SecurityCctSgxLePubKeyHash1;
+
+/** SGX Le Public Key Hash 2
+ : SGX Le Public Key Hash 2
+**/
+ UINT64 SecurityCctSgxLePubKeyHash2;
+
+/** SGX Le Public Key Hash 3
+ : SGX Le Public Key Hash 3
+**/
+ UINT64 SecurityCctSgxLePubKeyHash3;
+
+/** SGX Debug Mode
+ : SGX Debug Mode
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxDebugMode;
+
+/** SGX Factory Reset
+ : SGX Factory Reset
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxFactoryReset;
+
+/** Dfx Bios Param Header Override
+ : Dfx Bios Param Header Override
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxBiosParamHeaderOverride;
+
+/** Dfx Bios Param Header Version
+ : Dfx Bios Param Header Version
+**/
+ UINT16 SecurityCctDfxBiosParamHeaderVersion;
+
+/** Dfx Disable Actm Launch
+ : Dfx Disable Actm Launch
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxDisableActmLaunch;
+
+/** ACTM Flash Base
+ : ACTM Flash Base
+**/
+ UINT32 SecurityCctActmPcdFlash;
+
+/** Enable UPI FLE
+ : Enable UPI FLE
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableUpiFle;
+
+/** Enable SAF
+ : Enable SAF
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableSaf;
+
+/** Dfx TDX Disable 1MB CMR Exclude
+ : Dfx TDX Disable 1MB CMR Exclude
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxTdxDisable1MbCmrExclude;
+
+/** Dfx Seamldr Source location
+ : Dfx Seamldr Source location
+ 2:Auto, 0:ESP, 1:IFWI
+**/
+ UINT8 SecurityCctDfxSeamldrSrc;
+
+/** Dfx Tdx module Source location
+ : Dfx Tdx module Source location
+ 2:Auto, 0:ESP, 1:IFWI
+**/
+ UINT8 SecurityCctDfxTdxModuleSrc;
+
+/** Dfx PRMRR SEAMRR Support
+ : Dfx PRMRR SEAMRR Support
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxPrmrrSeamrrSupport;
+
+/** Dfx Simics Environment
+ : Dfx Simics Environment
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxSimicsEnvironment;
+
+/** Dfx Force UPL Unsupported
+ : Dfx Force UPL Unsupported
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxForceUplUnsupported;
+
+/** Dfx TME Key Restore
+ : Dfx TME Key Restore
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxTmeKeyRestore;
+
+/** Dfx TME Exclusion Base
+ : Dfx TME Exclusion Base
+**/
+ UINT64 SecurityCctDfxTmeExclusionBase;
+
+/** Dfx TME Exclusion Length
+ : Dfx TME Exclusion Length
+**/
+ UINT64 SecurityCctDfxTmeExclusionLength;
+
+/** Dfx MKTME KeyIdBits Override
+ : Dfx MKTME KeyIdBits Override
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxMkTmeKeyIdBitsOverride;
+
+/** Dfx MKTME KeyIdBits Override Value
+ : Dfx MKTME KeyIdBits Override Value
+**/
+ UINT8 SecurityCctDfxMkTmeKeyIdBitsOverrideValue;
+
+/** Dfx SGX Debug Print
+ : Dfx SGX Debug Print
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxDebugPrint;
+
+/** Dfx SGX Registration Server Select
+ : Dfx SGX Registration Server Select
+ 1:PRX, 0:SBX, 3:LIV, 4:SoftwareDefined, 2:Auto
+**/
+ UINT8 SecurityCctDfxSgxRegistrationServerSelect;
+
+/** Dfx SGX Add Package Support
+ : Dfx SGX Add Package Support
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxSgxAddPackageSupport;
+
+/** Dfx allow SGX non POR memory population
+ : Dfx SGX Add Package Support
+ 1:Enabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxAllowSgxNonPorMemoryPopulation;
+
+/** Dfx SGX Hang Before ACTM
+ : Dfx SGX Hang Before ACTM
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangBeforeActm;
+
+/** Dfx SGX Hang After ACTM
+ : Dfx SGX Hang After ACTM
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangAfterActm;
+
+/** Dfx SGX Hang Before MCHECK
+ : Dfx SGX Hang Before MCHECK
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangBeforeMcheck;
+
+/** Dfx SGX Hang After MCHECK
+ : Dfx SGX Hang After MCHECK
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangAfterMcheck;
+
+/** Dfx SGX Hang Before MSR 7A
+ : Dfx SGX Hang Before MSR 7A
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangBeforeMsr7a;
+
+/** Dfx SGX Hang After MSR 7A
+ : Dfx SGX Hang After MSR 7A
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangAfterMsr7a;
+
+/** Dfx disable CCT MSR_BIOS_DONE
+ : Dfx disable CCT MSR_BIOS_DONE
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxDisableCctBiosDone;
+
+/** Dfx Mcheck MSR 72
+ : Dfx Mcheck MSR 72 programming
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxMcheckMsr72;
+
+/** Dfx Skip Warm Reset Promotion
+ : Dfx Skip Warm Reset Promotion
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxSkipWarmResetPromotion;
+
+/** Enable SBFT
+ : Enable SBFT
+ 1:Enabled, 0:Disabled, 4:IfsSbftSgxEnabled
+**/
+ UINT8 SecurityCctEnableSbft;
+
+/** PRMRR SGX Size
+ : PRMRR SGX Size
+ 0x8000000:128MB, 0x10000000:256MB, 0x20000000:512MB, 0x40000000:1GB, 0x80000000:2GB,
+ 0x100000000:4GB, 0x200000000:8GB,0x400000000:16GB, 0x800000000:32GB, 0x1000000000:64GB,
+ 0x2000000000:128GB, 0x4000000000:256GB, 0x8000000000:512GB
+**/
+ UINT64 SecurityCctPrmrrSgxSize;
+
+/** PRMRR SAF Size
+ : PRMRR SAF Size
+ 0x0:Invalid, 0x800000:8MB, 0x2000000:32MB, 0x4000000:64MB, 0x8000000:128MB, 0x10000000:256MB
+**/
+ UINT64 SecurityCctPrmrrSafSize;
+
+/** PRMRR SBFT Size
+ : PRMRR SBFT Size
+ 0x0:Invalid, 0x10000000:256MB, 0x20000000:512MB
+**/
+ UINT64 SecurityCctPrmrrSbftSize;
+
+/** N/A
+ Pointer to node list which is used to initizalize security variables - CCT_VS_METADATA_NODE
+**/
+ EFI_PHYSICAL_ADDRESS SecurityCctVarStorageMetadataNodePtr;
+
+/** SINIT ACM SE SVN default
+ Default value of SINIT ACM SE SVN
+**/
+ UINT8 SecurityCctSinitAcmSeSvnFspDefault;
+
+/** SINIT ACM SE SVN override request
+ Override request for SINIT ACM SE SVN
+**/
+ UINT8 SecurityCctSinitAcmSeSvnOverrideRequest;
+
+/** SINIT ACM SE SVN value
+ Value of SINIT ACM SE SVN
+**/
+ UINT8 SecurityCctSinitAcmSeSvnValue;
+
+/** Setup data pointer
+ : Setup data pointer
+**/
+ UINT64 SetupDataPtr;
+
+/** Setup data Size
+ : Setup data Size
+**/
+ UINT64 SetupDataSize;
+
+/** Emulation Setting data pointer
+ : Emulation Setting data pointer
+**/
+ UINT64 EmulationSettingPtr;
+
+/** Emulation Setting data Size
+ : Emulation Setting data Size
+**/
+ UINT64 EmulationSettingSize;
+
+/** Platform info data pointer
+ : Platform info data pointer
+**/
+ UINT64 PlatformInfoPtr;
+
+/** Platform info data Size
+ : Platform info data Size
+**/
+ UINT64 PlatformInfoSize;
+
+/** FSPM Upd settings support
+ : FSPM Upd settings support
+ $EN_DIS
+**/
+ UINT8 FspmUpdSupport;
+
+/** Gen4 RCD Dimm support
+ Gen4 RCD Dimm support, 0- Disable, 1- Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 Gen4RcdDeviceSupport;
+
+} FSPM_CONFIG;
+
+
+typedef struct {
+
+/** N/A
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** N/A
+**/
+ FSPM_ARCH2_UPD FspmArchUpd;
+
+/** N/A
+**/
+ FSPM_CONFIG FspmConfig;
+
+/** N/A
+**/
+ UINT16 UpdTerminator;
+
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/BirchStreamFspBinPkg/ap/Include/FspsUpd.h b/BirchStreamFspBinPkg/ap/Include/FspsUpd.h
new file mode 100644
index 0000000..2bf198f
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/FspsUpd.h
@@ -0,0 +1,249 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPS_UPD_H__
+#define __FSPS_UPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+typedef struct {
+
+/** PCIe Controller 0
+ Enable / Disable PCI Express controller 0
+ $EN_DIS
+**/
+ UINT8 EnablePcie0;
+
+/** PCIe Controller 1
+ Enable / Disable PCI Express controller 1
+ $EN_DIS
+**/
+ UINT8 EnablePcie1;
+
+/** Embedded Multi-Media Controller (eMMC)
+ Enable / Disable Embedded Multi-Media controller
+ $EN_DIS
+**/
+ UINT8 EnableEmmc;
+
+/** LAN Controllers
+ Enable / Disable LAN controllers, refer to FSP Integration Guide for details.
+ 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only
+**/
+ UINT8 EnableGbE;
+
+/** PCIe Root Port 0 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort0DeEmphasis;
+
+/** PCIe Root Port 1 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort1DeEmphasis;
+
+/** PCIe Root Port 2 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort2DeEmphasis;
+
+/** PCIe Root Port 3 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort3DeEmphasis;
+
+/** PCIe Root Port 4 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort4DeEmphasis;
+
+/** PCIe Root Port 5 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort5DeEmphasis;
+
+/** PCIe Root Port 6 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort6DeEmphasis;
+
+/** PCIe Root Port 7 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort7DeEmphasis;
+
+/** eMMC DLL Configuration Data
+ Pointer to eMMC DLL Configuration Data
+**/
+ UINT32 EMMCDLLConfigPtr;
+
+/** PCH Protect Range Limit
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
+ limit comparison.
+**/
+ UINT16 PchProtectedRangeLimit[5];
+
+/** PCH Protect Range Base
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
+**/
+ UINT16 PchProtectedRangeBase[5];
+
+/** PchAdrEn
+ PchAdr 0:PLATFORM POR, <b>1:FORCE ENABLE(Default)</b>, 2:FORCE DISABLE
+ 0:PLATFORM POR, 1:FORCE ENABLE, 2:FORCE DISABLE
+**/
+ UINT8 PchAdrEn;
+
+/** Enable Timed GPIO0
+ Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
+ as extension of Hammock Harbor time synchronization
+ $EN_DIS
+**/
+ UINT8 EnableTimedGpio0;
+
+/** Enable Timed GPIO1
+ Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
+ as extension of Hammock Harbor time synchronization
+ $EN_DIS
+**/
+ UINT8 EnableTimedGpio1;
+
+/** FSP smm init enable
+ Enable / Disable FSP smm init
+ $EN_DIS
+**/
+ UINT8 FspSmmInitEn;
+
+/** C2C3TT
+ Default = 0, means [AUTO]. C2 to C3 Transition Timer, PPDN_INIT = C2C3TT CSR Bit[11:0]
+ 0: Default, Bit[11:0] : C2 to C3 Transition Timer
+**/
+ UINT8 CpuPmC2c3tt;
+
+/** Processor Enable Monitor MWAIT
+ Enable(Default) or Disable Processor Monitor MWAIT
+ $EN_DIS
+**/
+ UINT8 CpuPmMonitorMWait;
+
+/** Processor TurboMode Function
+ Enable(Default) or Disable Processor TurboMode Function
+ $EN_DIS
+**/
+ UINT8 CpuPmTurboMode;
+
+/** Hardware P-States
+ Disable: Hardware chooses a P-state based on OS Request (Legacy P-States)\n
+ Native Mode:Hardware chooses a P-state based on OS guidance\n
+ Out of Band Mode:Hardware autonomously chooses a P-state (no OS guidance)
+ 0:Disable, 1:Native Mode (Default), 2:Out of Band Mode, 3:Native Mode with No Legacy Support
+**/
+ UINT8 CpuPmProcessorHWPMEnable;
+
+/** HardwarePM Interrupt
+ Enable or Disable (Default) Hardware PM Interrupt
+ $EN_DIS
+**/
+ UINT8 CpuPmProcessorHWPMInterrupt;
+
+/** EPP Profile
+ Choose an HWPM Profile, 0: Performance, 128: Balanced Performance, 192: Balanced
+ Power, 255: Power
+ 0: Performance, 128: Balanced Performance, 192: Balanced Power, 255: Power
+**/
+ UINT8 CpuPmProcessorEPPProfile;
+
+/** Boot Performance Mode
+ Select the performance state that the BIOS will set before OS hand off, 0: Max Performance,
+ 1: Max Efficiency
+ 0: Max Performance (Default), 1: Max Efficiency
+**/
+ UINT8 CpuPmBootPstate;
+
+/** Power Performance Tuning
+ Power Performance Tuning <b>0: OS Controls EPB (Default)</b>, 1: BIOS Controls EPB,
+ 2: PECI Controls EPB
+ 0: OS Controls EPB, 1: BIOS Controls EPB, 2: PECI Controls EPB
+**/
+ UINT8 CpuPmPwrPerfTuning;
+
+/** FSPS Upd settings support
+ : FSPS Upd settings support
+ $EN_DIS
+**/
+ UINT8 FspsUpdSupport;
+
+/** N/A
+ Pointer to node list which is used to initizalize security variables - CCT_VS_METADATA_NODE
+**/
+ EFI_PHYSICAL_ADDRESS SecurityCctVarStorageMetadataNodePtr;
+
+/** N/A
+**/
+ UINT8 ReservedSiliconInitUpd[16];
+
+} FSPS_CONFIG;
+
+
+typedef struct {
+
+/** N/A
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** N/A
+**/
+ FSPS_ARCH2_UPD FspsArchUpd;
+
+/** N/A
+**/
+ FSPS_CONFIG FspsConfig;
+
+/** N/A
+**/
+ UINT16 UpdTerminator;
+
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/BirchStreamFspBinPkg/ap/Include/FsptUpd.h b/BirchStreamFspBinPkg/ap/Include/FsptUpd.h
new file mode 100644
index 0000000..2e7cfa1
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/FsptUpd.h
@@ -0,0 +1,101 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPT_UPD_H__
+#define __FSPT_UPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+typedef struct {
+
+/** N/A
+**/
+ UINT64 MicrocodeRegionBase;
+
+/** N/A
+**/
+ UINT64 MicrocodeRegionLength;
+
+/** N/A
+**/
+ UINT64 CodeRegionBase;
+
+/** N/A
+**/
+ UINT64 CodeRegionLength;
+
+} FSPT_CORE_UPD;
+
+
+typedef struct {
+
+/** Disable Port80 output in FSP-T
+ 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output
+**/
+ UINT8 FsptPort80RouteDisable;
+
+/** N/A
+**/
+ UINT8 ReservedTempRamInitUpd[31];
+
+} FSPT_CONFIG;
+
+
+typedef struct {
+
+/** N/A
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** N/A
+**/
+ FSPT_ARCH2_UPD FsptArchUpd;
+
+/** N/A
+**/
+ FSPT_CORE_UPD FsptCoreUpd;
+
+/** N/A
+**/
+ FSPT_CONFIG FsptConfig;
+
+/** N/A
+**/
+ UINT16 UpdTerminator;
+
+} FSPT_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/BirchStreamFspBinPkg/ap/Include/IioPcieConfigUpd.h b/BirchStreamFspBinPkg/ap/Include/IioPcieConfigUpd.h
new file mode 100644
index 0000000..0f33a0c
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/IioPcieConfigUpd.h
@@ -0,0 +1,300 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _IIO_PCIE_CONFIG_UPD_H_
+#define _IIO_PCIE_CONFIG_UPD_H_
+
+#ifndef MAX_SOCKET
+#define MAX_SOCKET 2
+#endif
+
+#ifndef MAX_LOGIC_IIO_STACK
+#define MAX_LOGIC_IIO_STACK 18
+#endif
+
+/**
+ * Maximum number of IIO ports per IIO stack.
+ */
+#ifndef MAX_IIO_PORTS_PER_STACK
+#define MAX_IIO_PORTS_PER_STACK 8
+#endif
+
+#define MAX_IIO_STACK 16
+#define MAX_IIO_STACKS_PER_SOCKET MAX_IIO_STACK
+#define MAX_IIO_PORTS_PER_SOCKET (MAX_IIO_STACKS_PER_SOCKET * MAX_IIO_PORTS_PER_STACK)
+
+#if MAX_SOCKET <= 4
+
+//
+// 10 PCIe stacks (PE) and 3 IO accelerator (IOAT) possible in Rich 1 Socket.
+// However, we share R1S image with 4 socket SP image, no separate build for R1S.
+// So use R1S definitions for 4 socket SP and 4 PE, 1 IOAT entry are just not used, never present.
+//
+#define MAX_IIO_PCIE_PER_SOCKET 10
+#else
+#define MAX_IIO_PCIE_PER_SOCKET 6
+#endif
+
+#define MAX_IOU_PER_SOCKET MAX_IIO_PCIE_PER_SOCKET
+
+#define IIO_BIFURCATE_xxxxxxxx 0xFE
+#define IIO_BIFURCATE_x4x4x4x4 0x0
+#define IIO_BIFURCATE_x4x4xxx8 0x1
+#define IIO_BIFURCATE_xxx8x4x4 0x2
+#define IIO_BIFURCATE_xxx8xxx8 0x3
+#define IIO_BIFURCATE_xxxxxx16 0x4
+#define IIO_BIFURCATE_x2x2x4x8 0x5
+#define IIO_BIFURCATE_x4x2x2x8 0x6
+#define IIO_BIFURCATE_x8x2x2x4 0x7
+#define IIO_BIFURCATE_x8x4x2x2 0x8
+#define IIO_BIFURCATE_x2x2x4x4x4 0x9
+#define IIO_BIFURCATE_x4x2x2x4x4 0xA
+#define IIO_BIFURCATE_x4x4x2x2x4 0xB
+#define IIO_BIFURCATE_x4x4x4x2x2 0xC
+#define IIO_BIFURCATE_x2x2x2x2x8 0xD
+#define IIO_BIFURCATE_x8x2x2x2x2 0xE
+#define IIO_BIFURCATE_x2x2x2x2x4x4 0xF
+#define IIO_BIFURCATE_x2x2x4x2x2x4 0x10
+#define IIO_BIFURCATE_x2x2x4x4x2x2 0x11
+#define IIO_BIFURCATE_x4x2x2x2x2x4 0x12
+#define IIO_BIFURCATE_x4x2x2x4x2x2 0x13
+#define IIO_BIFURCATE_x4x4x2x2x2x2 0x14
+#define IIO_BIFURCATE_x2x2x2x2x2x2x4 0x15
+#define IIO_BIFURCATE_x2x2x2x2x4x2x2 0x16
+#define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17
+#define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18
+#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19
+
+#define IIO_BIFURCATE_xxxxxxx4 0x40
+#define IIO_BIFURCATE_xxx2xxx2 0x41
+#define IIO_BIFURCATE_x1x1xxx2 0x42
+#define IIO_BIFURCATE_xxx2x1x1 0x43
+#define IIO_BIFURCATE_x1x1x1x1 0x44
+
+#define IIO_BIFURCATE_AUTO 0xFF
+
+#define C1_UID 2
+#define C2_UID 3
+
+/**
+ * VTBAR - Virtualization Technology BAR region size and alignment.
+ */
+#define IIO_VTBAR_LSB 16 // 64 kB
+#define IIO_VTBAR_SIZE (1 << IIO_VTBAR_LSB)
+
+#pragma pack(1)
+
+typedef enum {
+ PE0 = 0,
+ PE1,
+ PE2,
+ PE3,
+ PE4,
+ PE5,
+ PEa,
+ PEb,
+ PEc,
+ PEd,
+ PE_MAX,
+ PE_ = 0xFF // temporary unknown value
+} IIO_PACKAGE_PE;
+
+typedef struct {
+ struct {
+ UINT8 Segment; ///< Remember segment, if it changes reset everything
+ UINT8 StackPciBusPoolSize[MAX_LOGIC_IIO_STACK]; ///< Number of bus numbers needed for IIO stack
+ } Socket[MAX_SOCKET];
+} SYSTEM_PCI_BUS_CONFIGURATION;
+
+typedef struct {
+ UINT64 Base; ///< Base (starting) address of a range (I/O, 32 and 64-bit mmio regions)
+ UINT64 Limit; ///< Limit (last valid) address of a range
+} PCIE_BASE_LIMIT;
+
+typedef struct {
+ UINT32 MmioLSize;
+ UINT64 MmioHSize;
+} CXL11_LIMITS;
+
+typedef struct {
+ PCIE_BASE_LIMIT Io; ///< Base and limit of I/O range assigned to entity
+ PCIE_BASE_LIMIT LowMmio; ///< Base and limit of low MMIO region for entity
+ PCIE_BASE_LIMIT HighMmio; ///< Base and limit of high (64-bit) MMIO region for entity
+} PCI_BASE_LIMITS;
+
+typedef struct {
+ PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of all PCIe resources for each stack of the socket
+ CXL11_LIMITS CxlStackReq[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of CXL11 resources for each stack of the socket
+} SOCKET_PCI_BASE_LIMITS;
+
+typedef struct {
+ //
+ // Save basic system configuration parameters along with the resource map to detect a change.
+ // Remember low and high I/O memory range when saving recource configuration. It is used to verify
+ // whether system memory map changed. Remember also stacks configured when creating the map.
+ // If anything changed reset the system PCI resource configuration.
+ //
+ UINT64 MmioHBase;
+ UINT64 MmioHGranularity;
+ UINT32 MmioLBase;
+ UINT32 MmioLLimit;
+ UINT32 MmioLGranularity;
+ UINT16 IoBase;
+ UINT16 IoLimit;
+ UINT16 IoGranularity;
+ UINT32 StackPresentBitmap[MAX_SOCKET];
+ //
+ // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options
+ // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook
+ // which updates the KTI resource map.
+ //
+ SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET]; ///< Base and limit of all PCIe resources for each socket
+} SYSTEM_PCI_BASE_LIMITS;
+
+typedef struct {
+ UINT8 Address; // SMBUS address of IO expander which provides VPP register
+ UINT8 Port; // Port or bank on IoExpander which provides VPP register
+ UINT8 MuxAddress; // SMBUS address of MUX used to access VPP
+ UINT8 MuxChannel; // Channel of the MUX used to access VPP
+} IIO_VPP_CFG;
+
+typedef struct {
+ UINT8 Address; // SMBUS address of IO expander which provides NPEM
+ UINT8 Bank; // Port or bank on IoExpander which provides NPEM
+ UINT8 MuxAddress; // SMBUS address of MUX used to access NPEM
+ UINT8 MuxChannel; // Channel of the MUX used to access NPEM
+} IIO_NPEM_CFG;
+
+typedef struct {
+ UINT8 Eip : 1; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
+ UINT8 HotPlugSurprise : 1; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
+ UINT8 PowerInd : 1; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
+ UINT8 AttentionInd : 1; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
+ UINT8 PowerCtrl : 1; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
+ UINT8 AttentionBtn : 1; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
+
+ UINT8 Reserved : 2;
+} IIO_SLOT_CFG;
+
+typedef struct {
+ //
+ // Below is an excerpt from structure PCIE_PORT_ENTERPRISE_CONFIG
+ //
+ IIO_VPP_CFG Vpp;
+ IIO_NPEM_CFG Npem;
+ IIO_SLOT_CFG Slot;
+
+ UINT8 VppEnabled :1; // If VPP is supported on given port
+ UINT8 VppExpType :1; // IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE for values definitions)
+ UINT8 NpemSupported :1; // If NPEM is supported on given port
+
+ //
+ // Below is an excerpt IIO_PCIE_PORT_CONFIG
+ //
+ UINT8 SlotImplemented :1;
+ UINT8 Retimer1Present :1;
+ UINT8 Retimer2Present :1;
+ UINT8 CommonClock :1;
+ UINT8 SRIS :1;
+
+ //
+ // Below is an excerpt from structure PCIE_PORT_COMMON_CONFIG
+ //
+ UINT16 HotPlug : 1; // If hotplug is supported on slot connected to this port
+ UINT16 MrlSensorPresent : 1; // If MRL is present on slot connected to this port
+ UINT16 SlotPowerLimitScale : 2; // Slot Power Scale for slot connected to this port
+ UINT16 SlotPowerLimitValue : 12; // Slot Power Value for slot connected to this port
+
+ UINT16 PhysicalSlotNumber; // Slot number for slot connected to this port
+} IIO_BOARD_SETTINGS_PER_PORT;
+
+typedef enum {
+ IioBifurcation_UNKNOWN = IIO_BIFURCATE_xxxxxxxx,
+ IioBifurcation_x4x4x4x4 = IIO_BIFURCATE_x4x4x4x4,
+ IioBifurcation_x4x4xxx8 = IIO_BIFURCATE_x4x4xxx8,
+ IioBifurcation_xxx8x4x4 = IIO_BIFURCATE_xxx8x4x4,
+ IioBifurcation_xxx8xxx8 = IIO_BIFURCATE_xxx8xxx8,
+ IioBifurcation_xxxxxx16 = IIO_BIFURCATE_xxxxxx16,
+ IioBifurcation_x2x2x4x8 = IIO_BIFURCATE_x2x2x4x8,
+ IioBifurcation_x4x2x2x8 = IIO_BIFURCATE_x4x2x2x8,
+ IioBifurcation_x8x2x2x4 = IIO_BIFURCATE_x8x2x2x4,
+ IioBifurcation_x8x4x2x2 = IIO_BIFURCATE_x8x4x2x2,
+ IioBifurcation_x2x2x4x4x4 = IIO_BIFURCATE_x2x2x4x4x4,
+ IioBifurcation_x4x2x2x4x4 = IIO_BIFURCATE_x4x2x2x4x4,
+ IioBifurcation_x4x4x2x2x4 = IIO_BIFURCATE_x4x4x2x2x4,
+ IioBifurcation_x4x4x4x2x2 = IIO_BIFURCATE_x4x4x4x2x2,
+ IioBifurcation_x2x2x2x2x8 = IIO_BIFURCATE_x2x2x2x2x8,
+ IioBifurcation_x8x2x2x2x2 = IIO_BIFURCATE_x8x2x2x2x2,
+ IioBifurcation_x2x2x2x2x4x4 = IIO_BIFURCATE_x2x2x2x2x4x4,
+ IioBifurcation_x2x2x4x2x2x4 = IIO_BIFURCATE_x2x2x4x2x2x4,
+ IioBifurcation_x2x2x4x4x2x2 = IIO_BIFURCATE_x2x2x4x4x2x2,
+ IioBifurcation_x4x2x2x2x2x4 = IIO_BIFURCATE_x4x2x2x2x2x4,
+ IioBifurcation_x4x2x2x4x2x2 = IIO_BIFURCATE_x4x2x2x4x2x2,
+ IioBifurcation_x4x4x2x2x2x2 = IIO_BIFURCATE_x4x4x2x2x2x2,
+ IioBifurcation_x2x2x2x2x2x2x4 = IIO_BIFURCATE_x2x2x2x2x2x2x4,
+ IioBifurcation_x2x2x2x2x4x2x2 = IIO_BIFURCATE_x2x2x2x2x4x2x2,
+ IioBifurcation_x2x2x4x2x2x2x2 = IIO_BIFURCATE_x2x2x4x2x2x2x2,
+ IioBifurcation_x4x2x2x2x2x2x2 = IIO_BIFURCATE_x4x2x2x2x2x2x2,
+ IioBifurcation_x2x2x2x2x2x2x2x2 = IIO_BIFURCATE_x2x2x2x2x2x2x2x2,
+
+ // Specific values for DMR pcie4p4 controller for infrastructure lanes
+ IioBifurcation_xxxxxxx4 = IIO_BIFURCATE_xxxxxxx4,
+ IioBifurcation_xxx2xxx2 = IIO_BIFURCATE_xxx2xxx2,
+ IioBifurcation_x1x1xxx2 = IIO_BIFURCATE_x1x1xxx2,
+ IioBifurcation_xxx2x1x1 = IIO_BIFURCATE_xxx2x1x1,
+ IioBifurcation_x1x1x1x1 = IIO_BIFURCATE_x1x1x1x1,
+
+ IioBifurcation_Auto = IIO_BIFURCATE_AUTO
+} IIO_BIFURCATION;
+
+typedef struct {
+ IIO_BIFURCATION Bifurcation;
+ UINT8 CxlSupportInUba :1;
+ UINT8 Reserved :7;
+
+ IIO_BOARD_SETTINGS_PER_PORT Port[MAX_IIO_PORTS_PER_STACK];
+} IIO_BOARD_SETTINGS_PER_PE;
+
+typedef struct {
+ IIO_BOARD_SETTINGS_PER_PE Pe[MAX_IIO_PCIE_PER_SOCKET];
+} IIO_BOARD_SETTINGS_PER_SOCKET;
+
+//
+// HOB to store board settings data created based on UBA data
+//
+typedef struct {
+ IIO_BOARD_SETTINGS_PER_SOCKET Socket[MAX_SOCKET];
+} IIO_BOARD_SETTINGS_HOB;
+
+#pragma pack()
+
+#endif // _IIO_PCIE_CONFIG_UPD_H_
diff --git a/BirchStreamFspBinPkg/ap/Include/IioUniversalDataHob.h b/BirchStreamFspBinPkg/ap/Include/IioUniversalDataHob.h
new file mode 100644
index 0000000..cc82d24
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/IioUniversalDataHob.h
@@ -0,0 +1,219 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _IIO_UNIVERSAL_DATA_HOB_H_
+#define _IIO_UNIVERSAL_DATA_HOB_H_
+
+#define IIO_UNIVERSAL_DATA_GUID { 0x7FF396A1, 0xEE7D, 0x431E, { 0xBA, 0x53, 0x8F, 0xCA, 0x12, 0x7C, 0x44, 0xC0 } }
+
+#ifndef MAX_SOCKET
+#define MAX_SOCKET 2
+#endif
+
+#if (MAX_SOCKET == 1)
+ #define MAX_FW_KTI_PORTS 4 // Maximum KTI PORTS to be used in structure definition.
+#else
+ #define MAX_FW_KTI_PORTS 6 // Maximum KTI PORTS to be used in structure definition
+#endif //(MAX_SOCKET == 1)
+
+#define MAX_LOGIC_IIO_STACK 18
+
+#ifndef MAX_IIO_PCIROOTS_PER_STACK
+#define MAX_IIO_PCIROOTS_PER_STACK 3 // PCI roots that can be created for a stack
+#endif
+
+#define MAX_COMPUTE_DIE 3
+#define MAX_CHA_MAP (2 * MAX_COMPUTE_DIE) //for GNR & SRF only, each compute die has its own CAPID6 & CAPID7 (i.e. 2 CAPID registers)
+
+#ifndef MAX_MESSAGE_LENGTH
+#define MAX_MESSAGE_LENGTH 500
+#endif
+
+#define DINO_UID 0
+#define PC_UID 1
+#define UB_UID 4
+#define CPM0_UID 5
+#define HQM0_UID 6
+
+typedef enum {
+ IioStack0 = 0,
+ IioStack1 = 1,
+ IioStack2 = 2,
+ IioStack3 = 3,
+ IioStack4 = 4,
+ IioStack5 = 5,
+ IioStack6 = 6,
+ IioStack7 = 7,
+ IioStack8 = 8,
+ IioStack9 = 9,
+ IioStack10 = 10,
+ IioStack11 = 11,
+ IioStack12 = 12,
+ IioStack13 = 13,
+ IioStack14 = 14,
+ IioStack15 = 15,
+ IioStack16 = 16,
+ IioStackUnknown = 0xFF
+} IIO_STACK;
+
+//--------------------------------------------------------------------------------------//
+// Structure definitions for Universal Data Store (UDS)
+//--------------------------------------------------------------------------------------//
+#pragma pack(1)
+
+typedef struct {
+ UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
+ UINT8 PeerSocId; // Socket ID
+ UINT8 PeerSocType; // Socket Type (0 - CPU; 1 - IIO)
+ UINT8 PeerPort; // Port of the peer socket
+} QPI_PEER_DATA;
+
+typedef struct {
+ UINT8 Valid;
+ UINT8 PcieSegment;
+ UINT64 SegMmcfgBase;
+ UINT32 StackPresentBitmap;
+ UINT16 Cxl1p1PresentBitmap; // Bitmap of stacks where CXL 1p1 is connected
+ UINT16 CxlCapableBitmap; // Bitmap of stacks capable of CXL
+ UINT8 TotCha;
+ UINT32 SocId;
+ QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info
+} QPI_CPU_DATA;
+
+/**
+ * PCI resources that establish one PCI hierarchy for PCI Enumerator.
+ */
+typedef struct {
+ UINT16 UidType; // Type of UID for this root bridge.
+ UINT8 BusBase; // Base of PCI bus numbers available for PCI devices
+ UINT8 BusLimit; // Limit of PCI bus numbers available for PCI devices
+ UINT16 IoBase; // Base of IO resources available for PCI devices
+ UINT16 IoLimit; // Limit of IO resources available for PCI devices
+ UINT32 Mmio32Base; // Base of low MMIO resources available for PCI devices
+ UINT32 Mmio32Limit; // Limit of low MMIO resources available for PCI devices
+ UINT64 Mmio64Base; // Base of high MMIO resources available for PCI devices
+ UINT64 Mmio64Limit; // Limit of high MMIO resources available for PCI devices
+} UDS_PCIROOT_RES;
+
+/**
+ * This structore keeps resources configured in Host I/O Processor (HIOP) for one stack.
+ * One HIOP may produce more than one PCI hierarchy, these are in PciRoot[] table.
+ */
+typedef struct {
+ UINT8 Personality;
+ UINT8 PciRootBridgeNum; // Number of valid entries in PciRoot[] table
+ UINT8 Segment; // Segment for this stack
+ UINT8 BusBase; // Base of Bus configured for this stack
+ UINT8 BusLimit; // Limit of Bus configured for this stack
+ UINT8 Reserved[3]; // Reserved for alignment
+ UINT16 IoBase; // Base of IO configured for this stack
+ UINT16 IoLimit; // Limit of IO configured for this stack
+ UINT32 Mmio32Base; // Base of low MMIO configured for this stack in memory map
+ UINT32 Mmio32Limit; // Limit of low MMIO configured for this stack in memory map
+ UINT32 Mmio32MinSize; // The size of MMIO32 needed in PEI that must be preserved in rebalance
+ UINT64 Mmio64Base; // Base of high MMIO configured for this stack in memory map
+ UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map
+ UINT64 VtbarAddress; // VT-d Base Address
+ UINT64 ChbcrBarAddress; // CXL Host Bridge Component Registers (CHBCR) region
+ UDS_PCIROOT_RES PciRoot[MAX_IIO_PCIROOTS_PER_STACK];
+} UDS_STACK_RES;
+
+/**
+ * This structore keeps resource ranges configured in one socket. It contains a table of IO stacks provided by
+ // the socket. The stacks are also groupded by IO dies, but dies are not reflected in UDS.
+ */
+typedef struct {
+ UINT8 Valid;
+ UINT8 SocketID; // Socket ID of the IIO (0..3)
+ UINT16 IoBase;
+ UINT16 IoLimit;
+ UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
+ UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
+ UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
+ UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
+ UDS_STACK_RES StackRes[MAX_LOGIC_IIO_STACK];
+} UDS_SOCKET_RES;
+
+/**
+ * This structore keeps resource ranges configured in whole system.
+ */
+typedef struct {
+ UINT16 SystemIoBase; // System IO Base
+ UINT16 SystemIoLimit; // System IO Limit
+ UINT32 SystemIoApicBase; // Legacy IOAPIC base address, one in the system
+ UINT32 SystemIoApicLimit;
+ UINT32 SystemMmio32Base; // System low MMIO base
+ UINT32 SystemMmio32Limit; // System low MMIO limit
+ UINT64 SystemMmio64Base; // System high MMIO Base
+ UINT64 SystemMmio64Limit; // System high MMIO Limit
+ QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
+ UINT64 PciExpressBase; // PCI Config Space base address
+ UINT64 PciExpressSize; // PCI Config Space size
+ UDS_SOCKET_RES IIO_resource[MAX_SOCKET];
+ UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
+ UINT16 IoGranularity;
+ UINT32 Mmio32Granularity;
+ UINT64 Mmio64Granularity;
+ UINT32 UboxMmioSize;
+ UINT32 MemTolm;
+ UINT32 MemTsegSize;
+ UINT32 MaxAddressBits;
+} PLATFORM_DATA;
+
+typedef struct {
+ BOOLEAN FailFlag;
+ CHAR16 Message[MAX_MESSAGE_LENGTH];
+} REBALANCE_FAIL_INFO;
+
+typedef struct {
+ UINT8 CurrentUpiiLinkSpeed; // Current programmed UPI Link speed (Slow/Full speed mode)
+ UINT8 CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT)
+ UINT8 OutKtiCpuSktHotPlugEn; // 0 - Disabled, 1 - Enabled for PM X2APIC
+ UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
+ UINT8 SystemRasType;
+ UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
+ UINT8 OutSncEn;
+ UINT8 OutNumOfCluster;
+ UINT8 BitsUsed; //For 5 Level Paging
+ REBALANCE_FAIL_INFO RebalanceFailInfo;
+} SYSTEM_STATUS;
+
+typedef struct {
+ PLATFORM_DATA PlatformData;
+ SYSTEM_STATUS SystemStatus;
+ UINT32 OemValue;
+} IIO_UDS;
+
+#pragma pack()
+
+#endif // _IIO_UNIVERSAL_DATA_HOB_H_
+
diff --git a/BirchStreamFspBinPkg/ap/Include/MemoryMapDataHob.h b/BirchStreamFspBinPkg/ap/Include/MemoryMapDataHob.h
new file mode 100644
index 0000000..921e1be
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/MemoryMapDataHob.h
@@ -0,0 +1,359 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _MEMORY_MAP_DATA_HOB_H_
+#define _MEMORY_MAP_DATA_HOB_H_
+
+#define MEMORY_MAP_HOB_GUID { 0xf8870015, 0x6994, 0x4b98, { 0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f } }
+
+#ifndef MAX_SOCKET
+#define MAX_SOCKET 2
+#endif
+
+#ifndef MAX_IMC
+#define MAX_IMC 12 // Maximum memory controllers per socket
+#endif
+
+#ifndef MAX_MC_CH
+#define MAX_MC_CH 1 // Max number of channels per MC (3 for EP)
+#endif
+
+#ifndef MAX_CH
+#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
+#endif
+
+#ifndef MAX_CXL_HOST_BRIDGES
+#define MAX_CXL_HOST_BRIDGES 0x6 // Maximum number of CXL host bridges per socket.
+#endif
+
+#ifndef MAX_CXL_HOST_BRIDGE_WAYS
+#define MAX_CXL_HOST_BRIDGE_WAYS 0x4 // Maximum interleave ways of CXL host bridges per socket.
+#endif
+
+//
+// Macro definitions for abstracted memory decoding target. The data structure is designed to
+// iterate iMC and CXL host bridge host decoded memory in an unified way.
+// definition for GNRSRF/GNRD/GRR
+//
+#define MAX_CXL_AMT MAX_CXL_HOST_BRIDGES // Max number of unique interleaves for NGN DIMM
+
+
+#ifndef MAX_UNIQUE_NGN_DIMM_INTERLEAVE
+#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM
+#endif
+
+#ifndef MAX_SPARE_RANK
+#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel
+#endif
+
+#ifndef MAX_HBM_IO
+#define MAX_HBM_IO 4
+#endif
+
+#ifndef MAX_DIMM
+#define MAX_DIMM 2 // Max DIMM per channel
+#endif
+
+#ifndef MAX_RANK_DIMM
+#define MAX_RANK_DIMM 2
+#endif
+
+#ifndef MAX_DRAM_CLUSTERS
+#define MAX_DRAM_CLUSTERS 6
+#endif
+
+#ifndef MAX_SAD_RULES
+#define MAX_SAD_RULES 16
+#endif
+
+#ifndef MAX_FPGA_REMOTE_SAD_RULES
+#define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform
+#endif
+
+#define MAX_SI_SOCKET 8 // Maximum silicon supported socket number
+
+#define MAX_AMT (MAX_IMC+MAX_CXL_AMT) // Max abstract memory target per socket
+#define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets
+
+// NGN
+#define NGN_MAX_SERIALNUMBER_STRLEN 4
+#define NGN_MAX_PARTNUMBER_STRLEN 30
+#define NGN_FW_VER_LEN 4
+#define NGN_LOG_TYPE_NUM 2
+#define NGN_LOG_LEVEL_NUM 2
+
+/**
+ * Memory channel index conversion macros.
+ *
+ * We got two types of memory channel indexes:
+ * - socket channel - indexes 0..MAX_CH, used in [socket][channel] indexing
+ * - IMC channel - indexes 0..MAX_MC_CH, used in [socket][IMC][channel] indexing
+ * The below defined macros convert one channel index to the other one.
+ */
+#define MEM_SKTCH_TO_IMC(SktCh) ((SktCh) / MAX_MC_CH)
+#define MEM_SKTCH_TO_IMCCH(SktCh) ((SktCh) % MAX_MC_CH)
+#define MEM_IMCCH_TO_SKTCH(Imc, Ch) ((Imc) * MAX_MC_CH + (Ch))
+
+#define MEM_64MB_TO_BYTES(Size64M) ((UINT64)(Size64M) << 26)
+#define MEM_64MB_TO_KBYTES(Size64M) ((UINT64)(Size64M) << 16)
+#define MEM_64MB_TO_MBYTES(Size64M) ((UINT64)(Size64M) << 6)
+#define MEM_64MB_TO_GBYTES(Size64M) ((Size64M) >> 4)
+#define MEM_BYTES_TO_64MB(SizeB) ((SizeB) >> 26)
+#define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16)
+#define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6)
+
+typedef UINT8 INTLV_SET_KEY;
+
+#define FSP_RESERVED1_LEN 5748
+#define FSP_RESERVED2_LEN 1
+#define FSP_RESERVED3_LEN 220
+#define FSP_RESERVED4_LEN 10
+#pragma pack(1)
+
+struct RankDevice {
+ UINT8 enabled; // 0 = disabled, 1 = enabled
+ UINT8 logicalRank; // Logical Rank number (0 - 7)
+ UINT16 rankSize; // Units of 64 MB
+};
+
+struct PersisentDpaMap
+{
+ UINT32 perRegionDPAOffset;
+ UINT32 SPALimit;
+};
+
+typedef struct firmwareRev {
+ UINT8 majorVersion;
+ UINT8 minorVersion;
+ UINT8 hotfixVersion;
+ UINT16 buildVersion;
+} FIRMWARE_REV;
+
+typedef struct DimmDevice {
+ UINT8 Present;
+ BOOLEAN Enabled;
+ UINT8 DcpmmPresent; // 1 - This is a DCPMM
+ UINT8 X4Present;
+ UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
+ UINT8 NumRanks; // Number of ranks on dimm
+ UINT8 NumPackageRanks; // Number of Package ranks on dimm
+ // For DDR5 NumRanks and NumPackageRanks same
+ // For MRDIMM NumRanks and NumPackageRanks may differ
+ UINT8 keyByte;
+ UINT8 actKeyByte2; // Actual module type reported by SPD
+ UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width
+ UINT8 dimmTs; // Thermal sensor data.
+ UINT16 VolCap; // Volatile capacity (AEP DIMM only)
+ UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only)
+ UINT16 DimmSize;
+ UINT16 SPDMMfgId; // Module Mfg Id from SPD
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT32 perRegionDPA; // DPA of PMEM that Nfit needs
+ struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map
+ UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number
+ UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number
+ UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17
+ struct firmwareRev FirmwareVersion; // Firmware revision
+ struct RankDevice rankList[MAX_RANK_DIMM];
+ UINT16 InterfaceFormatCode;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT16 FisVersion; // Firmware Interface Specification version
+ UINT8 DimmSku; // Dimm SKU info
+ UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM
+ UINT16 manufacturingDate; // Date the NVDIMM was manufactured
+ INT32 commonTck;
+ UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
+ BOOLEAN NvDimmNPresent; // JEDEC NVDIMM-N Type Memory Present
+ UINT8 CidBitMap; // SubRankPer CS for DIMM device
+ UINT16 SPDRegVen; // Register Vendor ID in SPD
+ UINT8 SPDOtherOptFeatures; // SDRAM Other Optional features
+ BOOLEAN DimmChanged;
+} MEMMAP_DIMM_DEVICE_INFO_STRUCT;
+
+typedef struct ChannelDevice {
+ UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled
+ UINT8 Features; // Bit mask of features to enable or disable
+ UINT8 MaxDimm; // Number of DIMM
+ UINT8 NumRanks; // Number of ranks on this channel
+ UINT8 chFailed;
+ UINT8 ngnChFailed;
+ UINT8 Is4BitEccDimmPresent; // 4-bit Ecc dimm present indicator
+ UINT8 SpareLogicalRank[MAX_SPARE_RANK]; // Logical rank, selected as Spare
+ UINT8 SparePhysicalRank[MAX_SPARE_RANK]; // Physical rank, selected as spare
+ UINT16 SpareRankSize[MAX_SPARE_RANK]; // spare rank size
+ UINT8 EnabledLogicalRanks; // Bitmap of Logical ranks that are enabled
+ UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+ UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+ MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM];
+} CHANNEL_DEVICE;
+
+typedef struct memcontroller {
+ UINT32 MemSize;
+} MEMCONTROLLER;
+
+typedef enum {
+ MemTypeNone = 0,
+ MemType1lmDdr,
+ MemType1lmAppDirect,
+ MemType1lmAppDirectReserved,
+ MemType1lmCtrl,
+ MemType1lmHbm,
+ MemTypeNxm,
+ MemType2lmDdrCacheMemoryMode,
+ MemType2lmDdrWbCacheAppDirect,
+ MemType2lmHbmCacheDdr,
+ MemType2lmHbmCacheMemoryMode,
+ MemTypeCxlAccVolatileMem,
+ MemTypeCxlAccPersistentMem,
+ MemTypeFpga,
+ MemTypeCxlExpVolatileMem,
+ MemTypeCxlExpPersistentMem,
+ MemTypeCxl2lmDdrCacheMem,
+ MemTypeCxlHetero,
+ MemTypeCxlAccVolatileMemHdmDb,
+ MemTypeCxlExpVolatileMemDcd,
+ MemTypeMax
+} MEM_TYPE;
+
+typedef struct SADTable {
+ UINT8 Enable; // Rule enable
+ MEM_TYPE type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges.
+ UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options
+ UINT32 Base; // Base of the current SAD entry
+ UINT32 Limit; // Limit of the current SAD entry
+ UINT8 ways; // Interleave ways for SAD
+ UINT8 channelInterBitmap[MAX_AMT]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
+ UINT8 FMchannelInterBitmap[MAX_AMT]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
+ UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways for DDR4/NM.
+ UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap ways for DDRT.
+ UINT32 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket (based on channel ID for DMR).
+ UINT32 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM.
+ BOOLEAN local; // 0 - Remote 1- Local
+ UINT8 IotEnabled; // To indicate if IOT is enabled
+ UINT8 mirrored; // To Indicate the SAD is mirrored while enabling partial mirroring
+ UINT8 Attr;
+ UINT8 tgtGranularity; // Interleave mode for target list
+ UINT8 Cluster; // SNC cluster, hemisphere, or quadrant index.
+ UINT8 HostBridgeGran; // Host bridge interleaving granularity.
+ UINT8 HostBridgeList[MAX_CXL_HOST_BRIDGE_WAYS]; // List of interleaved CXL host bridges (DMR and beyond).
+ UINT32 HotPlugPadSize; // Memory size padded for CXL hot plug. 0 if it is not a CXL hot plug SAD.
+ INTLV_SET_KEY CxlIntlvSetKey; // The unique key of CXL interleave set. (7nm)
+} SAD_TABLE;
+
+typedef struct socket {
+ UINT8 SocketEnabled;
+ UINT32 IioStackBitmap;
+ BOOLEAN HbmIoEn[MAX_HBM_IO]; // Flag indicates if HBM IO is enabled. TRUE: HBM IO is Enabled, FALSE: HBM IO is disabled.
+ UINT8 imcEnabled[MAX_IMC];
+ UINT8 SadIntList[MAX_DRAM_CLUSTERS * MAX_SAD_RULES][AMT_MAX_NODE]; // SAD interleave list
+ UINT32 SktTotMemMapSPA; // Total memory mapped to SPA
+ SAD_TABLE SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; // SAD table
+ MEMCONTROLLER imc[MAX_IMC];
+ CHANNEL_DEVICE ChannelInfo[MAX_CH];
+} MEMMAP_SOCKET;
+
+typedef struct {
+ UINT8 Enabled; // Indicates if this EDC is enabled
+ UINT32 MemAsCache; // Memory used as Cache, in 64MB units
+ UINT32 MemAsFlat; // Memory used as Flat memory, in 64MB units
+} EDC_INFO;
+
+typedef struct SystemMemoryMapElement {
+ UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
+ UINT8 NodeId; // Node ID of the HA Owning the memory
+ UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
+ UINT8 ClusterId; // Logical cluster Id of SNC cluster - only 0 in UMA clustering and all2all
+ UINT8 SktInterBitmap; // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets
+ UINT32 ImcInterBitmap; // IMC interleave bitmap for this memory
+ UINT8 ChInterBitmap[MAX_AMT];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
+ UINT32 BaseAddress; // Base Address of the element in 64MB chunks
+ UINT32 ElementSize; // Size of this memory element in 64MB chunks
+} SYSTEM_MEMORY_MAP_ELEMENT;
+
+typedef struct SystemMemoryMapHob {
+ //
+ // Total Clusters. In SNC2 mode there are 2 clusters and SNC4 mode has 4 clusters.
+ // All2All/Hex/Quad/Hemi modes can be considered as having only one cluster (i.e SNC1).
+ //
+ UINT8 TotalClusters;
+ UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem.
+ UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem.
+ UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem.
+ UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem.
+ UINT32 memSize; // Total physical memory size
+ UINT16 memFreq; // Mem Frequency
+ UINT16 HbmFreq; // HBM Frequency in MHz.
+ UINT8 memMode; // 0 - Independent, 1 - Lockstep
+ UINT8 VolMemMode; // 0 - 1LM, 1 - 2LM
+ UINT16 DramType;
+ UINT8 DdrVoltage;
+ UINT8 XMPProfilesSup;
+ UINT8 XMPCapability;
+ //
+ // HBM Specific Info.
+ //
+ UINT16 HbmInstances[MAX_SOCKET]; // Total HBM instances
+ UINT32 HbmFlatMemSize; // Total HBM memory size in 64MB units, if HBM used as Flat memory
+ UINT32 HbmCacheMemSize; // Total HBM memory used as cache, if HBM used as Cache memory
+ UINT16 HbmSpeed; // Configured HBM (i.e OPIO channel) speed in MT/s.
+ UINT16 MaxHbmSpeed; // Max HBM (i.e OPIO channel) speed in MT/s.
+ UINT8 SystemRasType;
+ UINT8 RasModesEnabled; // RAS modes that are enabled
+ UINT16 ExRasModesEnabled; // Extended RAS modes that are enabled
+ UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
+ UINT8 NumOfCluster;
+ UINT8 NumChPerMC;
+ UINT8 numberEntries; // Number of Memory Map Elements
+ SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
+ UINT8 reserved1[FSP_RESERVED1_LEN]; // struct memSetup MemSetup;
+ UINT8 reserved2[FSP_RESERVED2_LEN]; // MEM_DFXMEMVARS DfxMemVar;
+ MEMMAP_SOCKET Socket[MAX_SOCKET];
+ UINT8 reserved3[FSP_RESERVED3_LEN]; // struct memTiming profileMemTime[XMP_MAX_PROFILES];
+
+ UINT8 reserved4[FSP_RESERVED4_LEN]; // RASMEMORYINFO RasMeminfo;
+ UINT32 DdrCacheSize[MAX_SOCKET][MAX_CH]; // Size of DDR memory reserved for 2LM cache (64MB granularity)
+ UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS
+ UINT32 MmiohBase; // MMIOH base in 64MB granularity
+ UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (16 for 10nm silicon)
+ UINT8 NumberofChaDramClusters; // Number of CHA DRAM decoder clusters
+ BOOLEAN VirtualNumaEnable; // Enable or Disable Virtual NUMA
+ UINT8 VirtualNumaNodes; // Number of virtual NUMA nodes per physical NUMA node (non-zero)
+ BOOLEAN MrDimmMemFreqRangeEn; // MRDIMM Memory Frequency range enabled.
+} SYSTEM_MEMORY_MAP_HOB;
+
+#pragma pack()
+
+#endif // _MEMORY_MAP_DATA_H_
diff --git a/BirchStreamFspBinPkg/ap/Include/PrevBootErrSrcHob.h b/BirchStreamFspBinPkg/ap/Include/PrevBootErrSrcHob.h
new file mode 100644
index 0000000..6eeabd3
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/PrevBootErrSrcHob.h
@@ -0,0 +1,86 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _PREV_BOOT_ERR_SRC_HOB_H_
+#define _PREV_BOOT_ERR_SRC_HOB_H_
+
+#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID { 0x5138b5c5, 0x9369, 0x48ec, { 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 } }
+
+#define PREV_BOOT_ERR_SRC_HOB_SIZE 1000
+
+#pragma pack(1)
+
+typedef struct {
+UINT16 Length; // Actual size of the error sources used in the HOB
+UINT8 HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2]; // List of Error source structures of format //MCBANK_ERR_INFO or CSR_ERR_INFO
+}PREV_BOOT_ERR_SRC_HOB;
+
+typedef struct{
+UINT8 Type; // McBankType = 1;
+UINT8 Segment;
+UINT8 Socket;
+UINT16 ApicId; // ApicId is Needed only if it a core McBank.
+UINT16 McBankNum;
+UINT64 McBankStatus;
+UINT64 McbankAddr;
+UINT64 McBankMisc;
+} MCBANK_ERR_INFO;
+
+typedef struct {
+UINT8 Type; // PciExType =2 ;
+UINT8 Segment;
+UINT8 Bus;
+UINT8 Device;
+UINT8 Function;
+UINT32 AerUncErrSts;
+UINT8 AerHdrLogData[16];
+} PCI_EX_ERR_INFO;
+
+typedef struct {
+UINT8 Type; // Other Csr error type =3 ;
+UINT8 Segment;
+UINT8 Bus;
+UINT8 Device;
+UINT8 Function;
+UINT16 offset;
+UINT32 Value;
+} CSR_ERR_INFO;
+
+typedef enum {
+ McBankType = 1,
+ PciExType,
+ CsrOtherType
+} ERROR_ACCESS_TYPE;
+
+#pragma pack()
+
+#endif //_PREV_BOOT_ERR_SRC_HOB_H_
diff --git a/BirchStreamFspBinPkg/ap/Include/SystemInfoHob.h b/BirchStreamFspBinPkg/ap/Include/SystemInfoHob.h
new file mode 100644
index 0000000..6890066
--- /dev/null
+++ b/BirchStreamFspBinPkg/ap/Include/SystemInfoHob.h
@@ -0,0 +1,271 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _SYSTEM_INFO_HOB_H_
+#define _SYSTEM_INFO_HOB_H_
+
+#define SYSTEM_INFO_HOB_GUID { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 } }
+
+#ifndef MAX_SOCKET
+#define MAX_SOCKET 2
+#endif
+
+#ifndef MAX_IIO_STACK
+#define MAX_IIO_STACK 16
+#endif
+
+#define MAX_LOGIC_IIO_STACK 18
+#define MAX_HPM_PFS_ENTRY_NUM 15 // Number of entries in PFS structure
+#define HPM_PFS_ENTRY_SIZE 2 // Entry size of PFS structure in DWORD
+
+#ifndef MAX_IMC
+#define MAX_IMC 12 // Maximum memory controllers per socket
+#endif
+
+#ifndef MAX_MC_CH
+#define MAX_MC_CH 1 // Max number of channels per MC (3 for EP)
+#endif
+
+#ifndef MAX_CH
+#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
+#endif
+
+#pragma pack(1)
+
+typedef enum {
+ TYPE_SCF_BAR = 0,
+ TYPE_PCU_BAR,
+ TYPE_MEM_BAR0,
+ TYPE_MEM_BAR1,
+ TYPE_MEM_BAR2,
+ TYPE_MEM_BAR3,
+ TYPE_MEM_BAR4,
+ TYPE_MEM_BAR5,
+ TYPE_MEM_BAR6,
+ TYPE_MEM_BAR7,
+ TYPE_SBREG_BAR,
+ TYPE_MAX_MMIO_BAR
+} MMIO_BARS;
+
+typedef enum {
+ ReservedMemSs,
+ Ddr4MemSs = 1,
+ Ddr5MemSs = 2,
+ LpDdr4MemSs = 3,
+ LpDdr5MemSs = 4,
+ Hbm2MemSs = 5,
+ MrcMstMax,
+ MrcMstDelim = MAX_INT32
+} MRC_MST;
+
+typedef enum BootMode {
+ NormalBoot = 0, // Normal path through RC with full init, mem detection, init, training, etc.
+ // Some of these MRC specific init routines can be skipped based on MRC input params
+ // in addition to the sub-boot type (WarmBoot, WarmBootFast, etc).
+ S3Resume = 1 // S3 flow through RC. Should do the bare minimum required for S3
+ // init and be optimized for speed.
+} BOOT_MODE;
+
+//
+// This is used to determine what type of die is connected to a UPI link
+//
+typedef enum {
+ UpiConnectionTypeCpu,
+ UpiConnectionTypePcieGen4,
+ UpiConnectionTypeFpga,
+ UpiConnectionTypeMax
+} UPI_CONNECTION_TYPE;
+
+//
+// VSEC info for HPM
+// The HPM_INFO struct contains info collected from the VSEC structure for the HPM.
+// VSEC Structure is defined as below:
+//
+// ------------------------VSEC Structure------------------------
+// | Next Cap Offset(12b) | Cap Version(4b) | PCIe Cap ID(16b) |
+// --------------------------------------------------------------
+// | VSEC_LEN(12b) | VSEC_REV(4b) | VSEC_ID(16b) |
+// --------------------------------------------------------------
+// | EntrySize(8b) | NumEntries(8b) | Rsvd(16b) |
+// --------------------------------------------------------------
+// | Address(29b) | tBIR(3b) |
+// --------------------------------------------------------------
+//
+//
+typedef struct {
+ UINT8 NumEntries; // The number of PM feature interface instances in this VSEC space
+ UINT8 EntrySize; // The entry size for each PM interface instance in 32-bit DWORDs
+ UINT32 Address; // The offset from the BAR register which is used for HPM to point to the base of the discovery entry. i.e. the PFS (PM Feature Structure)
+ UINT8 tBIR; // Which one of he function's BAR is used for the PFS offset
+} HPM_INFO;
+
+//
+//-------------------------------- - PFS Entry--------------------------------
+//| EntrySize(16b) | NumEntries(8b) | VSEC_SubID(8b) |
+//----------------------------------------------------------------------------
+//| RSVD(14b) | Attr(2b) | CapOffset(16b) |
+//----------------------------------------------------------------------------
+//
+typedef struct {
+ UINT32 TpmiId : 8;
+ UINT32 NumEntries : 8;
+ UINT32 EntrySize : 16;
+ UINT32 CapOffset : 16;
+ UINT32 Attribute : 2;
+ UINT32 EntryBitMap : 8;
+ UINT32 Rsvd : 6;
+} PFS_ENTRY;
+
+//
+// HPM (Hierarchical Power Management) VSEC resource allocation info
+//
+typedef struct {
+ BOOLEAN HpmEnabled; // HPM enabled or not in BIOS knob
+ BOOLEAN HpmInfraReady; // All the HPM infrastructure data is buffered
+ UINT32 OobMsmHpmBarBase; // The base of OOBMSM BAR1 for HPM PFS and LUT tables
+ UINT32 OobMsmHpmBarLimit; // The limit of OOBMSM BAR1 from where the required size will be allocated
+ UINT32 OobMsmHpmBarMmcfgAddress; // The OOBMSM BAR1 MMCFG address
+ UINT32 OobMsmHpmBarRequiredSize; // The required size of OOBMSM BAR1
+
+ HPM_INFO HpmVsecInfo; // For now, single VSEC is assumed
+ PFS_ENTRY Pfs[MAX_HPM_PFS_ENTRY_NUM]; // The buffered PFS structure
+
+} HPM_VSEC_RESOURCE;
+
+typedef struct {
+ UINT32 StackPresentBitmap[MAX_SOCKET]; ///< bitmap of present stacks per socket
+ UINT8 StackBus[MAX_SOCKET][MAX_LOGIC_IIO_STACK];///< Bus of each stack
+ UINT32 StackMmiol[MAX_SOCKET][MAX_IIO_STACK]; ///< mmiol of each IIO stack, if it works as CXL, the mmiol base is RCRBBAR
+ UINT8 SocketFirstBus[MAX_SOCKET];
+ UINT8 Socket10nmUboxBus0[MAX_SOCKET]; //10nm CPU use only
+ UINT8 TotIoDie[MAX_SOCKET]; //GNR & SRF CPU use only
+ UINT8 TotCmpDie[MAX_SOCKET]; //GNR & SRF CPU use only
+ UINT8 SocketLastBus[MAX_SOCKET];
+ UINT8 segmentSocket[MAX_SOCKET];
+ UINT8 KtiPortCnt;
+ UINT32 socketPresentBitMap;
+ UINT32 FpgaPresentBitMap;
+ UINT32 mmCfgBase;
+ UINT64 SocketMmCfgBase[MAX_SOCKET];
+ UINT8 DdrMaxCh;
+ UINT8 DdrMaxImc; ///< Logical number of IMC count, ignoring logical holes
+ UINT8 DdrPhysicalMaxImc; ///< Physical number of IMC count from Capid
+ UINT8 DdrNumChPerMc;
+ UINT8 DdrNumPseudoChPerCh;
+ UINT8 imcEnabled[MAX_SOCKET][MAX_IMC];
+ UINT8 mcId[MAX_SOCKET][MAX_CH];
+ MRC_MST MemSsType[MAX_SOCKET]; ///< MemSsType global identifier for DDR vs. HBM
+ UINT32 MmioBar[MAX_SOCKET][TYPE_MAX_MMIO_BAR];
+ UINT8 HbmMaxCh;
+ UINT8 HbmMaxIoInst;
+ UINT8 HbmNumChPerMc;
+ UINT8 HbmNumChPerIo;
+ UINT32 LastCsrAddress[2];
+ UINT32 LastCsrMmioAddr;
+ UINT8 CsrCachingEnable;
+ UINT32 LastCsrMcAddress[2];
+ UINT32 LastCsrMcMmioPhyAddr;
+ UINT8 CsrPciBarCachingEnable;
+ UINT32 LastCsrPciBarAddr[2];
+ UINT64 LastCsrPciBarPhyAddr;
+ UINT32 LastSBPortId[MAX_SOCKET];
+ UPI_CONNECTION_TYPE UpiConnectionType[MAX_SOCKET];
+ BOOLEAN PostedCsrAccessAllowed; // SW is allowed to use posted CSR writes method when TRUE
+ BOOLEAN PostedWritesEnabled; // All CSR writes use posted method when TRUE, non-posted when FALSE
+ BOOLEAN DataPopulated; // CPU_CSR_ACCESS_VAR is unavailable when FALSE
+ HPM_VSEC_RESOURCE SocketHpmVsecRes[MAX_SOCKET]; // HPM VSEC info for all sockets
+ BOOLEAN HbmSku;
+ UINT64 Cxl1p1Rcrb[MAX_SOCKET][MAX_IIO_STACK]; // CXL 1.1 RCRB, one per PI5 stack
+ UINT64 CxlRbBar[MAX_SOCKET][MAX_IIO_STACK]; // CXL RBBAR, one per PI5 stack
+ UINT32 DmiRcrb[MAX_SOCKET]; // DMI RCRB region, one per socket
+ UINT8 FabricType; //Compute die 10x6, 10x5, and 6x5 type is stored
+ UINT8 ChopType; //Compute Die Chop Type
+ UINT8 MdfInstCount;
+ UINT32 UboxMmioSize;
+ UINT32 UboxScfMmioSize;
+ UINT64 PpinValue[MAX_SOCKET]; // The Protected Processor Inventory Number from CPU MSRs
+ UINT32 OobMsmPciBaseAddress[MAX_SOCKET];
+ UINT32 S3mControlRegisterBaseAddress[MAX_SOCKET];
+} CPU_CSR_ACCESS_VAR;
+
+typedef struct {
+ UINT32 MeRequestedSizeNv;
+ UINT32 MeRequestedAlignmentNv;
+ UINT8 SbspSocketIdNv;
+} SYS_INFO_VAR_NVRAM;
+
+typedef struct _CPUID_REGISTER_INFO {
+ UINT32 Eax;
+ UINT32 Ebx;
+ UINT32 Ecx;
+ UINT32 Edx;
+} CPUID_REGISTER_INFO;
+
+typedef struct _PROCESSOR_COMMON_INFO {
+ UINT32 capid0;
+ UINT32 capid1;
+ UINT32 capid2;
+ UINT32 capid3;
+ UINT32 capid4;
+ UINT32 capid5;
+ UINT32 capid6lo;
+ UINT32 capid6hi;
+ CPUID_REGISTER_INFO ExtCpuid7;
+ CPUID_REGISTER_INFO ExtCpuid1B;
+} PROCESSOR_COMMON_INFO;
+
+typedef struct {
+ UINT32 MeRequestedSize;
+ UINT32 MeRequestedAlignment;
+ UINT32 CheckPoint;
+ UINT8 ResetRequired;
+ UINT8 Emulation;
+ BOOT_MODE SysBootMode;
+ CPU_CSR_ACCESS_VAR CpuCsrAccessVarHost; // Common resource for CsrAccessRoutines
+ UINT64 CpuFreq;
+ UINT8 SocketId;
+ SYS_INFO_VAR_NVRAM SysInfoVarNvram;
+ BOOLEAN UsraTraceControl;
+ UINT16 UsraTraceConfiguration; // Bit 7 6 5 4 3:0
+ // Write, Modify, GetAddr, Long/Short, Trace 0x5 as signature
+ // Bit 15 14:11 10 9 8
+ // DumpCpuCsrAccessVar, TBD, CSR, PCIE, Read
+ BOOLEAN CpuCsrAccessVarInfoDumped;
+ PROCESSOR_COMMON_INFO ProcessorCommonInfo[MAX_SOCKET];
+ EFI_PHYSICAL_ADDRESS SocAddrMapData;
+ UINTN UsraPpiPtr;
+} SYSTEM_INFO_VAR;
+
+
+#pragma pack ()
+
+#endif //#ifndef _SYSTEM_INFO_HOB_H_
diff --git a/BirchStreamFspBinPkg/sp/Fsp.fd b/BirchStreamFspBinPkg/sp/Fsp.fd
new file mode 100644
index 0000000..8377f49
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Fsp.fd
Binary files differ
diff --git a/BirchStreamFspBinPkg/sp/Include/CxlNodeHob.h b/BirchStreamFspBinPkg/sp/Include/CxlNodeHob.h
new file mode 100644
index 0000000..5f6afc2
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/CxlNodeHob.h
@@ -0,0 +1,102 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _CXL_NODE_HOB_
+#define _CXL_NODE_HOB_
+
+#define CXL_NODE_HOB_GUID { 0xdd8ae009, 0xda5a, 0x44a3, { 0xbe, 0x18, 0xda, 0x0c, 0x16, 0xc5, 0xaf, 0x5c } }
+
+#ifndef MAX_IIO_STACK
+#define MAX_IIO_STACK 16
+#endif
+
+#ifndef MAX_CXL_HDM_RANGES
+#define MAX_CXL_HDM_RANGES 0x2 // Maximum number of CXL HDM ranges per CXL end device.
+#endif
+
+#ifndef MAX_CXL_PER_SOCKET
+#define MAX_CXL_PER_SOCKET MAX_IIO_STACK
+#endif
+
+#define CXL_NODE_ATTR_MEM BIT0
+#define CXL_NODE_ATTR_PERSISTENT BIT1
+#define CXL_NODE_ATTR_MEM_HW_INIT BIT2
+#define CXL_NODE_ATTR_ACCELERATOR BIT3
+#define CXL_NODE_ATTR_HOT_PLUGGABLE BIT4
+
+typedef UINT32 CXL_NODE_ATTR;
+
+#pragma pack(1)
+
+//
+// CDAT DSEMTS EFI Memory Type and Attribute
+//
+typedef enum {
+ CxlEfiConventionalMemory = 0x0,
+ CxlEfiConventionalMemorySp = 0x1,
+ CxlEfiReservedMemoryType = 0x2,
+ MaxCxlEfiMemType
+} CXL_EFI_MEM_TYPE;
+
+typedef struct {
+ UINT32 RdLatency;
+ UINT32 WrLatency;
+ UINT32 RdBandwidth;
+ UINT32 WrBandwidth;
+} CXL_PERF_DATA;
+
+typedef struct {
+ UINT64 SerialNumber;
+ UINT16 VendorId;
+ CXL_NODE_ATTR Attr;
+ UINT32 Address;
+ UINT32 Size;
+ UINT8 Ways;
+ UINT8 SocketBitmap;
+ BOOLEAN AcpiSratSpMemFlag;
+ CXL_EFI_MEM_TYPE EfiMemType;
+ CXL_PERF_DATA InitiatorPerfData; // Performance data between device egress and initiator.
+ CXL_PERF_DATA TargetPerfData; // Performance data of entire target memory region.
+ CXL_PERF_DATA InitiatorTargetPerfData; // performance data between initiator and the device memory.
+} CXL_NODE_INFO;
+
+typedef struct {
+ UINT8 CxlNodeCount;
+ //
+ // CXL node info for UEFI memory map and ACPI tables construction
+ //
+ CXL_NODE_INFO CxlNodeInfo[MAX_IIO_STACK * MAX_CXL_HDM_RANGES];
+} CXL_NODE_SOCKET;
+
+#pragma pack()
+
+#endif //#ifndef _CXL_NODE_HOB_
diff --git a/BirchStreamFspBinPkg/sp/Include/FspAcpiHobs.h b/BirchStreamFspBinPkg/sp/Include/FspAcpiHobs.h
new file mode 100644
index 0000000..7150e5e
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/FspAcpiHobs.h
@@ -0,0 +1,53 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSP_ACPI_HOBS__
+#define __FSP_ACPI_HOBS__
+
+//Typecast HOB pointer to APEI table structure of ACPI version 6.2
+#define FSP_RAS_ACPI_HOB_GUID { 0x826785ee, 0xa8e0, 0x4d8f, { 0x82, 0x6f, 0x54, 0x29, 0x2c, 0xe7, 0x6f, 0xe6 } }
+
+//Typecast HOB pointer to ACPI CXL CEDT table structure
+#define FSP_CXL_CEDT_ACPI_HOB_GUID { 0x5CB7A12A, 0x8B2D, 0x485A, { 0xB7, 0x04, 0xC0, 0x52, 0x49, 0x56, 0x81, 0xE7 } }
+
+// Typecast HOB pointer to MEM_TRAINING_DATA_HOB_HEADER.
+// User with NDA clearance should refer to RC code for latest structure definition.
+#define FSP_MEM_TRAINING_DATA_HOB_GUID { 0x7e8b89e2, 0x8b84, 0x4cb3, { 0x86, 0x8f, 0x10, 0xb6, 0x78, 0x71, 0xa2, 0xc0 }}
+
+// Typecast HOB pointer to EWL_PRIVATE_DATA.
+// User with NDA clearance should refer to RC code for latest structure definition.
+#define FSP_EWL_ID_HOB_GUID { 0xd8e05800, 0x5e, 0x4462, { 0xaa, 0x3d, 0x9c, 0x6b, 0x47, 0x4, 0x92, 0xb } };
+
+//Typecast HOB pointer to RAS_ACPI_PARAM_HOB_DATA;
+#define RAS_ACPI_PARAM_HOB_GUID {0x594dfe5c, 0x7a87, 0x49dc, { 0x8f, 0x33, 0xea, 0x83, 0x4d, 0x6f, 0x18, 0x90 } }
+
+#endif // __FSP_ACPI_HOBS__
diff --git a/BirchStreamFspBinPkg/sp/Include/FspEdpcParam.h b/BirchStreamFspBinPkg/sp/Include/FspEdpcParam.h
new file mode 100644
index 0000000..ce694e9
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/FspEdpcParam.h
@@ -0,0 +1,71 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSP_EDPC_PARAM__
+#define __FSP_EDPC_PARAM__
+
+#pragma pack(1)
+typedef struct {
+ UINT8 Segment;
+ UINT8 Bus;
+ UINT8 Device;
+ UINT8 Function;
+} EDPC_DEV_INFO;
+
+typedef struct {
+ //
+ // There are three possible statuses of Valid infomation
+ // EPDC_INFO_VALID, EDPC_INFO_NOTIFIED, EDPC_INFO_CLEARED
+ //
+ UINT8 Valid;
+ EDPC_DEV_INFO EdpcTrigger;
+ EDPC_DEV_INFO EdpcRootPort;
+ UINT8 NotifyType;
+} EDPC_INFO;
+
+typedef struct {
+ UINT16 OsNativeAerSupport;
+ UINT16 Reserved;
+ UINT64 Reserved1[400];
+ EDPC_INFO EdpcInfo;
+ UINT64 EmcaL1DirAddr;
+ UINT8 EmcaEn;
+ UINT8 ElogEn;
+ UINT8 WheaEnabled;
+ UINT8 WheaSupportEn;
+ UINT64 ReadAckAddress;
+ UINT64 OobReadAckAddress;
+ UINT32 SoftwareSmi;
+} RAS_ACPI_PARAM;
+
+#pragma pack()
+#endif // __FSP_EDPC_PARAM__
diff --git a/BirchStreamFspBinPkg/sp/Include/FspErrorInfoHob.h b/BirchStreamFspBinPkg/sp/Include/FspErrorInfoHob.h
new file mode 100644
index 0000000..6b418c5
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/FspErrorInfoHob.h
@@ -0,0 +1,87 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _FSP_ERROR_INFO_HOB_H_
+#define _FSP_ERROR_INFO_HOB_H_
+
+///
+/// GUID value indicating the FSP error information.
+///
+#define FSP_ERROR_INFO_HOB_GUID { 0x611e6a88, 0xadb7, 0x4301, { 0x93, 0xff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6 } }
+
+#define FSP_ERROR_INFO_STATUS_CODE_TYPE (EFI_ERROR_CODE | EFI_ERROR_UNRECOVERED)
+///
+/// FSP Error Information Block.
+///
+#pragma pack(1)
+typedef struct {
+ ///
+ /// GUID HOB header.
+ ///
+ EFI_HOB_GUID_TYPE GuidHob;
+
+ ///
+ /// ReportStatusCode () type identifier.
+ ///
+ EFI_STATUS_CODE_TYPE Type;
+
+ ///
+ /// ReportStatusCode () value.
+ ///
+ EFI_STATUS_CODE_VALUE Value;
+
+ ///
+ /// ReportStatusCode () Instance number.
+ ///
+ UINT32 Instance;
+
+ ///
+ /// Optional GUID which may be used to identify
+ /// which internal component of the FSP was
+ /// executing at the time of the error.
+ ///
+ EFI_GUID CallerId;
+
+ ///
+ /// GUID identifying the nature of the fatal error.
+ ///
+ EFI_GUID ErrorType;
+
+ ///
+ /// EFI_STATUS code describing the error encountered.
+ ///
+ UINT32 Status;
+} FSP_ERROR_INFO_HOB;
+
+#pragma pack()
+
+#endif //_FSP_ERROR_INFO_H_
diff --git a/BirchStreamFspBinPkg/sp/Include/FspExtMemoryPprHob.h b/BirchStreamFspBinPkg/sp/Include/FspExtMemoryPprHob.h
new file mode 100644
index 0000000..97e3710
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/FspExtMemoryPprHob.h
@@ -0,0 +1,70 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _FSP_EXT_MEMORY_PPR_HOB_H_
+#define _FSP_EXT_MEMORY_PPR_HOB_H_
+
+#include "FspGlobals.h"
+
+#define FSP_EXT_MEMORY_PPR_HOB_GUID { 0x3956C6DA, 0x35B6, 0x4036, { 0x93, 0xE4, 0xB1, 0x51, 0x38, 0x60, 0x21, 0x1E } }
+
+#pragma pack(1)
+
+typedef struct FspExtPprAddr {
+ UINT8 Status;
+ UINT8 ErrorType;
+ UINT8 Socket;
+ UINT8 MemoryController;
+ UINT8 Channel;
+ UINT8 Dimm;
+ UINT8 Bank;
+ UINT32 Row;
+ UINT8 Rank;
+} FSP_EXT_PPR_ADDR;
+
+typedef struct FspExtPprDdrInfo {
+ UINT8 Count;
+ FSP_EXT_PPR_ADDR PprAddresses[FSP_MAX_PPR_ADDR_ENTRIES_DDR];
+} FSP_EXT_DDR_PPR_INFO;
+
+typedef struct FspExtMemoryPprData {
+ FSP_EXT_DDR_PPR_INFO DdrPprInfo;
+} FSP_EXT_MEMORY_PPR_DATA;
+
+typedef struct FspExtMemoryPprHob {
+ FSP_EXT_HEADER Header;
+ FSP_EXT_MEMORY_PPR_DATA Data;
+} FSP_EXT_MEMORY_PPR_HOB;
+
+#pragma pack()
+
+#endif // _FSP_EXT_MEMORY_PPR_HOB_H_
diff --git a/BirchStreamFspBinPkg/sp/Include/FspExtSystemMemoryMapHob.h b/BirchStreamFspBinPkg/sp/Include/FspExtSystemMemoryMapHob.h
new file mode 100644
index 0000000..066015e
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/FspExtSystemMemoryMapHob.h
@@ -0,0 +1,161 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
+#define _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
+
+#include "FspGlobals.h"
+
+#define FSP_EXT_SYSTEM_MEMORY_MAP_HOB_GUID { 0xDF310DE8, 0x579F, 0x419C, { 0xB6, 0xAB, 0x4D, 0x4B, 0xE7, 0xCA, 0xB0, 0x83 } }
+
+#pragma pack(1)
+
+typedef struct FspDimmDevice {
+ UINT8 Present;
+ BOOLEAN Enabled;
+ UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
+ UINT8 NumRanks; // Number of ranks on dimm
+ UINT8 NumPackageRanks; // Number of Package ranks on dimm
+ // For DDR5 NumRanks and NumPackageRanks same
+ // For MRDIMM NumRanks and NumPackageRanks may differ
+ UINT8 ActKeyByte2; // Actual module type reported by SPD
+ UINT16 DimmSize;
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT8 SerialNumber[FSP_DIMM_MAX_SERIALNUMBER_LEN]; // Serial Number
+ UINT8 PartNumber[FSP_DIMM_MAX_PARTNUMBER_LEN]; // Part Number
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT16 FisVersion; // Firmware Interface Specification version
+ INT32 CommonTck;
+ UINT16 SpdRegVen; // Register Vendor ID in SPD
+ UINT8 DataWidth;
+} FSP_EXT_DIMM_DEVICE;
+
+typedef struct FspExtMemoryDimmDeviceInfo {
+ UINT8 Count;
+ FSP_EXT_DIMM_DEVICE Dimms[FSP_MAX_DIMM];
+} FSP_EXT_DIMM_DEVICE_INFO;
+
+typedef struct FspMemoryChannelDevice {
+ UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled
+ UINT8 Features; // Bit mask of features to enable or disable
+ UINT8 MaxDimm; // Number of DIMM
+ UINT8 ChFailed;
+ UINT8 NgnChFailed;
+ UINT8 Is4BitEccDimmPresent; // 4-bit Ecc dimm present indicator
+ UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+ UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+ FSP_EXT_DIMM_DEVICE_INFO DimmInfo;
+} FSP_EXT_MEMORY_CHANNEL_DEVICE;
+
+typedef struct FspMemoryController {
+ UINT8 ImcEnabled;
+ UINT32 MemSize;
+} FSP_EXT_MEMORY_CONTROLLER;
+
+typedef struct FspExtMemoryChannelDeviceInfo {
+ UINT8 Count;
+ FSP_EXT_MEMORY_CHANNEL_DEVICE Devices[FSP_MAX_CH];
+} FSP_EXT_MEMORY_CHANNEL_DEVICE_INFO;
+
+typedef struct FspExtMemoryControllerInfo {
+ UINT8 Count;
+ UINT8 NumChPerMC;
+ FSP_EXT_MEMORY_CONTROLLER MemControllers[FSP_MAX_IMC];
+} FSP_EXT_MEMORY_CONTROLLER_INFO;
+
+typedef struct FspMemoryMapSocket {
+ UINT8 SocketEnabled;
+ UINT32 IioStackBitmap;
+ UINT32 SktTotMemMapSPA; // Total memory mapped to SPA
+ FSP_EXT_MEMORY_CONTROLLER_INFO MemoryControllerInfo;
+ FSP_EXT_MEMORY_CHANNEL_DEVICE_INFO MemoryChannelDeviceInfo;
+} FSP_EXT_MEMORY_MAP_SOCKET;
+
+typedef struct FspExtMemMapSocketInfo {
+ UINT8 Count;
+ FSP_EXT_MEMORY_MAP_SOCKET Sockets[FSP_MAX_SOCKET];
+} FSP_EXT_MEMORY_MAP_SOCKET_INFO;
+
+typedef struct FspMemoryMapElement {
+ UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
+ UINT8 NodeId; // Node ID of the HA Owning the memory
+ UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
+ UINT8 ClusterId; // Logical cluster Id of SNC cluster - only 0 in UMA clustering and all2all
+ UINT32 BaseAddress; // Base Address of the element in 64MB chunks
+ UINT32 ElementSize; // Size of this memory element in 64MB chunks
+} FSP_EXT_MEMORY_MAP_ELEMENT;
+
+typedef struct FspExtMemMapElementInfo {
+ UINT8 Count;
+ FSP_EXT_MEMORY_MAP_ELEMENT Elements[FSP_MAX_MEMORY_MAP_ELEMENTS];
+} FSP_EXT_MEMORY_MAP_ELEMENT_INFO;
+
+typedef struct FspExtRasInfo {
+ UINT8 SystemRasType;
+ UINT8 RasModesEnabled; // RAS modes that are enabled
+ UINT16 ExRasModesEnabled; // Extended RAS modes that are enabled
+} FSP_EXT_RAS_INFO;
+
+typedef struct FspExtMemoryConfigurationInfo {
+ UINT32 LowMemBase; // Mem base in 64MB units for below 4GB mem.
+ UINT32 LowMemSize; // Mem size in 64MB units for below 4GB mem.
+ UINT32 HighMemBase; // Mem base in 64MB units for above 4GB mem.
+ UINT32 HighMemSize; // Mem size in 64MB units for above 4GB mem.
+ UINT32 MmiohBase; // MMIOH base in 64MB granularity
+ UINT32 MemSize; // Total physical memory size
+ UINT16 MemFreq;
+ UINT8 MemMode; // 0 - Independent, 1 - Lockstep
+ UINT8 VolMemMode; // 0 - 1LM, 1 - 2LM
+ UINT16 DramType;
+ UINT8 DdrVoltage; // Mem Frequency
+ UINT8 ErrorCorrectionType;
+} FSP_EXT_MEMORY_CONFIGURATION_INFO;
+
+typedef struct FspExtSystemMemoryMapData {
+ FSP_EXT_MEMORY_CONFIGURATION_INFO MemoryConfigurationInfo;
+ FSP_EXT_RAS_INFO RasInfo;
+ FSP_EXT_MEMORY_MAP_ELEMENT_INFO MemoryMapElementInfo;
+ FSP_EXT_MEMORY_MAP_SOCKET_INFO MemoryMapSocketInfo;
+} FSP_EXT_SYSTEM_MEMORY_MAP_DATA;
+
+typedef struct FspExtSystemMemoryMapDataHob{
+ FSP_EXT_HEADER Header;
+ FSP_EXT_SYSTEM_MEMORY_MAP_DATA Data;
+} FSP_EXT_SYSTEM_MEMORY_MAP_HOB;
+
+#pragma pack()
+
+#endif // _FSP_EXT_SYSTEM_MEMORY_MAP_HOB_H_
diff --git a/BirchStreamFspBinPkg/sp/Include/FspGlobals.h b/BirchStreamFspBinPkg/sp/Include/FspGlobals.h
new file mode 100644
index 0000000..c8df3ac
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/FspGlobals.h
@@ -0,0 +1,61 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _FSP_EXT_GLOBALS_
+#define _FSP_EXT_GLOBALS_
+
+#define FSP_MAX_SOCKET MAX_SOCKET
+#define FSP_MAX_IMC MAX_IMC
+#define FSP_MAX_MC_CH MAX_MC_CH
+#define FSP_MAX_DIMM MAX_DIMM
+#define FSP_DIMM_MAX_SERIALNUMBER_LEN NGN_MAX_SERIALNUMBER_STRLEN
+#define FSP_DIMM_MAX_PARTNUMBER_LEN NGN_MAX_PARTNUMBER_STRLEN
+#define FSP_MAX_CH ((FSP_MAX_IMC)*(FSP_MAX_MC_CH))
+#define FSP_MAX_MEMORY_MAP_ELEMENTS 150
+
+#define MEM_64MB_TO_BYTES(Size64M) ((UINT64)(Size64M) << 26)
+#define MEM_64MB_TO_KBYTES(Size64M) ((UINT64)(Size64M) << 16)
+#define MEM_64MB_TO_MBYTES(Size64M) ((UINT64)(Size64M) << 6)
+#define MEM_64MB_TO_GBYTES(Size64M) ((Size64M) >> 4)
+#define MEM_BYTES_TO_64MB(SizeB) ((SizeB) >> 26)
+#define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16)
+#define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6)
+
+#define FSP_MAX_PPR_ADDR_ENTRIES_DDR MAX_PPR_ADDR_ENTRIES_DDR
+
+typedef struct FspExtHeader {
+ UINT64 Magic;
+ UINT32 DataLength;
+ UINT32 CheckSum;
+} FSP_EXT_HEADER;
+
+#endif // _FSP_EXT_GLOBALS_
diff --git a/BirchStreamFspBinPkg/sp/Include/FspUpd.h b/BirchStreamFspBinPkg/sp/Include/FspUpd.h
new file mode 100644
index 0000000..cbee351
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/FspUpd.h
@@ -0,0 +1,50 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPD_H__
+#define __FSPUPD_H__
+
+#include <FspEas.h>
+
+#pragma pack(1)
+
+#define FSPT_UPD_SIGNATURE 0x545F445055524E47 /* 'GNRUPD_T' */
+
+#define FSPM_UPD_SIGNATURE 0x4D5F445055524E47 /* 'GNRUPD_M' */
+
+#define FSPS_UPD_SIGNATURE 0x535F445055524E47 /* 'GNRUPD_S' */
+
+#define FSPI_UPD_SIGNATURE 0x495F445055524E47 /* 'GNRUPD_I' */
+
+#pragma pack()
+
+#endif
diff --git a/BirchStreamFspBinPkg/sp/Include/FspmUpd.h b/BirchStreamFspBinPkg/sp/Include/FspmUpd.h
new file mode 100644
index 0000000..86c40eb
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/FspmUpd.h
@@ -0,0 +1,1866 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPM_UPD_H__
+#define __FSPM_UPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+typedef struct {
+
+/** Customer Revision
+ The Customer can set this revision string for their own purpose.
+**/
+ UINT8 CustomerRevision[32];
+
+/** Bus Ratio
+ Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO
+**/
+ UINT8 BusRatio[8];
+
+/** Legacy VGA Soc
+ Socket that claims the legacy VGA range
+**/
+ UINT8 LegacyVgaSoc;
+
+/** Legacy VGA Stack
+ Stack that claims the legacy VGA range
+**/
+ UINT8 LegacyVgaStack;
+
+/** Pcie P2P Performance Mode
+ Determine if to enable PCIe P2P Performance Mode
+ $EN_DIS
+**/
+ UINT8 P2pRelaxedOrdering;
+
+/** UPI Debug Print Level
+ UPI Debug Print Level Bitmask. 0- Disable, 1- Fatal, 2- Warning, 4- Summary, 8-
+ Detail, <b>0xF- All(Default)</b>
+ 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All
+**/
+ UINT8 DebugPrintLevel;
+
+/** NumaEn
+ Enable or Disable Numa
+ $EN_DIS
+**/
+ UINT8 NumaEn;
+
+/** SNC Enable
+ Enable or Disable SNC
+ 0x0:Disable, 0x1:Enable, 0x0F:Auto
+**/
+ UINT8 SncEn;
+
+/** IODC Mode
+ IODC Mode. 0- Disable, <b>1- Auto(Default)</b>, 2- Push, 3- AllocFlow, 4- NonAlloc, 5- WCILF
+ 0:Disable, 1:Auto, 2:Push, 3:AllocFlow, 4:NonAlloc, 5:WCILF
+**/
+ UINT8 IoDcMode;
+
+/** Degrade Precedence
+ Setup Degrade Precedence
+ 0:Topology, 1:Feature
+**/
+ UINT8 DegradePrecedence;
+
+/** Degrade 4 Socket Preference
+ Setup Degrade 4 Socket Preference
+ 0:Fully Connect, 1:Dual Link Ring
+**/
+ UINT8 Degrade4SPreference;
+
+/** Directory Mode
+ Enable or Disable Directory Mode
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 DirectoryModeEn;
+
+/** XPT Prefetch Enable
+ Enable or Disable XPT Prefetch
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 XptPrefetchEn;
+
+/** KTI Prefetch Enable
+ Enable or Disable KTI Prefetch
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 KtiPrefetchEn;
+
+/** XPT Remote Prefetch Enable
+ Enable or Disable XPT Remote Prefetch Enable
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 XptRemotePrefetchEn;
+
+/** Distress QoS Mode
+ Distress QoS. <b>0- Mode 0(Default)</b>, 2- Mode 2
+ 0:Mode 0, 2:Mode 2
+**/
+ UINT8 DistressQoS;
+
+/** KTI Link Speed Mode
+ Choose KTI Link Speed Mode
+ 0:Slow, 1:Full
+**/
+ UINT8 KtiLinkSpeedMode;
+
+/** KTI Link Speed
+ Setup KTI Link Speed - 2- 160GT, 3- 200GT, 4- 240GT, <b>0x7F- Max KTI Link Speed
+ (Default)</b>, 0x8F- Frequency Per Link
+ 2:160GT, 3:200GT, 4:240GT, 0x7F:Max KTI Link Speed, 0x8F:Frequency Per Link
+**/
+ UINT8 KtiLinkSpeed;
+
+/** KTI Link L0p
+ Enable or Disable KTI Link L0p
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 KtiLinkL0pEn;
+
+/** KTI Link L1
+ Enable or Disable KTI Link L1
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 KtiLinkL1En;
+
+/** Kti Link Speed Per Port
+ Setup KTI Link Speed to be allocated for each port, 2:160GT, 2:200GT, 3:240GT, 0X7f:Max
+ KTI Link Speed
+**/
+ UINT8 KtiLinkSpeedPerPort[48];
+
+/** DfxL0p Enable
+ Indicates the DfxL0p Enable to be allocated for each port, 0:Disable, 1:Enable
+**/
+ UINT8 DfxL0pEnable[48];
+
+/** DfxL1 Enable
+ Indicates the DfxL1 Enable to be allocated for each port, 0:Disable, 1:Enable
+**/
+ UINT8 DfxL1Enable[48];
+
+/** KTI Failover
+ Enable or Disable KTI Failover
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 KtiFailoverEn;
+
+/** KTI CRC Mode
+ Select KTI CRC Mode
+ 0:16bit, 1:32bit, 2:Auto
+**/
+ UINT8 KtiCrcMode;
+
+/** KTI CPU Socket Hotplug
+ Enable or Disable KTI CPU Socket Hotplug
+ $EN_DIS
+**/
+ UINT8 KtiCpuSktHotPlugEn;
+
+/** KTI CPU Socket HotPlug Topology
+ Select KTI CPU Socket HotPlug Topology
+ 0:4Socket, 1:8Socket
+**/
+ UINT8 KtiCpuSktHotPlugTopology;
+
+/** KTI SKU Mismatch Check
+ Enable or Disable KTI SKU Mismatch Check
+ $EN_DIS
+**/
+ UINT8 KtiSkuMismatchCheck;
+
+/** Sdsi Contrl Ib Lock
+ Enable or Disable Sdsi Contrl Ib Lock
+ $EN_DIS
+**/
+ UINT8 SdsiCtrlIbLock;
+
+/** TOR Threshold - Loctorem threshold Normal
+ Select TOR Threshold - Loctorem threshold Normal
+ 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
+**/
+ UINT8 TorThresLoctoremNorm;
+
+/** TOR threshold - Loctorem threshold empty
+ Select TOR threshold - Loctorem threshold empty
+ 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High
+**/
+ UINT8 TorThresLoctoremEmpty;
+
+/** HA A to S directory optimization
+ Enable or Disable HA A to S directory optimization
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 StaleAtoSOptEn;
+
+/** LLC Deadline Allocation
+ Enable or Disable LLC Deadline Allocation
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 LLCDeadLineAlloc;
+
+/** MBA BW Calibration Profiles
+ Choice of MBA BW throttling curve
+ 0:Linear BW shaping, 1:Biased BW shaping, 2:Legacy BW shaping, 3:Auto
+**/
+ UINT8 MbeBWCalChoice;
+
+/** PMM MBA BW downscale
+ PMM BW downscaling vs the baseline Total memory BW profile. Eg- picking 1/2x results
+ in scaling PMM BW throttling in a 2:1 ratio vs. DDR throttling.
+ 0:PMM BW throttling in a 1/1 ratio vs. DDR throttling, 1:2/1 ratio, 2:4/1 ratio,
+ 3:8/1 ratio
+**/
+ UINT8 PmmMbaBWDownscale;
+
+/** CXL (Type3) MBA BW downscale
+ CXL (Type3) BW downscaling vs the baseline Total memory BW profile. Eg- picking
+ 1/2x results in scaling CXL (Type3) BW throttling in a 2:1 ratio vs. DDR throttling.
+ 0:CXL BW throttling in a 1/1 ratio vs. DDR throttling, 1:2/1 ratio, 2:4/1 ratio,
+ 3:8/1 ratio
+**/
+ UINT8 CxlMbaBWDownscale;
+
+/** Remote Target MBA BW downscale
+ Remote Target BW downscaling vs the baseline Total memory BW profile. Eg- picking
+ 1/2x results in scaling Remote Target BW throttling in a 2:1 ratio vs. DDR throttling.
+ 0:Remote Target BW throttling in a 1/1 ratio vs. DDR throttling, 1:2/1 ratio, 2:4/1
+ ratio, 3:8/1 ratio
+**/
+ UINT8 RemoteTargetMbaBWDownscale;
+
+/** Split Lock
+ Enable or Disable Split Lock
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 SplitLock;
+
+/** MMCFG Base Address
+ Setup MMCFG Base Address
+ 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 0xFF:Auto
+**/
+ UINT32 mmCfgBase;
+
+/** MMCFG Size
+ Select MMCFG Size
+ 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 0xFF:Auto
+**/
+ UINT32 mmCfgSize;
+
+/** MMIO High Base Address
+ MMIO High Base Address
+ 0:56T, 1:40T, 2:32T, 3:24T, 4:16T, 5:4T, 6:2T, 7:1T, 8:512G, 9:3584T, 10:30T, 11:60T,
+ 12:88T, 13:120T, 14:248T, 255:AUTO
+**/
+ UINT32 mmiohBase;
+
+/** CPU Physical Address Limit
+ CPU Physical Address Limit
+ $EN_DIS
+**/
+ UINT8 CpuPaLimit;
+
+/** MMIO High Size
+ MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space per CPU.
+ 0:1GB, 1:4GB, 2:16GB, 3:64GB, 4:256GB, 5:1024GB, 6:32GB, 255:AUTO
+**/
+ UINT32 mmiohSize;
+
+/** DCA
+ Enable or Disable DCA
+ $EN_DIS
+**/
+ UINT8 dcaEn;
+
+/** BoardTypeBitmask
+ BoardTypeBitmask
+**/
+ UINT32 BoardTypeBitmask;
+
+/** S3mClkSetupPtr
+ Pointer to clk setup variable data
+**/
+ UINT64 S3mClkSetupPtr;
+
+/** AllLanesPtr
+ Pointer to array of ALL_LANES_EPARAM_LINK_INFO
+**/
+ UINT64 AllLanesPtr;
+
+/** PerLanePtr
+ Pointer to array of PER_LANE_EPARAM_LINK_INFO
+**/
+ UINT64 PerLanePtr;
+
+/** AllLanesSizeOfTable
+ Number of elements in AllLanesPtr array.
+**/
+ UINT32 AllLanesSizeOfTable;
+
+/** PerLaneSizeOfTable
+ Number of elements in PerLanePtr array.
+**/
+ UINT32 PerLaneSizeOfTable;
+
+/** WaitTimeForPSBP
+ Enable or Disable WaitTimeForPSBP
+**/
+ UINT32 WaitTimeForPSBP;
+
+/** KtiInEnableMktme
+ Enable or Disable KtiInEnableMktme
+ $EN_DIS
+**/
+ UINT8 KtiInEnableMktme;
+
+/** HIOP STACK DISABLE
+ Enables/Disables given HIOP STACK. Default is AUTO no stack is disabled. 1 - The
+ stacks indicated by the bit locations are disabled. 0 - The stacks indicated by
+ the bit locations are not modified. The stack order is abstracted each bit 0 =
+ stack 0 ... bit n = stack n. The bit setting for each stack can be overriden by
+ BIOS based on part-knob compatibility. The array size must be MAX_SOCKET(Maximum:8) x UINT32.
+**/
+ UINT32 StackDisableBitMap[8];
+
+/** Processor VmxEnable Function
+ Enable(Default) or Disable Processor VmxEnable Function
+ $EN_DIS
+**/
+ UINT8 VmxEnable;
+
+/** Smm Relocation
+ Enable(Default)/Disable Smm Relocation
+ $EN_DIS
+**/
+ UINT8 SmmRelocationEnable;
+
+/** Processor HyperThreading Function
+ Enables Logical processor, 0- ALL LPs, 1- Single LP, 2- Two LPs
+ 0:ALL LPs, 1:Single LP, 2:Two LPs
+**/
+ UINT8 ProcessorLpEnable;
+
+/** Processor Safer Mode Extensions Function
+ Enable or Disable(Default) Processor Safer Mode Extensions Function
+ $EN_DIS
+**/
+ UINT8 ProcessorSmxEnable;
+
+/** Uncore Freq Control Compute
+ Mode 0: Power Limited Ordered Throttling Mode 1: Power Limited Proportional Throttling
+ 0:Mode 0, 1:Mode 1
+**/
+ UINT8 UncoreFreqCtrl;
+
+/** Uncore Freq Ratio Compute
+ 0: Set dynamic Uncore frequency range from max and min fused values. Otherwise Uncore
+ will run at a constant frequency ratio, the UFS algorithm will be disabled, but
+ physical limits may still reduce frequency. NOTE: The user input will be clipped
+ to the range accordingly during boot.
+**/
+ UINT8 UncoreFreqRatio;
+
+/** Uncore Freq Control IO
+ Mode 0: Power Limited Ordered Throttling Mode 1: Power Limited Proportional Throttling
+ 0:Mode 0, 1:Mode 1
+**/
+ UINT8 UncoreFreqCtrlIo;
+
+/** Uncore Freq Ratio IO
+ 0: Set dynamic Uncore frequency range from max and min fused values. Otherwise Uncore
+ will run at a constant frequency ratio, the UFS algorithm will be disabled, but
+ physical limits may still reduce frequency. NOTE: The user input will be clipped
+ to the range accordingly during boot.
+**/
+ UINT8 UncoreFreqRatioIo;
+
+/** DDR frequency limit
+ Select DDR frequency limit, <b>0x00- Auto(Default)</b>, 0x01:DDR_3200, 0x03:DDR_3600,
+ 0x05:DDR_4000, 0x07:DDR_4400, 0x08:DDR_4800, 0x09:DDR_5200, 0x0A:DDR_5600, 0x0B:DDR_6000,
+ 0x0C:DDR_6400
+**/
+ UINT8 HostDdrFreqLimit;
+
+/** DDR Over Clock Enable
+ DDR Over Clock Enable, 0- Disable, 1- Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 DdrOverClockEnable;
+
+/** Advanced Debug Function
+ Select Advanced Debug Function, 0- Disable, 1- Enable, 2- Auto
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 DfxAdvDebugJumper;
+
+/** Memory Serial Debug Message Level
+ Select Memory Serial Debug Message Level, 0- Disable, 1- Minimum, 2- Normal, 3-
+ Maximum, <b>4- Auto(Default)</b>, 5- Fixed PCD
+ 0:Disable, 1:Minimum, 2:Normal, 3:Maximum, 4:Auto, 5:Fixed PCD
+**/
+ UINT8 serialDebugMsgLvl;
+
+/** IIO IioPE0Bifurcation
+ IioPE0Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPE0Bifurcation[8];
+
+/** IIO IioPE1Bifurcation
+ IioPE1Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPE1Bifurcation[8];
+
+/** IIO IioPE2Bifurcation
+ IioPE2Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPE2Bifurcation[8];
+
+/** IIO IioPE3Bifurcation
+ IioPE3Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPE3Bifurcation[8];
+
+/** IIO IioPE4Bifurcation
+ IioPE4Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPE4Bifurcation[8];
+
+/** IIO IioPE5Bifurcation
+ IioPE5Bifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPE5Bifurcation[8];
+
+/** IIO IioPEaBifurcation
+ IioPEaBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPEaBifurcation[8];
+
+/** IIO IioPEbBifurcation
+ IioPEbBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPEbBifurcation[8];
+
+/** IIO IioPEcBifurcation
+ IioPEcBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPEcBifurcation[8];
+
+/** IIO IioPEdBifurcation
+ IioPEdBifurcation[MAX_SOCKET]- MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4,
+ 0x03:xxx8xxx8, 0x04:xxxxxx16, <b>0xFF:AUTO(Default)</b>
+**/
+ UINT8 IioPEdBifurcation[8];
+
+/** Toggle Msi Bypass
+ Msi Bypass: 0- Disable, 1- Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 CtrlMsiBypassEn;
+
+/** IIO Msi Bypass Enabled Ptr
+ Pointer to array of Msi Bypass Enabled settings Per Stack
+**/
+ UINT32 IioMsiBypassEnabledPtr;
+
+/** IIO Msi Bypass Enabled entry Number
+ Number of elements in IioMsiBypassEnabledPtr array, stack number as unit.
+**/
+ UINT32 IioMsiBypassEnabledNumber;
+
+/** IIO PCIE MaxPayload Ptr
+ Pointer to array of PCIE MaxPayload settings Per Port
+**/
+ UINT32 IioPcieMaxPayloadPtr;
+
+/** IIO PCIE MaxPayload entry Number
+ Number of elements in PcieMaxPayloadPtr array, port number as unit.
+**/
+ UINT32 IioPcieMaxPayloadNumber;
+
+/** IIO Board settings Hob Ptr
+ Pointer to array of IIO_BOARD_SETTINGS_HOB
+**/
+ UINT32 IioBoardSettingsHobPtr;
+
+/** IIO Board Settings Hob length
+ The IIO Board Settings Hob Length.
+**/
+ UINT32 IioBoardSettingsHobLength;
+
+/** Iio Setup Knobs pointer
+ : Iio Setup Knobs pointer
+**/
+ UINT64 IioSetupKnobsPtr;
+
+/** Iio Setup Knobs Size
+ : Iio Setup Knobs Size
+**/
+ UINT64 IioSetupKnobsSize;
+
+/** Iio SocketConfig Setup Knobs pointer
+ : Iio SocketConfig Setup Knobs pointer
+**/
+ UINT64 IioSocketConfigSetupKnobsPtr;
+
+/** Iio SocketConfig Setup Knobs Size
+ : Iio SocketConfig Setup Knobs Size
+**/
+ UINT64 IioSocketConfigSetupKnobsSize;
+
+/** IIO DeEmphasis Array Ptr
+ Pointer to array of DeEmphasis
+**/
+ UINT32 DeEmphasisPtr;
+
+/** IIO DeEmphasis Array Number
+ Number of elements in DeEmphasis array.
+**/
+ UINT32 DeEmphasisNumber;
+
+/** IIO PCIe Common Clock Array Ptr
+ Pointer to array of PCIe Common Clock
+**/
+ UINT32 PcieCommonClockPtr;
+
+/** IIO PCIe Common Clock Array Number
+ Number of elements in PCIe Common Clock array.
+**/
+ UINT32 PcieCommonClockNumber;
+
+/** IIO Cpm Enable Array Ptr
+ Pointer to array of Cpm Enable, which points to array Socket[MAX_SOCKET].Ioat[MAX_IIO_IOAT_PER_SOCKET].CpmEn
+**/
+ UINT32 IioCpmEnPtr;
+
+/** IIO Hqm Enable Array Ptr
+ Pointer to array of Hqm Enable, which points to array Socket[MAX_SOCKET].Ioat[MAX_IIO_IOAT_PER_SOCKET].HqmEn
+**/
+ UINT32 IioHqmEnPtr;
+
+/** Gen5LinkDegradation
+ Enable or disable Gen5 link degradation.
+ 0:Disable, 1:Enable
+**/
+ UINT8 Gen5LinkDegradation;
+
+/** PcieHotPlugEnable
+ Enable or disable Pcie hot plug enable feature
+ 0:Disable, 1:Enable
+**/
+ UINT8 PcieHotPlugEnable;
+
+/** DelayAfterPCIeLinkTraining
+ Custom delay after PCI-E link training on IIO ports
+**/
+ UINT16 DelayAfterPCIeLinkTraining;
+
+/** MSR Lock Control
+ Enable - MSR 3Ah and CSR 80h will be locked in FSP. Power Good reset is needed to
+ remove lock bits
+ 0:Disable, 1:Enable
+**/
+ UINT8 ProcessorMsrLockControl;
+
+/** Lock Chipset
+ Lock or Unlock chipset in FSP
+ 0:Disable, 1:Enable
+**/
+ UINT8 LockChipset;
+
+/** DFX Ev Mode
+ When Enabled, Expose IIO DFX devices and other CPU devices like PMON in FSP
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 DfxEvMode;
+
+/** DFX Disable Bios Done
+ When Enabled, suppresses notifying processor via MSR 151h that boot initialization
+ is finished in FSP
+ 0:Disable, 1:Enable
+**/
+ UINT8 DfxDisableBiosDone;
+
+/** PciBusResConfigPtr
+ Pointer to array of socket PCI bus resource.
+**/
+ UINT32 PciBusResConfigPtr;
+
+/** PciBaseLimitsResConfigPtr
+ Pointer to array of socket PCI IO/MMIO resource.
+**/
+ UINT32 PciBaseLimitsResConfigPtr;
+
+/** PCH PCIE PLL Ssc
+**/
+ UINT8 PchPciePllSsc;
+
+/** PchDciEn
+ Enable or <b>Disable(Default)</b> PCH DCI
+ 0:Disable, 1:Enable
+**/
+ UINT8 PchDciEn;
+
+/** MeUmaEnable
+ Enable or disable ME UMA feature
+ 0:Disable, 1:Enable
+**/
+ UINT8 MeUmaEnable;
+
+/** SerialIoUartDebugEnable
+ <b>Enable(Default)</b> or Disable SerialIo Uart debug library in FSP.
+ 0:Disable, 1:Enable
+**/
+ UINT8 SerialIoUartDebugEnable;
+
+/** ISA Serial Base selection
+ Select ISA Serial Base address could be initialized by boot loader. Default is 0x3F8
+ 0x2F8:0x2F8, 0x3F8:0x3F8
+**/
+ UINT16 SerialIoUartDebugIoBase;
+
+/** promoteMrcWarnings
+ Determines if MRC warnings are promoted to system level in FSP.
+ $EN_DIS
+**/
+ UINT8 promoteMrcWarnings;
+
+/** promoteWarnings
+ Determines if warnings are promoted to system level in FSP.
+ $EN_DIS
+**/
+ UINT8 promoteWarnings;
+
+/** serialDebugMsgLvlTrainResults
+ Enabled = set to display the training results. Training results also get displayed
+ if debug messages is set to Maximum in FSP.
+ $EN_DIS
+**/
+ UINT8 serialDebugMsgLvlTrainResults;
+
+/** Enhanced Log Parsing
+ Enables additional output in debug log for easier machine parsing in FSP.
+ $EN_DIS
+**/
+ UINT8 logParsing;
+
+/** MemTest
+ Enable - Enables memory test during normal boot. Disable - Disables this feature in FSP.
+ $EN_DIS
+**/
+ UINT8 HwMemTest;
+
+/** MemTest Loops
+ Number of memory test loops during normal boot, set to 0 to run memtest infinitely in FSP.
+**/
+ UINT16 MemTestLoops;
+
+/** Adv MemTest Options
+ This option is a bit mask[19:0]- All 0 = disabled- bit-0=XMATS8, bit-1=XMATS16,
+ bit-2=Reserved, bit-3=Reserved, bit-4=WCMATS8, bit-5=WCMCH8, bit-6=Reserved, bit-7=MARCHCM64,
+ bit-8=Reserved, bit-9=Reserved, bit-10=Reserved, bit-11=TWR, bit-12=DATARET, bit-13=MATS8TC1,
+ bit-14=MATS8TC2, bit-15=MATS8TC3, bit-16=SK-HYNIX, bit-17=SAMSUNG, bit-18=MICRON-RMW,
+ bit-19=SCRAM_X2 in FSP.
+**/
+ UINT32 AdvMemTestOptions;
+
+/** SmartTestKey
+ Number of SmartTest Key
+**/
+ UINT32 SmartTestKey;
+
+/** Adv MemTest Pause
+ Specify a pause delay between 0 to 255 in units of msec. This is a time period where
+ refresh is disabled between write and read sequences in FSP.
+**/
+ UINT8 AdvMemTestCondPause;
+
+/** Adv MemTest tREFI
+ Specify tREFI (refresh rate) timing between 1850 to 7800 in nsec.
+**/
+ UINT16 AdvMemTestCondTrefi;
+
+/** Adv MemTest tWR
+ Specify tWR timing between 48 to 96 in units of tCK in FSP.
+**/
+ UINT8 AdvMemTestCondTwr;
+
+/** Adv MemTest PMIC VDD Level
+ Specify PMIC VDD level in units of mV in FSP.
+**/
+ UINT16 AdvMemTestCondPmicVdd;
+
+/** Adv MemTest Conditions
+ Auto = set test conditions based on test type; Manual = specify global test conditions;
+ Disable = Do not apply test conditions in FSP.
+ 0:Disable, 1:Auto, 2:Manual
+**/
+ UINT8 AdvMemTestCondition;
+
+/** Adv MemTest Reset Failure Tracking List
+ Enable/disable Reset of the Row Failure Tracking List after each Adv MemTest option.
+ Useful for testing performance of multiple options in FSP.
+ $EN_DIS
+**/
+ UINT8 AdvMemTestResetList;
+
+/** MemTest On Cold Fast Boot
+ Enable - Enables memory test during cold fast boot. Disable - Disables this feature in FSP.
+ $EN_DIS
+**/
+ UINT8 MemTestOnColdFastBoot;
+
+/** Attempt Fast Boot
+ Enable - Portions of memory reference code will be skipped when possible to increase
+ boot speed on warm boots. Disable - Disables this feature in FSP.
+ $EN_DIS
+**/
+ UINT8 AttemptFastBoot;
+
+/** MemTest On Cold Fast Boot
+ Enable - Enables memory test during cold fast boot. Disable - Disables this feature in FSP.
+ $EN_DIS
+**/
+ UINT8 AttemptFastBootCold;
+
+/** Multithreaded Memory Training
+ Selects the number of processor sockets to train in parallel. 0 - All sockets operate
+ in parallel. 1 - At any time only one socket is executing. 2 - At any time only
+ two socket are executing. 4 - At any time only four socket are executing in FSP.
+ 0:All Processor Sockets, 1:One Socket at a Time (No Multithreading), 2:Two Sockets
+ at a Time, 4:Four Sockets at a Time
+**/
+ UINT8 AllowedSocketsInParallel;
+
+/** Auto-Reset on mem Training Error
+ Enable/Disable Auto-Reset on mem Training Error in FSP.
+ $EN_DIS
+**/
+ UINT8 AutoResetOnMemErr;
+
+/** Rank Margin Tool
+ Enable/Disable two types of rank margin in FSP.
+ 0:Normal RMT & Turnaround RMT Disabled, 1:Normal RMT Enabled, 2:Turnaround RMT Enabled,
+ 3:Normal RMT & Turnaround RMT Enabled, 4:Auto RMT Enable/Disabled
+**/
+ UINT8 EnableRMT;
+
+/** RMT on Fast Cold Boot
+ Enable/Disable the Rank Margin Tool on a Fast Cold Boot in FSP.
+ $EN_DIS
+**/
+ UINT8 EnableRMTonFCB;
+
+/** Execute Jedecinit before RMT
+ Execute Jedecinit before Rank Margin Tool in FSP.
+ $EN_DIS
+**/
+ UINT8 JedecInitBeforeRMT;
+
+/** Backside Margining
+ Enable/Disable margin test on the register or buffer backside in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTBacksideMargining;
+
+/** CmdAll
+ Step size of CmdAll. Auto- 1. Supported values- 1,2,4,8 in FSP.
+ 1:1, 2:2, 4:4, 8:8
+**/
+ UINT8 RMTCmdAll;
+
+/** RMT Debug Messages
+ Enable/Disable the RMT debug messages in FSP.
+ 2:Disable, 5:Enable
+**/
+ UINT8 RMTDebugMessages;
+
+/** RMT Display Tables
+ Enable/Disable displaying results as tables in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTDisplayTables;
+
+/** RMT Loop Count
+ Exponential loop count for single rank test in FSP.
+**/
+ UINT8 RMTLoopCount;
+
+/** Test Signal Bit Mask For RMT
+ Test signal bit mask for RMT in FSP.
+**/
+ UINT32 TestSignalBitMaskRMT;
+
+/** RMT Per Bit Margining
+ Enable/Disable Per Bit Margining in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTPerBitMargining;
+
+/** RMT Per CA Lane Margining
+ Enable/Disable Per CA Lane Margining in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTPerCaLaneMargining;
+
+/** RMT Per CS Lane Margining
+ Enable/Disable Per CS Lane Margining in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTPerCsLaneMargining;
+
+/** RMT Display Plots
+ Enable/Disable the display of per-bit results as plots in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTPerDisplayPlots;
+
+/** RMT RxDqs
+ Step size of RxDqs. Auto- 1. Supported values- 1,2,4,8 in FSP.
+ 1:Auto, 2:2, 4:4, 8:8
+**/
+ UINT8 RMTRxDqs;
+
+/** RMT RxVref
+ Step size of RxVref. Auto- 1. Supported values- 1,2,4,8 in FSP.
+ 1:Auto, 2:2, 4:4, 8:8
+**/
+ UINT8 RMTRxVref;
+
+/** Dfx RMT Scrambler
+ Enable or Disable scrambler during RMT test in FSP.
+ $EN_DIS
+**/
+ UINT8 DfxScrambleEnRMT;
+
+/** RMT Step Size Override
+ Enable or Disable overriding the default step sizes in FSP.
+ $EN_DIS
+**/
+ UINT8 RMTStepSizeOverride;
+
+/** RMT TxDq
+ Step size of TxDq. Auto- 1. Supported values- 1,2,4,8 in FSP.
+ 1:Auto, 2:2, 4:4, 8:8
+**/
+ UINT8 RMTTxDq;
+
+/** RMT TxVref
+ Step size of TxVref. Auto- 1. Supported values- 1,2,4,8 in FSP.
+ 1:Auto, 2:2, 4:4, 8:8
+**/
+ UINT8 RMTTxVref;
+
+/** DDR5 ECS
+ Disable: Disable ECS/Result collection. Enable: Enable ECS without Result Collection.
+ Enable ECS with Result Collection: Enable ECS/Result Collection.
+ 0:Disable, 1:Enable, 2:Enable ECS with Result Collection
+**/
+ UINT8 ErrorCheckScrub;
+
+/** Runtime PPR/Row Sparing
+ Enable/Disable Runtime PPR / Row Sparing.
+ $EN_DIS
+**/
+ UINT8 RtRowSparing;
+
+/** Mca Bank Warm Boot Clear Errors
+ Enable/Disable Mca Bank Warm Boot Clear Errors.
+ $EN_DIS
+**/
+ UINT8 McBankWarmBootClearError;
+
+/** RasStateVarPtr
+ Pointer to array of RAS_STATE_VARIABLE_DATA
+**/
+ UINT32 RasStateVarPtr;
+
+/** Enforce Memory POR
+ Enforce POR (0x0) - Enforces Plan Of Record restrictions for DDR5 frequency and
+ voltage programming. Enforce Stretch Goals (0x1) - Enforce DDR memory frequency
+ stretch goal. <b>Disable (0x2 - Default)</b> - Disables this feature and user is
+ able to run at higher frequencies, specified in the DDR Frequency Limit field (limited
+ by processor support).
+ 0:POR, 1:Enforce Stretch Goals, 2:Disabled
+**/
+ UINT8 EnforceDdrMemoryFreqPor;
+
+/** Enforce Population POR
+ Enable Memory Population POR Enforcement. Selecting Enforce Validated Populations
+ will only allow populations that have been validated in FSP.
+ $EN_DIS
+**/
+ UINT8 EnforcePopulationPor;
+
+/** DDR PPR Type
+ Selects DDR Post Package Repair Type - 2- Hard PPR, <b>1- Soft PPR (Default)</b>,
+ 0- Disabled.
+ 0:Disabled, 2:Hard PPR, 1:Soft PPR
+**/
+ UINT8 pprType;
+
+/** pprAddrVariablePtr
+ Pointer to array of PPR_ADDR_VARIABLE
+**/
+ UINT32 PprAddrVariablePtr;
+
+/** BDAT ACPI Table
+ Enable / Disable publishing BDAT ACPI Table in FSP.
+ $EN_DIS
+**/
+ UINT8 bdatEn;
+
+/** Allow Memory Test Correctable Error
+ Enable - Logs error and allows correctable errors during memory test(DIMM Rank not
+ removed). Disable - Logs error and removes DIMM Rank. Auto - Sets it to the MRC
+ default setting; current default is Enable in FSP.
+ $EN_DIS
+**/
+ UINT8 allowCorrectableMemTestError;
+
+/** SlotPerChannel
+ Slot number per channel, default value is 2
+ 1:Slot1, 2:Slot2
+**/
+ UINT8 SlotPerChannel;
+
+/** Memory I/O Health Check
+ Memory I/O Health Check - 0- Auto, 1- Manual, <b>2- Disable (Default)</b>. Select
+ option Auto for default values. Manual for new values. Disable for disabling feature in FSP.
+ 0:Auto, 1:Manual, 2:Disable
+**/
+ UINT8 MemIOHealthCheck;
+
+/** Memory I/O Health Turnaround Test
+ Memory I/O Health Turnaround Test - 1- Enable, <b>0- Disable (Default)</b>. Select
+ Disable for disabling feature in FSP. Enable for enabling feature in FSP.
+ 0:Disable, 1:Enable
+**/
+ UINT8 MemIOHealthTurnaroundTest;
+
+/** Memory I/O Health Check Loop Count
+ CPGC Test Loop Count for Memory IO Health Test.
+**/
+ UINT8 MemIOLoopCount;
+
+/** RxDqsDelay Left Edge
+ Offset for RxDqsDelay Left Edge in FSP.
+**/
+ UINT8 CriticalRxDqsDelayLeftEdge;
+
+/** RxDqsDelay Right Edge
+ Offset for RxDqsDelay Right in FSP.
+**/
+ UINT8 CriticalRxDqsDelayRightEdge;
+
+/** RxVref Left Edge
+ Offset for RxVref Left Edge in FSP.
+**/
+ UINT8 CriticalRxVrefLeftEdge;
+
+/** RxVref Right Edge
+ Offset for RxVref Right Edge in FSP.
+**/
+ UINT8 CriticalRxVrefRightEdge;
+
+/** TxDqDelay Left Edge
+ Offset for TxDqDelay Left Edge in FSP.
+**/
+ UINT8 CriticalTxDqDelayLeftEdge;
+
+/** TxDqDelay Right Edge
+ Offset for TxDqDelay Right Edge in FSP.
+**/
+ UINT8 CriticalTxDqDelayRightEdge;
+
+/** TxVref Left Edge
+ Offset for TxDqDelay Left Edge in FSP.
+**/
+ UINT8 CriticalTxVrefLeftEdge;
+
+/** TxVref Right Edge
+ Offset for TxDqDelay Right Edge in FSP.
+**/
+ UINT8 CriticalTxVrefRightEdge;
+
+/** Reboot On Critical Failure
+ Reboot System on Critical failure to do Memory Training in FSP.
+ $EN_DIS
+**/
+ UINT8 ResetOnCriticalError;
+
+/** Number of Times to Reboot and Retrain
+ Number of times to Reboot System on Critical failure to do Memory Training in FSP.
+**/
+ UINT8 CriticalRetries;
+
+/** Telemetry RxDqsDelay Left Edge
+ Offset for Telemetry RxDqsDelay Left Edge in FSP.
+**/
+ UINT8 TelemetryRxDqsDelayLeftEdge;
+
+/** Telemetry RxDqsDelay Right Edge
+ Offset for Telemetry RxDqsDelay Right Edge in FSP.
+**/
+ UINT8 TelemetryRxDqsDelayRightEdge;
+
+/** Telemetry RxVref Left Edge
+ Offset for Telemetry RxDqsDelay Left Edge in FSP.
+**/
+ UINT8 TelemetryRxVrefLeftEdge;
+
+/** Telemetry RxVref Right Edge
+ Offset for Telemetry RxDqsDelay Right Edge in FSP.
+**/
+ UINT8 TelemetryRxVrefRightEdge;
+
+/** Telemetry TxDqDelay Left Edge
+ Offset for Telemetry TxDqDelay Left Edge in FSP.
+**/
+ UINT8 TelemetryTxDqDelayLeftEdge;
+
+/** Telemetry TxDqDelay Right Edge
+ Offset for Telemetry TxDqDelay Right Edge in FSP.
+**/
+ UINT8 TelemetryTxDqDelayRightEdge;
+
+/** Telemetry TxVref Left Edge
+ Offset for Telemetry TxDqDelay Left Edge in FSP.
+**/
+ UINT8 TelemetryTxVrefLeftEdge;
+
+/** Telemetry TxVref Right Edge
+ Offset for Telemetry TxDqDelay Right Edge in FSP.
+**/
+ UINT8 TelemetryTxVrefRightEdge;
+
+/** Telemetry CaTiming Left Edge
+ Offset for Telemetry CaTiming Left Edge in FSP.
+**/
+ UINT8 TelemetryCaTimingLeftEdge;
+
+/** Telemetry CaTiming Right Edge
+ Offset for Telemetry CaTiming Right Edge in FSP.
+**/
+ UINT8 TelemetryCaTimingRightEdge;
+
+/** Telemetry CtlTiming Left Edge
+ Offset for Telemetry CtlTiming Left Edge in FSP.
+**/
+ UINT8 TelemetryCtlTimingLeftEdge;
+
+/** Telemetry CtlTiming Right Edge
+ Offset for Telemetry CtlTiming Right Edge in FSP.
+**/
+ UINT8 TelemetryCtlTimingRightEdge;
+
+/** Telemetry CaVref Left Edge
+ Offset for Telemetry CaVref Left Edge in FSP.
+**/
+ UINT8 TelemetryCaVrefLeftEdge;
+
+/** Telemetry CaVref Right Edge
+ Offset for Telemetry CaVref Right Edge in FSP.
+**/
+ UINT8 TelemetryCaVrefRightEdge;
+
+/** Critical CaTiming Left Edge
+ Offset for Critical CaTiming Left Edge in FSP.
+**/
+ UINT8 CriticalCaTimingLeftEdge;
+
+/** Critical CaTiming Right Edge
+ Offset for Critical CaTiming Right Edge in FSP.
+**/
+ UINT8 CriticalCaTimingRightEdge;
+
+/** Critical CtlTiming Left Edge
+ Offset for Critical CtlTiming Left Edge in FSP.
+**/
+ UINT8 CriticalCtlTimingLeftEdge;
+
+/** Critical CtlTiming Right Edge
+ Offset for Critical CtlTiming Right Edge in FSP.
+**/
+ UINT8 CriticalCtlTimingRightEdge;
+
+/** Critical CaVref Left Edge
+ Offset for Critical CaVref Left Edge in FSP.
+**/
+ UINT8 CriticalCaVrefLeftEdge;
+
+/** Critical CaVref Right Edge
+ Offset for Critical CaVref Right Edge in FSP.
+**/
+ UINT8 CriticalCaVrefRightEdge;
+
+/** Intel(R) Flat Memory Mode Support
+ Enable or disable Intel(R) Flat Memory Mode support.
+ 0:Disable, 1:Enable
+**/
+ UINT8 Flat2lmSupport;
+
+/** Dynamic ECC Mode Selection
+ Enable/Disable Dynamic ECC Mode Selection in FSP.
+ $EN_DIS
+**/
+ UINT8 DynamicEccModeSel;
+
+/** Leaky bucket high bit
+ Leaky bucket high bit" (0x1 - 0x29)
+**/
+ UINT8 leakyBktHi;
+
+/** Leaky bucket time window based interface Hour
+ Leaky bucket time window based interface Hour" (0 - 24)
+**/
+ UINT16 leakyBktHour;
+
+/** Leaky bucket low bit
+ Leaky bucket low bit" (0x1 - 0x29)
+**/
+ UINT8 leakyBktLo;
+
+/** Leaky bucket time window based interface Minute
+ Leaky bucket time window based interface Minute" (0 - 60)
+**/
+ UINT8 leakyBktMinute;
+
+/** Leaky bucket time window based interface
+ Enable/Disable leaky bucket time window based interface
+ 0:Disable, 1:Enable
+**/
+ UINT8 leakyBktTimeWindow;
+
+/** Memory Patrol Scrub
+ Enable/Disable Patrol Scrub
+ 0:Disable, 2:Enable at End of POST
+**/
+ UINT8 PatrolScrub;
+
+/** Memory Patrol Scrub Notify
+ Memory Patrol Scrub - <b>0:Disable (Default)</b>, 1:Enable at ReadyToBootFsp().
+ 0:Disable, 1:Enable at ReadyToBootFsp()
+**/
+ UINT8 PatrolScrubNotify;
+
+/** Patrol Scrub Interval
+ Patrol Scrub Interval in FSP.
+**/
+ UINT8 PatrolScrubDuration;
+
+/** Patrol Scrub Address Mode
+ Selects the address mode between <b>System Physical Address (0x1 - Default)</b>
+ or Reverse Address (0x0) in FSP.
+ 0:Reverse Address, 1:System Physical Address
+**/
+ UINT8 PatrolScrubAddrMode;
+
+/** Memory Thermal Throttling Mode
+ Memory Configure Memory Thermal Throttling Mode in FSP.
+ 0:Disable, 2:CLTT, 3:CLTT with PECI
+**/
+ UINT8 thermalthrottlingsupport;
+
+/** Memory Correctable Error Threshold
+ Memory Correctable Error Threshold (1 - 32767) used for sparing and leaky bucket in FSP.
+**/
+ UINT16 spareErrTh;
+
+/** WR CRC feature Control
+ Enable/Disable Write CRC in FSP.
+ $EN_DIS
+**/
+ UINT8 WrCRC;
+
+/** DDR 2x Refresh Enable
+ Enable/Disable 2x Refresh. Auto = dynamically selected.
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 RefreshMode;
+
+/** Adaptive Refresh Management Level
+ Selects Adaptive Refresh Management(ARFM) Level when refresh management(RFM) is
+ required. 0:Default - RAAIMT, RAAMMT, RAADEC; 1:Level A - RAAIMT-A, RAAMMT-A, RAADEC-A;
+ 2:Level B - RAAIMT-B, RAAMMT-B, RAADEC-B; 3:Level C - RAAIMT-C, RAAMMT-C, RAADEC-C
+ 0:Default - RAAIMT or RAAMMT or RAADEC, 1:Level A - RAAIMT-A or RAAMMT-A or RAADEC-A,
+ 2:Level B - RAAIMT-B or RAAMMT-B or RAADEC-B, 3:Level C - RAAIMT-C or RAAMMT-C
+ or RAADEC-C
+**/
+ UINT8 AdaptiveRefreshMgmtLevel;
+
+/** CXL Hetero Support
+ Enable/Disable (Default) DDR CXL Heterogeneous Interleave in FSP.
+ $EN_DIS
+**/
+ UINT8 CxlHeteroSupport;
+
+/** MEMHOT INPUT Control
+ Enable/Disable MEMHOT INPUT in FSP.
+ $EN_DIS
+**/
+ UINT8 MemHotIn;
+
+/** MEMHOT OUTPUT Mode
+ MEMHOT OUTPUT Mode in FSP.
+ 0:Disable, 1:Enable only temphi, 2:Enable only temphi and mid, 3:Enable only temphi
+ mid and low
+**/
+ UINT8 MemhotOutputOnlyOpt;
+
+/** DfxPmicSecureMode
+ 0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode.
+ 0:Disable Pmic Secure Mode, 1:Enable Pmic Secure Mode, 2:Auto Pmic Secure Mode
+**/
+ UINT8 DfxPmicSecureMode;
+
+/** SpdPrintEn
+ Enable/Disable SPD Print
+ $EN_DIS
+**/
+ UINT8 SpdPrintEn;
+
+/** Force PPR On All Dram For UCE
+ Enable/Disable force PPR on all dram for UCE.
+ 0:Disable, 1:Enable
+**/
+ UINT8 ForcePprOnAllDramUce;
+
+/** CXL Header Bypass
+ Enable/Disable the CXL header bypass in FSP.
+ 0:Disable, 1:Enable
+**/
+ UINT8 DfxCxlHeaderBypass;
+
+/** CXL Security Level
+ CXL Security Level<br>\n
+ 0- Fully Trusted - CXL Device can get access on CXL.$ for host-attached and device
+ attached memory ranges in the WB address space.<br>\n
+ 1- Partially Trusted - CXL Device can get access on CXL.$ for device attached memory
+ ranges only;<br>\n
+ 2- Untrusted - All requests on CXL.$ will be aborted by the Host.<br>\n
+ <b>3- Auto - Currently identical to Fully Trusted. (Default)</b>
+ 0:Fully Trusted, 1:Partially Trusted, 2:Untrusted, 3:Auto
+**/
+ UINT8 DfxCxlSecLvl;
+
+/** CXL VID
+ CXL VID on SPR B0. Auto(Default) and Enable is 0x1E98. Disable is 0x8086
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 DfxCxlVid;
+
+/** Warm-Reset Elimination
+ When enabled, BIOS will attempt to skip warm-reset on the cold-reset path. Auto:
+ platform or silicon RC policy determines feature status
+ 0:Disable, 1:Enable, 2:Auto
+**/
+ UINT8 DfxWarmResetEliminationEn;
+
+/** IIO DFX CxlDebugMode Ptr
+ Pointer to array of CxlDebugMode settings Per Port, 0x00000000 indicates Dfx CXL
+ Debug mode Disable.
+**/
+ UINT32 DfxCxlDebugModePtr;
+
+/** IIO DFX CxlDebugMode Number
+ Number of elements in DfxCxlDebugModePtr array, port number as unit, should be set
+ along with DfxCxlDebugModePtr.
+**/
+ UINT32 DfxCxlDebugModeNumber;
+
+/** Processor Package C State
+ Package C State 0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention)
+ state, 7: No Limit, <b>0xFF: Auto (Default)</b>
+ 0: C0/C1 state, 1: C2 state, 2: C6(non Retention) state, 3: C6(Retention) state,
+ 7: No Limit, 0xFF: Auto
+**/
+ UINT8 CpuPmPackageCState;
+
+/** Enhanced Intel SpeedStep(R) Tech
+ Enable(Default)/Disable Enhanced Intel SpeedStep(R) Tech
+ $EN_DIS
+**/
+ UINT8 CpuPmEistEnable;
+
+/** C1E
+ Enable(Default)/Disable C1E
+ $EN_DIS
+**/
+ UINT8 CpuPmC1eEnable;
+
+/** Intel SST-PP
+ Intel SST-PP Select allows user to choose level.\n
+ AUTO: Choose lowest level hardware supported.
+ 0xFF: AUTO (default), 0: Level 0, 1: Level 1, 2: Level 2, 3: Level 3, 4: Level 4
+**/
+ UINT8 CpuPmSstPpLevel;
+
+/** Intel SST-BF
+ SST-BF - <b>0: Disable (Default)</b>, 1: Enabled.
+ $EN_DIS
+**/
+ UINT8 CpuPmProcessorSstBfSetting;
+
+/** Core Disable Bitmask for Socket 0 - Compute Die 0
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0 - Compute Die
+ 0.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt0Die0;
+
+/** Core Disable Bitmask for Socket 0 - Compute Die 1
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0 - Compute Die
+ 1.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt0Die1;
+
+/** Core Disable Bitmask for Socket 0 - Compute Die 2
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 0 - Compute Die
+ 2.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt0Die2;
+
+/** Core Disable Bitmask for Socket 1 - Compute Die 0
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1 - Compute Die
+ 0.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt1Die0;
+
+/** Core Disable Bitmask for Socket 1 - Compute Die 1
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1 - Compute Die
+ 1.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt1Die1;
+
+/** Core Disable Bitmask for Socket 1 - Compute Die 2
+ Set bit(s) to Disable or clear bit(s) to Enable core(s) on Socket 1 - Compute Die
+ 2.\n
+ NOTE:\n
+ (1) Any core disabled by user will force static SST-PP.\n
+ (2) Please leave this UPD at default value if CPU SKU does not support the corresponding
+ number of compute die.
+**/
+ UINT64 CpuPmCoreDisableBitmaskSkt1Die2;
+
+/** Processor Dynamic Intel Speed Select (ISS) Function
+ Enable or Disable(Default) Processor Dynamic Intel Speed Select (ISS) Function
+ $EN_DIS
+**/
+ UINT8 CpuPmDynamicIss;
+
+/** BIOS Region Base
+ Pointer to the location of the BIOS Region
+**/
+ UINT32 BiosRegionBase;
+
+/** BIOS Region Size
+ The size of the BIOS Region in bytes
+**/
+ UINT32 BiosRegionSize;
+
+/** Platform Data Area Base
+ Pointer to the location of the Platform Data Area
+**/
+ UINT32 PlatformDataAreaBase;
+
+/** Platform Data Area Size
+ The size of the Platform Data Area in bytes
+**/
+ UINT32 PlatformDataAreaSize;
+
+/** N/A
+**/
+ UINT8 ReservedMemoryInitUpd[16];
+
+/** Enable TME
+ Enable TME
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableTme;
+
+/** Enable TME CR
+ Enable TME CR
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableTmeCR;
+
+/** Enable MKTME
+ Enable MKTME
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableMktme;
+
+/** Enable Global Integrity
+ Enable Global Integrity
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableGlobalIntegrity;
+
+/** Select TME Crypto Algorithm
+ Enable Global Integrity
+ 0:Algo1,1:Algo2, 2:Algo3
+**/
+ UINT16 SecurityCctTmeCryptoAlg;
+
+/** Enable TDX
+ : Enable TDX
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableTdx;
+
+/** Enable TDX Connect
+ : Enable TDX Connect
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableTdxConnect;
+
+/** TDX Physical PCIe Port Disable Bitmap
+ TDX Physical PCIe Port Disable Bitmap
+**/
+ UINT16 SecurityCctTdxPhysicalPciePortDisableBitmap[8];
+
+/** Key Split
+ : Key Split
+**/
+ UINT8 SecurityCctKeySplit;
+
+/** Enable TDX SEAM Loader
+ : Enable TDX SEAM Loader
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableTdxSeamldr;
+
+/** Enabne SGX
+ : Enable SGX
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableSgx;
+
+/** Dfx Sgx CMCS Payload
+ Dfx Sgx CMCS Payload
+**/
+ UINT64 SecurityCctDfxSgxCmcsPayload[16];
+
+/** SGX QoS
+ : SGX QoS
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxQoS;
+
+/** SGX Auto Registration Agent
+ : SGX Auto Registration Agent
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxAutoRegistrationAgent;
+
+/** SGX Package Info In Band Access
+ : SGX Package Info In Band Access
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxPackageInfoInBandAccess;
+
+/** EPOCH Update
+ : EPOCH Update
+ 3:EpochDeactived, 0:EpochActived, 1:NewRandomEpoch, 2:ManualEpoch
+**/
+ UINT8 SecurityCctEpochUpdate;
+
+/** SGX EPOCH 0
+ : SGX EPOCH 0
+**/
+ UINT64 SecurityCctSgxEpoch0;
+
+/** SGX EPOCH 1
+ : SGX EPOCH 1
+**/
+ UINT64 SecurityCctSgxEpoch1;
+
+/** SGX LeWr
+ : SGX LeWr
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxLeWr;
+
+/** SGX Le Public Key Hash 0
+ : SGX Le Public Key Hash 0
+**/
+ UINT64 SecurityCctSgxLePubKeyHash0;
+
+/** SGX Le Public Key Hash 1
+ : SGX Le Public Key Hash 1
+**/
+ UINT64 SecurityCctSgxLePubKeyHash1;
+
+/** SGX Le Public Key Hash 2
+ : SGX Le Public Key Hash 2
+**/
+ UINT64 SecurityCctSgxLePubKeyHash2;
+
+/** SGX Le Public Key Hash 3
+ : SGX Le Public Key Hash 3
+**/
+ UINT64 SecurityCctSgxLePubKeyHash3;
+
+/** SGX Debug Mode
+ : SGX Debug Mode
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxDebugMode;
+
+/** SGX Factory Reset
+ : SGX Factory Reset
+ $EN_DIS
+**/
+ UINT8 SecurityCctSgxFactoryReset;
+
+/** Dfx Bios Param Header Override
+ : Dfx Bios Param Header Override
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxBiosParamHeaderOverride;
+
+/** Dfx Bios Param Header Version
+ : Dfx Bios Param Header Version
+**/
+ UINT16 SecurityCctDfxBiosParamHeaderVersion;
+
+/** Dfx Disable Actm Launch
+ : Dfx Disable Actm Launch
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxDisableActmLaunch;
+
+/** ACTM Flash Base
+ : ACTM Flash Base
+**/
+ UINT32 SecurityCctActmPcdFlash;
+
+/** Enable UPI FLE
+ : Enable UPI FLE
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableUpiFle;
+
+/** Enable SAF
+ : Enable SAF
+ $EN_DIS
+**/
+ UINT8 SecurityCctEnableSaf;
+
+/** Dfx TDX Disable 1MB CMR Exclude
+ : Dfx TDX Disable 1MB CMR Exclude
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxTdxDisable1MbCmrExclude;
+
+/** Dfx Seamldr Source location
+ : Dfx Seamldr Source location
+ 2:Auto, 0:ESP, 1:IFWI
+**/
+ UINT8 SecurityCctDfxSeamldrSrc;
+
+/** Dfx Tdx module Source location
+ : Dfx Tdx module Source location
+ 2:Auto, 0:ESP, 1:IFWI
+**/
+ UINT8 SecurityCctDfxTdxModuleSrc;
+
+/** Dfx PRMRR SEAMRR Support
+ : Dfx PRMRR SEAMRR Support
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxPrmrrSeamrrSupport;
+
+/** Dfx Simics Environment
+ : Dfx Simics Environment
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxSimicsEnvironment;
+
+/** Dfx Force UPL Unsupported
+ : Dfx Force UPL Unsupported
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxForceUplUnsupported;
+
+/** Dfx TME Key Restore
+ : Dfx TME Key Restore
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxTmeKeyRestore;
+
+/** Dfx TME Exclusion Base
+ : Dfx TME Exclusion Base
+**/
+ UINT64 SecurityCctDfxTmeExclusionBase;
+
+/** Dfx TME Exclusion Length
+ : Dfx TME Exclusion Length
+**/
+ UINT64 SecurityCctDfxTmeExclusionLength;
+
+/** Dfx MKTME KeyIdBits Override
+ : Dfx MKTME KeyIdBits Override
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxMkTmeKeyIdBitsOverride;
+
+/** Dfx MKTME KeyIdBits Override Value
+ : Dfx MKTME KeyIdBits Override Value
+**/
+ UINT8 SecurityCctDfxMkTmeKeyIdBitsOverrideValue;
+
+/** Dfx SGX Debug Print
+ : Dfx SGX Debug Print
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxDebugPrint;
+
+/** Dfx SGX Registration Server Select
+ : Dfx SGX Registration Server Select
+ 1:PRX, 0:SBX, 3:LIV, 4:SoftwareDefined, 2:Auto
+**/
+ UINT8 SecurityCctDfxSgxRegistrationServerSelect;
+
+/** Dfx SGX Add Package Support
+ : Dfx SGX Add Package Support
+ 1:Enabled, 0:Disabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxSgxAddPackageSupport;
+
+/** Dfx allow SGX non POR memory population
+ : Dfx SGX Add Package Support
+ 1:Enabled, 2:Auto
+**/
+ UINT8 SecurityCctDfxAllowSgxNonPorMemoryPopulation;
+
+/** Dfx SGX Hang Before ACTM
+ : Dfx SGX Hang Before ACTM
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangBeforeActm;
+
+/** Dfx SGX Hang After ACTM
+ : Dfx SGX Hang After ACTM
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangAfterActm;
+
+/** Dfx SGX Hang Before MCHECK
+ : Dfx SGX Hang Before MCHECK
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangBeforeMcheck;
+
+/** Dfx SGX Hang After MCHECK
+ : Dfx SGX Hang After MCHECK
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangAfterMcheck;
+
+/** Dfx SGX Hang Before MSR 7A
+ : Dfx SGX Hang Before MSR 7A
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangBeforeMsr7a;
+
+/** Dfx SGX Hang After MSR 7A
+ : Dfx SGX Hang After MSR 7A
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxSgxHangAfterMsr7a;
+
+/** Dfx disable CCT MSR_BIOS_DONE
+ : Dfx disable CCT MSR_BIOS_DONE
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxDisableCctBiosDone;
+
+/** Dfx Mcheck MSR 72
+ : Dfx Mcheck MSR 72 programming
+ $EN_DIS
+**/
+ UINT8 SecurityCctDfxMcheckMsr72;
+
+/** Dfx Skip Warm Reset Promotion
+ : Dfx Skip Warm Reset Promotion
+ 2:Auto, 1:Enabled
+**/
+ UINT8 SecurityCctDfxSkipWarmResetPromotion;
+
+/** Enable SBFT
+ : Enable SBFT
+ 1:Enabled, 0:Disabled, 4:IfsSbftSgxEnabled
+**/
+ UINT8 SecurityCctEnableSbft;
+
+/** PRMRR SGX Size
+ : PRMRR SGX Size
+ 0x8000000:128MB, 0x10000000:256MB, 0x20000000:512MB, 0x40000000:1GB, 0x80000000:2GB,
+ 0x100000000:4GB, 0x200000000:8GB,0x400000000:16GB, 0x800000000:32GB, 0x1000000000:64GB,
+ 0x2000000000:128GB, 0x4000000000:256GB, 0x8000000000:512GB
+**/
+ UINT64 SecurityCctPrmrrSgxSize;
+
+/** PRMRR SAF Size
+ : PRMRR SAF Size
+ 0x0:Invalid, 0x800000:8MB, 0x2000000:32MB, 0x4000000:64MB, 0x8000000:128MB, 0x10000000:256MB
+**/
+ UINT64 SecurityCctPrmrrSafSize;
+
+/** PRMRR SBFT Size
+ : PRMRR SBFT Size
+ 0x0:Invalid, 0x10000000:256MB, 0x20000000:512MB
+**/
+ UINT64 SecurityCctPrmrrSbftSize;
+
+/** N/A
+ Pointer to node list which is used to initizalize security variables - CCT_VS_METADATA_NODE
+**/
+ EFI_PHYSICAL_ADDRESS SecurityCctVarStorageMetadataNodePtr;
+
+/** SINIT ACM SE SVN default
+ Default value of SINIT ACM SE SVN
+**/
+ UINT8 SecurityCctSinitAcmSeSvnFspDefault;
+
+/** SINIT ACM SE SVN override request
+ Override request for SINIT ACM SE SVN
+**/
+ UINT8 SecurityCctSinitAcmSeSvnOverrideRequest;
+
+/** SINIT ACM SE SVN value
+ Value of SINIT ACM SE SVN
+**/
+ UINT8 SecurityCctSinitAcmSeSvnValue;
+
+/** Setup data pointer
+ : Setup data pointer
+**/
+ UINT64 SetupDataPtr;
+
+/** Setup data Size
+ : Setup data Size
+**/
+ UINT64 SetupDataSize;
+
+/** Emulation Setting data pointer
+ : Emulation Setting data pointer
+**/
+ UINT64 EmulationSettingPtr;
+
+/** Emulation Setting data Size
+ : Emulation Setting data Size
+**/
+ UINT64 EmulationSettingSize;
+
+/** Platform info data pointer
+ : Platform info data pointer
+**/
+ UINT64 PlatformInfoPtr;
+
+/** Platform info data Size
+ : Platform info data Size
+**/
+ UINT64 PlatformInfoSize;
+
+/** FSPM Upd settings support
+ : FSPM Upd settings support
+ $EN_DIS
+**/
+ UINT8 FspmUpdSupport;
+
+/** Gen4 RCD Dimm support
+ Gen4 RCD Dimm support, 0- Disable, 1- Enable
+ 0:Disable, 1:Enable
+**/
+ UINT8 Gen4RcdDeviceSupport;
+
+} FSPM_CONFIG;
+
+
+typedef struct {
+
+/** N/A
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** N/A
+**/
+ FSPM_ARCH2_UPD FspmArchUpd;
+
+/** N/A
+**/
+ FSPM_CONFIG FspmConfig;
+
+/** N/A
+**/
+ UINT16 UpdTerminator;
+
+} FSPM_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/BirchStreamFspBinPkg/sp/Include/FspsUpd.h b/BirchStreamFspBinPkg/sp/Include/FspsUpd.h
new file mode 100644
index 0000000..2bf198f
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/FspsUpd.h
@@ -0,0 +1,249 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPS_UPD_H__
+#define __FSPS_UPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+typedef struct {
+
+/** PCIe Controller 0
+ Enable / Disable PCI Express controller 0
+ $EN_DIS
+**/
+ UINT8 EnablePcie0;
+
+/** PCIe Controller 1
+ Enable / Disable PCI Express controller 1
+ $EN_DIS
+**/
+ UINT8 EnablePcie1;
+
+/** Embedded Multi-Media Controller (eMMC)
+ Enable / Disable Embedded Multi-Media controller
+ $EN_DIS
+**/
+ UINT8 EnableEmmc;
+
+/** LAN Controllers
+ Enable / Disable LAN controllers, refer to FSP Integration Guide for details.
+ 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only
+**/
+ UINT8 EnableGbE;
+
+/** PCIe Root Port 0 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort0DeEmphasis;
+
+/** PCIe Root Port 1 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort1DeEmphasis;
+
+/** PCIe Root Port 2 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort2DeEmphasis;
+
+/** PCIe Root Port 3 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort3DeEmphasis;
+
+/** PCIe Root Port 4 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort4DeEmphasis;
+
+/** PCIe Root Port 5 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort5DeEmphasis;
+
+/** PCIe Root Port 6 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort6DeEmphasis;
+
+/** PCIe Root Port 7 DeEmphasis
+ Desired DeEmphasis level for PCIE root port
+ 0:6dB, 1:3.5dB
+**/
+ UINT8 PcieRootPort7DeEmphasis;
+
+/** eMMC DLL Configuration Data
+ Pointer to eMMC DLL Configuration Data
+**/
+ UINT32 EMMCDLLConfigPtr;
+
+/** PCH Protect Range Limit
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
+ limit comparison.
+**/
+ UINT16 PchProtectedRangeLimit[5];
+
+/** PCH Protect Range Base
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
+**/
+ UINT16 PchProtectedRangeBase[5];
+
+/** PchAdrEn
+ PchAdr 0:PLATFORM POR, <b>1:FORCE ENABLE(Default)</b>, 2:FORCE DISABLE
+ 0:PLATFORM POR, 1:FORCE ENABLE, 2:FORCE DISABLE
+**/
+ UINT8 PchAdrEn;
+
+/** Enable Timed GPIO0
+ Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
+ as extension of Hammock Harbor time synchronization
+ $EN_DIS
+**/
+ UINT8 EnableTimedGpio0;
+
+/** Enable Timed GPIO1
+ Enable/Disable Timed GPIO0. When disabled, it disables cross time stamp time-synchronization
+ as extension of Hammock Harbor time synchronization
+ $EN_DIS
+**/
+ UINT8 EnableTimedGpio1;
+
+/** FSP smm init enable
+ Enable / Disable FSP smm init
+ $EN_DIS
+**/
+ UINT8 FspSmmInitEn;
+
+/** C2C3TT
+ Default = 0, means [AUTO]. C2 to C3 Transition Timer, PPDN_INIT = C2C3TT CSR Bit[11:0]
+ 0: Default, Bit[11:0] : C2 to C3 Transition Timer
+**/
+ UINT8 CpuPmC2c3tt;
+
+/** Processor Enable Monitor MWAIT
+ Enable(Default) or Disable Processor Monitor MWAIT
+ $EN_DIS
+**/
+ UINT8 CpuPmMonitorMWait;
+
+/** Processor TurboMode Function
+ Enable(Default) or Disable Processor TurboMode Function
+ $EN_DIS
+**/
+ UINT8 CpuPmTurboMode;
+
+/** Hardware P-States
+ Disable: Hardware chooses a P-state based on OS Request (Legacy P-States)\n
+ Native Mode:Hardware chooses a P-state based on OS guidance\n
+ Out of Band Mode:Hardware autonomously chooses a P-state (no OS guidance)
+ 0:Disable, 1:Native Mode (Default), 2:Out of Band Mode, 3:Native Mode with No Legacy Support
+**/
+ UINT8 CpuPmProcessorHWPMEnable;
+
+/** HardwarePM Interrupt
+ Enable or Disable (Default) Hardware PM Interrupt
+ $EN_DIS
+**/
+ UINT8 CpuPmProcessorHWPMInterrupt;
+
+/** EPP Profile
+ Choose an HWPM Profile, 0: Performance, 128: Balanced Performance, 192: Balanced
+ Power, 255: Power
+ 0: Performance, 128: Balanced Performance, 192: Balanced Power, 255: Power
+**/
+ UINT8 CpuPmProcessorEPPProfile;
+
+/** Boot Performance Mode
+ Select the performance state that the BIOS will set before OS hand off, 0: Max Performance,
+ 1: Max Efficiency
+ 0: Max Performance (Default), 1: Max Efficiency
+**/
+ UINT8 CpuPmBootPstate;
+
+/** Power Performance Tuning
+ Power Performance Tuning <b>0: OS Controls EPB (Default)</b>, 1: BIOS Controls EPB,
+ 2: PECI Controls EPB
+ 0: OS Controls EPB, 1: BIOS Controls EPB, 2: PECI Controls EPB
+**/
+ UINT8 CpuPmPwrPerfTuning;
+
+/** FSPS Upd settings support
+ : FSPS Upd settings support
+ $EN_DIS
+**/
+ UINT8 FspsUpdSupport;
+
+/** N/A
+ Pointer to node list which is used to initizalize security variables - CCT_VS_METADATA_NODE
+**/
+ EFI_PHYSICAL_ADDRESS SecurityCctVarStorageMetadataNodePtr;
+
+/** N/A
+**/
+ UINT8 ReservedSiliconInitUpd[16];
+
+} FSPS_CONFIG;
+
+
+typedef struct {
+
+/** N/A
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** N/A
+**/
+ FSPS_ARCH2_UPD FspsArchUpd;
+
+/** N/A
+**/
+ FSPS_CONFIG FspsConfig;
+
+/** N/A
+**/
+ UINT16 UpdTerminator;
+
+} FSPS_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/BirchStreamFspBinPkg/sp/Include/FsptUpd.h b/BirchStreamFspBinPkg/sp/Include/FsptUpd.h
new file mode 100644
index 0000000..2e7cfa1
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/FsptUpd.h
@@ -0,0 +1,101 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPT_UPD_H__
+#define __FSPT_UPD_H__
+
+#include <FspUpd.h>
+
+#pragma pack(1)
+
+typedef struct {
+
+/** N/A
+**/
+ UINT64 MicrocodeRegionBase;
+
+/** N/A
+**/
+ UINT64 MicrocodeRegionLength;
+
+/** N/A
+**/
+ UINT64 CodeRegionBase;
+
+/** N/A
+**/
+ UINT64 CodeRegionLength;
+
+} FSPT_CORE_UPD;
+
+
+typedef struct {
+
+/** Disable Port80 output in FSP-T
+ 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output
+**/
+ UINT8 FsptPort80RouteDisable;
+
+/** N/A
+**/
+ UINT8 ReservedTempRamInitUpd[31];
+
+} FSPT_CONFIG;
+
+
+typedef struct {
+
+/** N/A
+**/
+ FSP_UPD_HEADER FspUpdHeader;
+
+/** N/A
+**/
+ FSPT_ARCH2_UPD FsptArchUpd;
+
+/** N/A
+**/
+ FSPT_CORE_UPD FsptCoreUpd;
+
+/** N/A
+**/
+ FSPT_CONFIG FsptConfig;
+
+/** N/A
+**/
+ UINT16 UpdTerminator;
+
+} FSPT_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/BirchStreamFspBinPkg/sp/Include/IioPcieConfigUpd.h b/BirchStreamFspBinPkg/sp/Include/IioPcieConfigUpd.h
new file mode 100644
index 0000000..0f33a0c
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/IioPcieConfigUpd.h
@@ -0,0 +1,300 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _IIO_PCIE_CONFIG_UPD_H_
+#define _IIO_PCIE_CONFIG_UPD_H_
+
+#ifndef MAX_SOCKET
+#define MAX_SOCKET 2
+#endif
+
+#ifndef MAX_LOGIC_IIO_STACK
+#define MAX_LOGIC_IIO_STACK 18
+#endif
+
+/**
+ * Maximum number of IIO ports per IIO stack.
+ */
+#ifndef MAX_IIO_PORTS_PER_STACK
+#define MAX_IIO_PORTS_PER_STACK 8
+#endif
+
+#define MAX_IIO_STACK 16
+#define MAX_IIO_STACKS_PER_SOCKET MAX_IIO_STACK
+#define MAX_IIO_PORTS_PER_SOCKET (MAX_IIO_STACKS_PER_SOCKET * MAX_IIO_PORTS_PER_STACK)
+
+#if MAX_SOCKET <= 4
+
+//
+// 10 PCIe stacks (PE) and 3 IO accelerator (IOAT) possible in Rich 1 Socket.
+// However, we share R1S image with 4 socket SP image, no separate build for R1S.
+// So use R1S definitions for 4 socket SP and 4 PE, 1 IOAT entry are just not used, never present.
+//
+#define MAX_IIO_PCIE_PER_SOCKET 10
+#else
+#define MAX_IIO_PCIE_PER_SOCKET 6
+#endif
+
+#define MAX_IOU_PER_SOCKET MAX_IIO_PCIE_PER_SOCKET
+
+#define IIO_BIFURCATE_xxxxxxxx 0xFE
+#define IIO_BIFURCATE_x4x4x4x4 0x0
+#define IIO_BIFURCATE_x4x4xxx8 0x1
+#define IIO_BIFURCATE_xxx8x4x4 0x2
+#define IIO_BIFURCATE_xxx8xxx8 0x3
+#define IIO_BIFURCATE_xxxxxx16 0x4
+#define IIO_BIFURCATE_x2x2x4x8 0x5
+#define IIO_BIFURCATE_x4x2x2x8 0x6
+#define IIO_BIFURCATE_x8x2x2x4 0x7
+#define IIO_BIFURCATE_x8x4x2x2 0x8
+#define IIO_BIFURCATE_x2x2x4x4x4 0x9
+#define IIO_BIFURCATE_x4x2x2x4x4 0xA
+#define IIO_BIFURCATE_x4x4x2x2x4 0xB
+#define IIO_BIFURCATE_x4x4x4x2x2 0xC
+#define IIO_BIFURCATE_x2x2x2x2x8 0xD
+#define IIO_BIFURCATE_x8x2x2x2x2 0xE
+#define IIO_BIFURCATE_x2x2x2x2x4x4 0xF
+#define IIO_BIFURCATE_x2x2x4x2x2x4 0x10
+#define IIO_BIFURCATE_x2x2x4x4x2x2 0x11
+#define IIO_BIFURCATE_x4x2x2x2x2x4 0x12
+#define IIO_BIFURCATE_x4x2x2x4x2x2 0x13
+#define IIO_BIFURCATE_x4x4x2x2x2x2 0x14
+#define IIO_BIFURCATE_x2x2x2x2x2x2x4 0x15
+#define IIO_BIFURCATE_x2x2x2x2x4x2x2 0x16
+#define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17
+#define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18
+#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19
+
+#define IIO_BIFURCATE_xxxxxxx4 0x40
+#define IIO_BIFURCATE_xxx2xxx2 0x41
+#define IIO_BIFURCATE_x1x1xxx2 0x42
+#define IIO_BIFURCATE_xxx2x1x1 0x43
+#define IIO_BIFURCATE_x1x1x1x1 0x44
+
+#define IIO_BIFURCATE_AUTO 0xFF
+
+#define C1_UID 2
+#define C2_UID 3
+
+/**
+ * VTBAR - Virtualization Technology BAR region size and alignment.
+ */
+#define IIO_VTBAR_LSB 16 // 64 kB
+#define IIO_VTBAR_SIZE (1 << IIO_VTBAR_LSB)
+
+#pragma pack(1)
+
+typedef enum {
+ PE0 = 0,
+ PE1,
+ PE2,
+ PE3,
+ PE4,
+ PE5,
+ PEa,
+ PEb,
+ PEc,
+ PEd,
+ PE_MAX,
+ PE_ = 0xFF // temporary unknown value
+} IIO_PACKAGE_PE;
+
+typedef struct {
+ struct {
+ UINT8 Segment; ///< Remember segment, if it changes reset everything
+ UINT8 StackPciBusPoolSize[MAX_LOGIC_IIO_STACK]; ///< Number of bus numbers needed for IIO stack
+ } Socket[MAX_SOCKET];
+} SYSTEM_PCI_BUS_CONFIGURATION;
+
+typedef struct {
+ UINT64 Base; ///< Base (starting) address of a range (I/O, 32 and 64-bit mmio regions)
+ UINT64 Limit; ///< Limit (last valid) address of a range
+} PCIE_BASE_LIMIT;
+
+typedef struct {
+ UINT32 MmioLSize;
+ UINT64 MmioHSize;
+} CXL11_LIMITS;
+
+typedef struct {
+ PCIE_BASE_LIMIT Io; ///< Base and limit of I/O range assigned to entity
+ PCIE_BASE_LIMIT LowMmio; ///< Base and limit of low MMIO region for entity
+ PCIE_BASE_LIMIT HighMmio; ///< Base and limit of high (64-bit) MMIO region for entity
+} PCI_BASE_LIMITS;
+
+typedef struct {
+ PCI_BASE_LIMITS StackLimits[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of all PCIe resources for each stack of the socket
+ CXL11_LIMITS CxlStackReq[MAX_LOGIC_IIO_STACK]; ///< Base and Limit of CXL11 resources for each stack of the socket
+} SOCKET_PCI_BASE_LIMITS;
+
+typedef struct {
+ //
+ // Save basic system configuration parameters along with the resource map to detect a change.
+ // Remember low and high I/O memory range when saving recource configuration. It is used to verify
+ // whether system memory map changed. Remember also stacks configured when creating the map.
+ // If anything changed reset the system PCI resource configuration.
+ //
+ UINT64 MmioHBase;
+ UINT64 MmioHGranularity;
+ UINT32 MmioLBase;
+ UINT32 MmioLLimit;
+ UINT32 MmioLGranularity;
+ UINT16 IoBase;
+ UINT16 IoLimit;
+ UINT16 IoGranularity;
+ UINT32 StackPresentBitmap[MAX_SOCKET];
+ //
+ // Used by the PciHostBridge DXE driver, these variables don't need to be exposed through setup options
+ // The variables are used as a communication vehicle from the PciHostBridge DXE driver to an OEM hook
+ // which updates the KTI resource map.
+ //
+ SOCKET_PCI_BASE_LIMITS Socket[MAX_SOCKET]; ///< Base and limit of all PCIe resources for each socket
+} SYSTEM_PCI_BASE_LIMITS;
+
+typedef struct {
+ UINT8 Address; // SMBUS address of IO expander which provides VPP register
+ UINT8 Port; // Port or bank on IoExpander which provides VPP register
+ UINT8 MuxAddress; // SMBUS address of MUX used to access VPP
+ UINT8 MuxChannel; // Channel of the MUX used to access VPP
+} IIO_VPP_CFG;
+
+typedef struct {
+ UINT8 Address; // SMBUS address of IO expander which provides NPEM
+ UINT8 Bank; // Port or bank on IoExpander which provides NPEM
+ UINT8 MuxAddress; // SMBUS address of MUX used to access NPEM
+ UINT8 MuxChannel; // Channel of the MUX used to access NPEM
+} IIO_NPEM_CFG;
+
+typedef struct {
+ UINT8 Eip : 1; // Electromechanical Interlock Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B17)
+ UINT8 HotPlugSurprise : 1; // Hot Plug surprise supported - Slot Capabilities (D0-10 / F0 / R0xA4 / B5)
+ UINT8 PowerInd : 1; // Power Indicator Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B4)
+ UINT8 AttentionInd : 1; // Attention Inductor Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B3)
+ UINT8 PowerCtrl : 1; // Power Controller Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B1)
+ UINT8 AttentionBtn : 1; // Attention Button Present - Slot Capabilities (D0-10 / F0 / R0xA4 / B0)
+
+ UINT8 Reserved : 2;
+} IIO_SLOT_CFG;
+
+typedef struct {
+ //
+ // Below is an excerpt from structure PCIE_PORT_ENTERPRISE_CONFIG
+ //
+ IIO_VPP_CFG Vpp;
+ IIO_NPEM_CFG Npem;
+ IIO_SLOT_CFG Slot;
+
+ UINT8 VppEnabled :1; // If VPP is supported on given port
+ UINT8 VppExpType :1; // IO Expander type used for VPP (see IIO_VPP_EXPANDER_TYPE for values definitions)
+ UINT8 NpemSupported :1; // If NPEM is supported on given port
+
+ //
+ // Below is an excerpt IIO_PCIE_PORT_CONFIG
+ //
+ UINT8 SlotImplemented :1;
+ UINT8 Retimer1Present :1;
+ UINT8 Retimer2Present :1;
+ UINT8 CommonClock :1;
+ UINT8 SRIS :1;
+
+ //
+ // Below is an excerpt from structure PCIE_PORT_COMMON_CONFIG
+ //
+ UINT16 HotPlug : 1; // If hotplug is supported on slot connected to this port
+ UINT16 MrlSensorPresent : 1; // If MRL is present on slot connected to this port
+ UINT16 SlotPowerLimitScale : 2; // Slot Power Scale for slot connected to this port
+ UINT16 SlotPowerLimitValue : 12; // Slot Power Value for slot connected to this port
+
+ UINT16 PhysicalSlotNumber; // Slot number for slot connected to this port
+} IIO_BOARD_SETTINGS_PER_PORT;
+
+typedef enum {
+ IioBifurcation_UNKNOWN = IIO_BIFURCATE_xxxxxxxx,
+ IioBifurcation_x4x4x4x4 = IIO_BIFURCATE_x4x4x4x4,
+ IioBifurcation_x4x4xxx8 = IIO_BIFURCATE_x4x4xxx8,
+ IioBifurcation_xxx8x4x4 = IIO_BIFURCATE_xxx8x4x4,
+ IioBifurcation_xxx8xxx8 = IIO_BIFURCATE_xxx8xxx8,
+ IioBifurcation_xxxxxx16 = IIO_BIFURCATE_xxxxxx16,
+ IioBifurcation_x2x2x4x8 = IIO_BIFURCATE_x2x2x4x8,
+ IioBifurcation_x4x2x2x8 = IIO_BIFURCATE_x4x2x2x8,
+ IioBifurcation_x8x2x2x4 = IIO_BIFURCATE_x8x2x2x4,
+ IioBifurcation_x8x4x2x2 = IIO_BIFURCATE_x8x4x2x2,
+ IioBifurcation_x2x2x4x4x4 = IIO_BIFURCATE_x2x2x4x4x4,
+ IioBifurcation_x4x2x2x4x4 = IIO_BIFURCATE_x4x2x2x4x4,
+ IioBifurcation_x4x4x2x2x4 = IIO_BIFURCATE_x4x4x2x2x4,
+ IioBifurcation_x4x4x4x2x2 = IIO_BIFURCATE_x4x4x4x2x2,
+ IioBifurcation_x2x2x2x2x8 = IIO_BIFURCATE_x2x2x2x2x8,
+ IioBifurcation_x8x2x2x2x2 = IIO_BIFURCATE_x8x2x2x2x2,
+ IioBifurcation_x2x2x2x2x4x4 = IIO_BIFURCATE_x2x2x2x2x4x4,
+ IioBifurcation_x2x2x4x2x2x4 = IIO_BIFURCATE_x2x2x4x2x2x4,
+ IioBifurcation_x2x2x4x4x2x2 = IIO_BIFURCATE_x2x2x4x4x2x2,
+ IioBifurcation_x4x2x2x2x2x4 = IIO_BIFURCATE_x4x2x2x2x2x4,
+ IioBifurcation_x4x2x2x4x2x2 = IIO_BIFURCATE_x4x2x2x4x2x2,
+ IioBifurcation_x4x4x2x2x2x2 = IIO_BIFURCATE_x4x4x2x2x2x2,
+ IioBifurcation_x2x2x2x2x2x2x4 = IIO_BIFURCATE_x2x2x2x2x2x2x4,
+ IioBifurcation_x2x2x2x2x4x2x2 = IIO_BIFURCATE_x2x2x2x2x4x2x2,
+ IioBifurcation_x2x2x4x2x2x2x2 = IIO_BIFURCATE_x2x2x4x2x2x2x2,
+ IioBifurcation_x4x2x2x2x2x2x2 = IIO_BIFURCATE_x4x2x2x2x2x2x2,
+ IioBifurcation_x2x2x2x2x2x2x2x2 = IIO_BIFURCATE_x2x2x2x2x2x2x2x2,
+
+ // Specific values for DMR pcie4p4 controller for infrastructure lanes
+ IioBifurcation_xxxxxxx4 = IIO_BIFURCATE_xxxxxxx4,
+ IioBifurcation_xxx2xxx2 = IIO_BIFURCATE_xxx2xxx2,
+ IioBifurcation_x1x1xxx2 = IIO_BIFURCATE_x1x1xxx2,
+ IioBifurcation_xxx2x1x1 = IIO_BIFURCATE_xxx2x1x1,
+ IioBifurcation_x1x1x1x1 = IIO_BIFURCATE_x1x1x1x1,
+
+ IioBifurcation_Auto = IIO_BIFURCATE_AUTO
+} IIO_BIFURCATION;
+
+typedef struct {
+ IIO_BIFURCATION Bifurcation;
+ UINT8 CxlSupportInUba :1;
+ UINT8 Reserved :7;
+
+ IIO_BOARD_SETTINGS_PER_PORT Port[MAX_IIO_PORTS_PER_STACK];
+} IIO_BOARD_SETTINGS_PER_PE;
+
+typedef struct {
+ IIO_BOARD_SETTINGS_PER_PE Pe[MAX_IIO_PCIE_PER_SOCKET];
+} IIO_BOARD_SETTINGS_PER_SOCKET;
+
+//
+// HOB to store board settings data created based on UBA data
+//
+typedef struct {
+ IIO_BOARD_SETTINGS_PER_SOCKET Socket[MAX_SOCKET];
+} IIO_BOARD_SETTINGS_HOB;
+
+#pragma pack()
+
+#endif // _IIO_PCIE_CONFIG_UPD_H_
diff --git a/BirchStreamFspBinPkg/sp/Include/IioUniversalDataHob.h b/BirchStreamFspBinPkg/sp/Include/IioUniversalDataHob.h
new file mode 100644
index 0000000..cc82d24
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/IioUniversalDataHob.h
@@ -0,0 +1,219 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _IIO_UNIVERSAL_DATA_HOB_H_
+#define _IIO_UNIVERSAL_DATA_HOB_H_
+
+#define IIO_UNIVERSAL_DATA_GUID { 0x7FF396A1, 0xEE7D, 0x431E, { 0xBA, 0x53, 0x8F, 0xCA, 0x12, 0x7C, 0x44, 0xC0 } }
+
+#ifndef MAX_SOCKET
+#define MAX_SOCKET 2
+#endif
+
+#if (MAX_SOCKET == 1)
+ #define MAX_FW_KTI_PORTS 4 // Maximum KTI PORTS to be used in structure definition.
+#else
+ #define MAX_FW_KTI_PORTS 6 // Maximum KTI PORTS to be used in structure definition
+#endif //(MAX_SOCKET == 1)
+
+#define MAX_LOGIC_IIO_STACK 18
+
+#ifndef MAX_IIO_PCIROOTS_PER_STACK
+#define MAX_IIO_PCIROOTS_PER_STACK 3 // PCI roots that can be created for a stack
+#endif
+
+#define MAX_COMPUTE_DIE 3
+#define MAX_CHA_MAP (2 * MAX_COMPUTE_DIE) //for GNR & SRF only, each compute die has its own CAPID6 & CAPID7 (i.e. 2 CAPID registers)
+
+#ifndef MAX_MESSAGE_LENGTH
+#define MAX_MESSAGE_LENGTH 500
+#endif
+
+#define DINO_UID 0
+#define PC_UID 1
+#define UB_UID 4
+#define CPM0_UID 5
+#define HQM0_UID 6
+
+typedef enum {
+ IioStack0 = 0,
+ IioStack1 = 1,
+ IioStack2 = 2,
+ IioStack3 = 3,
+ IioStack4 = 4,
+ IioStack5 = 5,
+ IioStack6 = 6,
+ IioStack7 = 7,
+ IioStack8 = 8,
+ IioStack9 = 9,
+ IioStack10 = 10,
+ IioStack11 = 11,
+ IioStack12 = 12,
+ IioStack13 = 13,
+ IioStack14 = 14,
+ IioStack15 = 15,
+ IioStack16 = 16,
+ IioStackUnknown = 0xFF
+} IIO_STACK;
+
+//--------------------------------------------------------------------------------------//
+// Structure definitions for Universal Data Store (UDS)
+//--------------------------------------------------------------------------------------//
+#pragma pack(1)
+
+typedef struct {
+ UINT8 Valid; // TRUE, if the link is valid (i.e reached normal operation)
+ UINT8 PeerSocId; // Socket ID
+ UINT8 PeerSocType; // Socket Type (0 - CPU; 1 - IIO)
+ UINT8 PeerPort; // Port of the peer socket
+} QPI_PEER_DATA;
+
+typedef struct {
+ UINT8 Valid;
+ UINT8 PcieSegment;
+ UINT64 SegMmcfgBase;
+ UINT32 StackPresentBitmap;
+ UINT16 Cxl1p1PresentBitmap; // Bitmap of stacks where CXL 1p1 is connected
+ UINT16 CxlCapableBitmap; // Bitmap of stacks capable of CXL
+ UINT8 TotCha;
+ UINT32 SocId;
+ QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info
+} QPI_CPU_DATA;
+
+/**
+ * PCI resources that establish one PCI hierarchy for PCI Enumerator.
+ */
+typedef struct {
+ UINT16 UidType; // Type of UID for this root bridge.
+ UINT8 BusBase; // Base of PCI bus numbers available for PCI devices
+ UINT8 BusLimit; // Limit of PCI bus numbers available for PCI devices
+ UINT16 IoBase; // Base of IO resources available for PCI devices
+ UINT16 IoLimit; // Limit of IO resources available for PCI devices
+ UINT32 Mmio32Base; // Base of low MMIO resources available for PCI devices
+ UINT32 Mmio32Limit; // Limit of low MMIO resources available for PCI devices
+ UINT64 Mmio64Base; // Base of high MMIO resources available for PCI devices
+ UINT64 Mmio64Limit; // Limit of high MMIO resources available for PCI devices
+} UDS_PCIROOT_RES;
+
+/**
+ * This structore keeps resources configured in Host I/O Processor (HIOP) for one stack.
+ * One HIOP may produce more than one PCI hierarchy, these are in PciRoot[] table.
+ */
+typedef struct {
+ UINT8 Personality;
+ UINT8 PciRootBridgeNum; // Number of valid entries in PciRoot[] table
+ UINT8 Segment; // Segment for this stack
+ UINT8 BusBase; // Base of Bus configured for this stack
+ UINT8 BusLimit; // Limit of Bus configured for this stack
+ UINT8 Reserved[3]; // Reserved for alignment
+ UINT16 IoBase; // Base of IO configured for this stack
+ UINT16 IoLimit; // Limit of IO configured for this stack
+ UINT32 Mmio32Base; // Base of low MMIO configured for this stack in memory map
+ UINT32 Mmio32Limit; // Limit of low MMIO configured for this stack in memory map
+ UINT32 Mmio32MinSize; // The size of MMIO32 needed in PEI that must be preserved in rebalance
+ UINT64 Mmio64Base; // Base of high MMIO configured for this stack in memory map
+ UINT64 Mmio64Limit; // Limit of high MMIO configured for this stack in memory map
+ UINT64 VtbarAddress; // VT-d Base Address
+ UINT64 ChbcrBarAddress; // CXL Host Bridge Component Registers (CHBCR) region
+ UDS_PCIROOT_RES PciRoot[MAX_IIO_PCIROOTS_PER_STACK];
+} UDS_STACK_RES;
+
+/**
+ * This structore keeps resource ranges configured in one socket. It contains a table of IO stacks provided by
+ // the socket. The stacks are also groupded by IO dies, but dies are not reflected in UDS.
+ */
+typedef struct {
+ UINT8 Valid;
+ UINT8 SocketID; // Socket ID of the IIO (0..3)
+ UINT16 IoBase;
+ UINT16 IoLimit;
+ UINT32 Mmio32Base; // Base of low MMIO configured for this socket in memory map
+ UINT32 Mmio32Limit; // Limit of low MMIO configured for this socket in memory map
+ UINT64 Mmio64Base; // Base of high MMIO configured for this socket in memory map
+ UINT64 Mmio64Limit; // Limit of high MMIO configured for this socket in memory map
+ UDS_STACK_RES StackRes[MAX_LOGIC_IIO_STACK];
+} UDS_SOCKET_RES;
+
+/**
+ * This structore keeps resource ranges configured in whole system.
+ */
+typedef struct {
+ UINT16 SystemIoBase; // System IO Base
+ UINT16 SystemIoLimit; // System IO Limit
+ UINT32 SystemIoApicBase; // Legacy IOAPIC base address, one in the system
+ UINT32 SystemIoApicLimit;
+ UINT32 SystemMmio32Base; // System low MMIO base
+ UINT32 SystemMmio32Limit; // System low MMIO limit
+ UINT64 SystemMmio64Base; // System high MMIO Base
+ UINT64 SystemMmio64Limit; // System high MMIO Limit
+ QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
+ UINT64 PciExpressBase; // PCI Config Space base address
+ UINT64 PciExpressSize; // PCI Config Space size
+ UDS_SOCKET_RES IIO_resource[MAX_SOCKET];
+ UINT32 packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. <AS> for CpuSv
+ UINT16 IoGranularity;
+ UINT32 Mmio32Granularity;
+ UINT64 Mmio64Granularity;
+ UINT32 UboxMmioSize;
+ UINT32 MemTolm;
+ UINT32 MemTsegSize;
+ UINT32 MaxAddressBits;
+} PLATFORM_DATA;
+
+typedef struct {
+ BOOLEAN FailFlag;
+ CHAR16 Message[MAX_MESSAGE_LENGTH];
+} REBALANCE_FAIL_INFO;
+
+typedef struct {
+ UINT8 CurrentUpiiLinkSpeed; // Current programmed UPI Link speed (Slow/Full speed mode)
+ UINT8 CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT)
+ UINT8 OutKtiCpuSktHotPlugEn; // 0 - Disabled, 1 - Enabled for PM X2APIC
+ UINT32 meRequestedSize; // Size of the memory range requested by ME FW, in MB
+ UINT8 SystemRasType;
+ UINT8 numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC
+ UINT8 OutSncEn;
+ UINT8 OutNumOfCluster;
+ UINT8 BitsUsed; //For 5 Level Paging
+ REBALANCE_FAIL_INFO RebalanceFailInfo;
+} SYSTEM_STATUS;
+
+typedef struct {
+ PLATFORM_DATA PlatformData;
+ SYSTEM_STATUS SystemStatus;
+ UINT32 OemValue;
+} IIO_UDS;
+
+#pragma pack()
+
+#endif // _IIO_UNIVERSAL_DATA_HOB_H_
+
diff --git a/BirchStreamFspBinPkg/sp/Include/MemoryMapDataHob.h b/BirchStreamFspBinPkg/sp/Include/MemoryMapDataHob.h
new file mode 100644
index 0000000..5df1afc
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/MemoryMapDataHob.h
@@ -0,0 +1,359 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _MEMORY_MAP_DATA_HOB_H_
+#define _MEMORY_MAP_DATA_HOB_H_
+
+#define MEMORY_MAP_HOB_GUID { 0xf8870015, 0x6994, 0x4b98, { 0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f } }
+
+#ifndef MAX_SOCKET
+#define MAX_SOCKET 2
+#endif
+
+#ifndef MAX_IMC
+#define MAX_IMC 8 // Maximum memory controllers per socket
+#endif
+
+#ifndef MAX_MC_CH
+#define MAX_MC_CH 1 // Max number of channels per MC (3 for EP)
+#endif
+
+#ifndef MAX_CH
+#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
+#endif
+
+#ifndef MAX_CXL_HOST_BRIDGES
+#define MAX_CXL_HOST_BRIDGES 0x6 // Maximum number of CXL host bridges per socket.
+#endif
+
+#ifndef MAX_CXL_HOST_BRIDGE_WAYS
+#define MAX_CXL_HOST_BRIDGE_WAYS 0x4 // Maximum interleave ways of CXL host bridges per socket.
+#endif
+
+//
+// Macro definitions for abstracted memory decoding target. The data structure is designed to
+// iterate iMC and CXL host bridge host decoded memory in an unified way.
+// definition for GNRSRF/GNRD/GRR
+//
+#define MAX_CXL_AMT MAX_CXL_HOST_BRIDGES // Max number of unique interleaves for NGN DIMM
+
+
+#ifndef MAX_UNIQUE_NGN_DIMM_INTERLEAVE
+#define MAX_UNIQUE_NGN_DIMM_INTERLEAVE 2 // Max number of unique interleaves for NGN DIMM
+#endif
+
+#ifndef MAX_SPARE_RANK
+#define MAX_SPARE_RANK 2 // Max number of spare ranks in a channel
+#endif
+
+#ifndef MAX_HBM_IO
+#define MAX_HBM_IO 4
+#endif
+
+#ifndef MAX_DIMM
+#define MAX_DIMM 2 // Max DIMM per channel
+#endif
+
+#ifndef MAX_RANK_DIMM
+#define MAX_RANK_DIMM 2
+#endif
+
+#ifndef MAX_DRAM_CLUSTERS
+#define MAX_DRAM_CLUSTERS 6
+#endif
+
+#ifndef MAX_SAD_RULES
+#define MAX_SAD_RULES 16
+#endif
+
+#ifndef MAX_FPGA_REMOTE_SAD_RULES
+#define MAX_FPGA_REMOTE_SAD_RULES 2 // Maximum FPGA sockets exists on ICX platform
+#endif
+
+#define MAX_SI_SOCKET 8 // Maximum silicon supported socket number
+
+#define MAX_AMT (MAX_IMC+MAX_CXL_AMT) // Max abstract memory target per socket
+#define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets
+
+// NGN
+#define NGN_MAX_SERIALNUMBER_STRLEN 4
+#define NGN_MAX_PARTNUMBER_STRLEN 30
+#define NGN_FW_VER_LEN 4
+#define NGN_LOG_TYPE_NUM 2
+#define NGN_LOG_LEVEL_NUM 2
+
+/**
+ * Memory channel index conversion macros.
+ *
+ * We got two types of memory channel indexes:
+ * - socket channel - indexes 0..MAX_CH, used in [socket][channel] indexing
+ * - IMC channel - indexes 0..MAX_MC_CH, used in [socket][IMC][channel] indexing
+ * The below defined macros convert one channel index to the other one.
+ */
+#define MEM_SKTCH_TO_IMC(SktCh) ((SktCh) / MAX_MC_CH)
+#define MEM_SKTCH_TO_IMCCH(SktCh) ((SktCh) % MAX_MC_CH)
+#define MEM_IMCCH_TO_SKTCH(Imc, Ch) ((Imc) * MAX_MC_CH + (Ch))
+
+#define MEM_64MB_TO_BYTES(Size64M) ((UINT64)(Size64M) << 26)
+#define MEM_64MB_TO_KBYTES(Size64M) ((UINT64)(Size64M) << 16)
+#define MEM_64MB_TO_MBYTES(Size64M) ((UINT64)(Size64M) << 6)
+#define MEM_64MB_TO_GBYTES(Size64M) ((Size64M) >> 4)
+#define MEM_BYTES_TO_64MB(SizeB) ((SizeB) >> 26)
+#define MEM_KBYTES_TO_64MB(SizeKB) ((SizeKB) >> 16)
+#define MEM_MBYTES_TO_64MB(SizeMB) ((SizeMB) >> 6)
+
+typedef UINT8 INTLV_SET_KEY;
+
+#define FSP_RESERVED1_LEN 5476
+#define FSP_RESERVED2_LEN 1
+#define FSP_RESERVED3_LEN 220
+#define FSP_RESERVED4_LEN 10
+#pragma pack(1)
+
+struct RankDevice {
+ UINT8 enabled; // 0 = disabled, 1 = enabled
+ UINT8 logicalRank; // Logical Rank number (0 - 7)
+ UINT16 rankSize; // Units of 64 MB
+};
+
+struct PersisentDpaMap
+{
+ UINT32 perRegionDPAOffset;
+ UINT32 SPALimit;
+};
+
+typedef struct firmwareRev {
+ UINT8 majorVersion;
+ UINT8 minorVersion;
+ UINT8 hotfixVersion;
+ UINT16 buildVersion;
+} FIRMWARE_REV;
+
+typedef struct DimmDevice {
+ UINT8 Present;
+ BOOLEAN Enabled;
+ UINT8 DcpmmPresent; // 1 - This is a DCPMM
+ UINT8 X4Present;
+ UINT8 DramIoWidth; // Actual DRAM IO Width (4, 8, 16)
+ UINT8 NumRanks; // Number of ranks on dimm
+ UINT8 NumPackageRanks; // Number of Package ranks on dimm
+ // For DDR5 NumRanks and NumPackageRanks same
+ // For MRDIMM NumRanks and NumPackageRanks may differ
+ UINT8 keyByte;
+ UINT8 actKeyByte2; // Actual module type reported by SPD
+ UINT8 actSPDModuleOrg; // Actual number of DRAM ranks and device width
+ UINT8 dimmTs; // Thermal sensor data.
+ UINT16 VolCap; // Volatile capacity (AEP DIMM only)
+ UINT16 nonVolCap; // Non-volatile capacity (AEP DIMM only)
+ UINT16 DimmSize;
+ UINT16 SPDMMfgId; // Module Mfg Id from SPD
+ UINT16 VendorID;
+ UINT16 DeviceID;
+ UINT16 RevisionID;
+ UINT32 perRegionDPA; // DPA of PMEM that Nfit needs
+ struct PersisentDpaMap perDPAMap[MAX_UNIQUE_NGN_DIMM_INTERLEAVE]; // DPA map
+ UINT8 serialNumber[NGN_MAX_SERIALNUMBER_STRLEN]; // Serial Number
+ UINT8 PartNumber[NGN_MAX_PARTNUMBER_STRLEN]; // Part Number
+ UINT8 FirmwareVersionStr[NGN_FW_VER_LEN]; // Used to update the SMBIOS TYPE 17
+ struct firmwareRev FirmwareVersion; // Firmware revision
+ struct RankDevice rankList[MAX_RANK_DIMM];
+ UINT16 InterfaceFormatCode;
+ UINT16 SubsystemVendorID;
+ UINT16 SubsystemDeviceID;
+ UINT16 SubsystemRevisionID;
+ UINT16 FisVersion; // Firmware Interface Specification version
+ UINT8 DimmSku; // Dimm SKU info
+ UINT8 manufacturingLocation; // Manufacturing location for the NVDIMM
+ UINT16 manufacturingDate; // Date the NVDIMM was manufactured
+ INT32 commonTck;
+ UINT8 EnergyType; // 0: 12V aux power; 1: dedicated backup energy source; 2: no backup energy source
+ BOOLEAN NvDimmNPresent; // JEDEC NVDIMM-N Type Memory Present
+ UINT8 CidBitMap; // SubRankPer CS for DIMM device
+ UINT16 SPDRegVen; // Register Vendor ID in SPD
+ UINT8 SPDOtherOptFeatures; // SDRAM Other Optional features
+ BOOLEAN DimmChanged;
+} MEMMAP_DIMM_DEVICE_INFO_STRUCT;
+
+typedef struct ChannelDevice {
+ UINT8 Enabled; // 0 = channel disabled, 1 = channel enabled
+ UINT8 Features; // Bit mask of features to enable or disable
+ UINT8 MaxDimm; // Number of DIMM
+ UINT8 NumRanks; // Number of ranks on this channel
+ UINT8 chFailed;
+ UINT8 ngnChFailed;
+ UINT8 Is4BitEccDimmPresent; // 4-bit Ecc dimm present indicator
+ UINT8 SpareLogicalRank[MAX_SPARE_RANK]; // Logical rank, selected as Spare
+ UINT8 SparePhysicalRank[MAX_SPARE_RANK]; // Physical rank, selected as spare
+ UINT16 SpareRankSize[MAX_SPARE_RANK]; // spare rank size
+ UINT8 EnabledLogicalRanks; // Bitmap of Logical ranks that are enabled
+ UINT8 DdrPopulationMap; // Bitmap to indicate location of DDR DIMMs within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+ UINT8 PmemPopulationMap; // Bitmap to indicate location of PMem modules within the channel memory slots (BIT0: Ch.D0, BIT1: CH.D1)
+ MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM];
+} CHANNEL_DEVICE;
+
+typedef struct memcontroller {
+ UINT32 MemSize;
+} MEMCONTROLLER;
+
+typedef enum {
+ MemTypeNone = 0,
+ MemType1lmDdr,
+ MemType1lmAppDirect,
+ MemType1lmAppDirectReserved,
+ MemType1lmCtrl,
+ MemType1lmHbm,
+ MemTypeNxm,
+ MemType2lmDdrCacheMemoryMode,
+ MemType2lmDdrWbCacheAppDirect,
+ MemType2lmHbmCacheDdr,
+ MemType2lmHbmCacheMemoryMode,
+ MemTypeCxlAccVolatileMem,
+ MemTypeCxlAccPersistentMem,
+ MemTypeFpga,
+ MemTypeCxlExpVolatileMem,
+ MemTypeCxlExpPersistentMem,
+ MemTypeCxl2lmDdrCacheMem,
+ MemTypeCxlHetero,
+ MemTypeCxlAccVolatileMemHdmDb,
+ MemTypeCxlExpVolatileMemDcd,
+ MemTypeMax
+} MEM_TYPE;
+
+typedef struct SADTable {
+ UINT8 Enable; // Rule enable
+ MEM_TYPE type; // Bit map of memory region types, See defines 'MEM_TYPE_???' above for bit definitions of the ranges.
+ UINT8 granularity; // Interleave granularities for current SAD entry. Possible interleave granularity options depend on the SAD entry type. Note that SAD entry type BLK Window and CSR/Mailbox/Ctrl region do not support any granularity options
+ UINT32 Base; // Base of the current SAD entry
+ UINT32 Limit; // Limit of the current SAD entry
+ UINT8 ways; // Interleave ways for SAD
+ UINT8 channelInterBitmap[MAX_AMT]; //Bit map to denote which DDR4/NM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
+ UINT8 FMchannelInterBitmap[MAX_AMT]; //Bit map to denote which FM channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
+ UINT8 NmChWays; // Channel Interleave ways for SAD. Represents channelInterBitmap ways for DDR4/NM.
+ UINT8 FmChWays; // Channel Interleave ways for SAD. Represents FMchannelInterBitmap ways for DDRT.
+ UINT32 imcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket (based on channel ID for DMR).
+ UINT32 NmImcInterBitmap; // Bit map to denote which IMCs are interleaved from this socket as NM.
+ BOOLEAN local; // 0 - Remote 1- Local
+ UINT8 IotEnabled; // To indicate if IOT is enabled
+ UINT8 mirrored; // To Indicate the SAD is mirrored while enabling partial mirroring
+ UINT8 Attr;
+ UINT8 tgtGranularity; // Interleave mode for target list
+ UINT8 Cluster; // SNC cluster, hemisphere, or quadrant index.
+ UINT8 HostBridgeGran; // Host bridge interleaving granularity.
+ UINT8 HostBridgeList[MAX_CXL_HOST_BRIDGE_WAYS]; // List of interleaved CXL host bridges (DMR and beyond).
+ UINT32 HotPlugPadSize; // Memory size padded for CXL hot plug. 0 if it is not a CXL hot plug SAD.
+ INTLV_SET_KEY CxlIntlvSetKey; // The unique key of CXL interleave set. (7nm)
+} SAD_TABLE;
+
+typedef struct socket {
+ UINT8 SocketEnabled;
+ UINT32 IioStackBitmap;
+ BOOLEAN HbmIoEn[MAX_HBM_IO]; // Flag indicates if HBM IO is enabled. TRUE: HBM IO is Enabled, FALSE: HBM IO is disabled.
+ UINT8 imcEnabled[MAX_IMC];
+ UINT8 SadIntList[MAX_DRAM_CLUSTERS * MAX_SAD_RULES][AMT_MAX_NODE]; // SAD interleave list
+ UINT32 SktTotMemMapSPA; // Total memory mapped to SPA
+ SAD_TABLE SAD[MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; // SAD table
+ MEMCONTROLLER imc[MAX_IMC];
+ CHANNEL_DEVICE ChannelInfo[MAX_CH];
+} MEMMAP_SOCKET;
+
+typedef struct {
+ UINT8 Enabled; // Indicates if this EDC is enabled
+ UINT32 MemAsCache; // Memory used as Cache, in 64MB units
+ UINT32 MemAsFlat; // Memory used as Flat memory, in 64MB units
+} EDC_INFO;
+
+typedef struct SystemMemoryMapElement {
+ UINT16 Type; // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region
+ UINT8 NodeId; // Node ID of the HA Owning the memory
+ UINT8 SocketId; // Socket Id of socket that has his memory - ONLY IN NUMA
+ UINT8 ClusterId; // Logical cluster Id of SNC cluster - only 0 in UMA clustering and all2all
+ UINT8 SktInterBitmap; // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets
+ UINT32 ImcInterBitmap; // IMC interleave bitmap for this memory
+ UINT8 ChInterBitmap[MAX_AMT];//Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; 011b denotes Ch1 & 0 are interleaved
+ UINT32 BaseAddress; // Base Address of the element in 64MB chunks
+ UINT32 ElementSize; // Size of this memory element in 64MB chunks
+} SYSTEM_MEMORY_MAP_ELEMENT;
+
+typedef struct SystemMemoryMapHob {
+ //
+ // Total Clusters. In SNC2 mode there are 2 clusters and SNC4 mode has 4 clusters.
+ // All2All/Hex/Quad/Hemi modes can be considered as having only one cluster (i.e SNC1).
+ //
+ UINT8 TotalClusters;
+ UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem.
+ UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem.
+ UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem.
+ UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem.
+ UINT32 memSize; // Total physical memory size
+ UINT16 memFreq; // Mem Frequency
+ UINT16 HbmFreq; // HBM Frequency in MHz.
+ UINT8 memMode; // 0 - Independent, 1 - Lockstep
+ UINT8 VolMemMode; // 0 - 1LM, 1 - 2LM
+ UINT16 DramType;
+ UINT8 DdrVoltage;
+ UINT8 XMPProfilesSup;
+ UINT8 XMPCapability;
+ //
+ // HBM Specific Info.
+ //
+ UINT16 HbmInstances[MAX_SOCKET]; // Total HBM instances
+ UINT32 HbmFlatMemSize; // Total HBM memory size in 64MB units, if HBM used as Flat memory
+ UINT32 HbmCacheMemSize; // Total HBM memory used as cache, if HBM used as Cache memory
+ UINT16 HbmSpeed; // Configured HBM (i.e OPIO channel) speed in MT/s.
+ UINT16 MaxHbmSpeed; // Max HBM (i.e OPIO channel) speed in MT/s.
+ UINT8 SystemRasType;
+ UINT8 RasModesEnabled; // RAS modes that are enabled
+ UINT16 ExRasModesEnabled; // Extended RAS modes that are enabled
+ UINT8 sncEnabled; // 0 - SNC disabled for this configuration, 1 - SNC enabled for this configuration
+ UINT8 NumOfCluster;
+ UINT8 NumChPerMC;
+ UINT8 numberEntries; // Number of Memory Map Elements
+ SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES];
+ UINT8 reserved1[FSP_RESERVED1_LEN]; // struct memSetup MemSetup;
+ UINT8 reserved2[FSP_RESERVED2_LEN]; // MEM_DFXMEMVARS DfxMemVar;
+ MEMMAP_SOCKET Socket[MAX_SOCKET];
+ UINT8 reserved3[FSP_RESERVED3_LEN]; // struct memTiming profileMemTime[XMP_MAX_PROFILES];
+
+ UINT8 reserved4[FSP_RESERVED4_LEN]; // RASMEMORYINFO RasMeminfo;
+ UINT32 DdrCacheSize[MAX_SOCKET][MAX_CH]; // Size of DDR memory reserved for 2LM cache (64MB granularity)
+ UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS
+ UINT32 MmiohBase; // MMIOH base in 64MB granularity
+ UINT8 MaxSadRules; // Maximum SAD entries supported by silicon (16 for 10nm silicon)
+ UINT8 NumberofChaDramClusters; // Number of CHA DRAM decoder clusters
+ BOOLEAN VirtualNumaEnable; // Enable or Disable Virtual NUMA
+ UINT8 VirtualNumaNodes; // Number of virtual NUMA nodes per physical NUMA node (non-zero)
+ BOOLEAN MrDimmMemFreqRangeEn; // MRDIMM Memory Frequency range enabled.
+} SYSTEM_MEMORY_MAP_HOB;
+
+#pragma pack()
+
+#endif // _MEMORY_MAP_DATA_H_
diff --git a/BirchStreamFspBinPkg/sp/Include/PrevBootErrSrcHob.h b/BirchStreamFspBinPkg/sp/Include/PrevBootErrSrcHob.h
new file mode 100644
index 0000000..6eeabd3
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/PrevBootErrSrcHob.h
@@ -0,0 +1,86 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _PREV_BOOT_ERR_SRC_HOB_H_
+#define _PREV_BOOT_ERR_SRC_HOB_H_
+
+#define FSP_PREV_BOOT_ERR_SRC_HOB_GUID { 0x5138b5c5, 0x9369, 0x48ec, { 0x5b, 0x97, 0x38, 0xa2, 0xf7, 0x09, 0x66, 0x75 } }
+
+#define PREV_BOOT_ERR_SRC_HOB_SIZE 1000
+
+#pragma pack(1)
+
+typedef struct {
+UINT16 Length; // Actual size of the error sources used in the HOB
+UINT8 HobData[PREV_BOOT_ERR_SRC_HOB_SIZE -2]; // List of Error source structures of format //MCBANK_ERR_INFO or CSR_ERR_INFO
+}PREV_BOOT_ERR_SRC_HOB;
+
+typedef struct{
+UINT8 Type; // McBankType = 1;
+UINT8 Segment;
+UINT8 Socket;
+UINT16 ApicId; // ApicId is Needed only if it a core McBank.
+UINT16 McBankNum;
+UINT64 McBankStatus;
+UINT64 McbankAddr;
+UINT64 McBankMisc;
+} MCBANK_ERR_INFO;
+
+typedef struct {
+UINT8 Type; // PciExType =2 ;
+UINT8 Segment;
+UINT8 Bus;
+UINT8 Device;
+UINT8 Function;
+UINT32 AerUncErrSts;
+UINT8 AerHdrLogData[16];
+} PCI_EX_ERR_INFO;
+
+typedef struct {
+UINT8 Type; // Other Csr error type =3 ;
+UINT8 Segment;
+UINT8 Bus;
+UINT8 Device;
+UINT8 Function;
+UINT16 offset;
+UINT32 Value;
+} CSR_ERR_INFO;
+
+typedef enum {
+ McBankType = 1,
+ PciExType,
+ CsrOtherType
+} ERROR_ACCESS_TYPE;
+
+#pragma pack()
+
+#endif //_PREV_BOOT_ERR_SRC_HOB_H_
diff --git a/BirchStreamFspBinPkg/sp/Include/SystemInfoHob.h b/BirchStreamFspBinPkg/sp/Include/SystemInfoHob.h
new file mode 100644
index 0000000..9f0987a
--- /dev/null
+++ b/BirchStreamFspBinPkg/sp/Include/SystemInfoHob.h
@@ -0,0 +1,271 @@
+/** @file
+
+Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef _SYSTEM_INFO_HOB_H_
+#define _SYSTEM_INFO_HOB_H_
+
+#define SYSTEM_INFO_HOB_GUID { 0x7650A0F2, 0x0D91, 0x4B0C, { 0x92, 0x3B, 0xBD, 0xCF, 0x22, 0xD1, 0x64, 0x35 } }
+
+#ifndef MAX_SOCKET
+#define MAX_SOCKET 2
+#endif
+
+#ifndef MAX_IIO_STACK
+#define MAX_IIO_STACK 16
+#endif
+
+#define MAX_LOGIC_IIO_STACK 18
+#define MAX_HPM_PFS_ENTRY_NUM 15 // Number of entries in PFS structure
+#define HPM_PFS_ENTRY_SIZE 2 // Entry size of PFS structure in DWORD
+
+#ifndef MAX_IMC
+#define MAX_IMC 8 // Maximum memory controllers per socket
+#endif
+
+#ifndef MAX_MC_CH
+#define MAX_MC_CH 1 // Max number of channels per MC (3 for EP)
+#endif
+
+#ifndef MAX_CH
+#define MAX_CH ((MAX_IMC)*(MAX_MC_CH)) // Max channels per socket (worst case EP * EX combination = 16)
+#endif
+
+#pragma pack(1)
+
+typedef enum {
+ TYPE_SCF_BAR = 0,
+ TYPE_PCU_BAR,
+ TYPE_MEM_BAR0,
+ TYPE_MEM_BAR1,
+ TYPE_MEM_BAR2,
+ TYPE_MEM_BAR3,
+ TYPE_MEM_BAR4,
+ TYPE_MEM_BAR5,
+ TYPE_MEM_BAR6,
+ TYPE_MEM_BAR7,
+ TYPE_SBREG_BAR,
+ TYPE_MAX_MMIO_BAR
+} MMIO_BARS;
+
+typedef enum {
+ ReservedMemSs,
+ Ddr4MemSs = 1,
+ Ddr5MemSs = 2,
+ LpDdr4MemSs = 3,
+ LpDdr5MemSs = 4,
+ Hbm2MemSs = 5,
+ MrcMstMax,
+ MrcMstDelim = MAX_INT32
+} MRC_MST;
+
+typedef enum BootMode {
+ NormalBoot = 0, // Normal path through RC with full init, mem detection, init, training, etc.
+ // Some of these MRC specific init routines can be skipped based on MRC input params
+ // in addition to the sub-boot type (WarmBoot, WarmBootFast, etc).
+ S3Resume = 1 // S3 flow through RC. Should do the bare minimum required for S3
+ // init and be optimized for speed.
+} BOOT_MODE;
+
+//
+// This is used to determine what type of die is connected to a UPI link
+//
+typedef enum {
+ UpiConnectionTypeCpu,
+ UpiConnectionTypePcieGen4,
+ UpiConnectionTypeFpga,
+ UpiConnectionTypeMax
+} UPI_CONNECTION_TYPE;
+
+//
+// VSEC info for HPM
+// The HPM_INFO struct contains info collected from the VSEC structure for the HPM.
+// VSEC Structure is defined as below:
+//
+// ------------------------VSEC Structure------------------------
+// | Next Cap Offset(12b) | Cap Version(4b) | PCIe Cap ID(16b) |
+// --------------------------------------------------------------
+// | VSEC_LEN(12b) | VSEC_REV(4b) | VSEC_ID(16b) |
+// --------------------------------------------------------------
+// | EntrySize(8b) | NumEntries(8b) | Rsvd(16b) |
+// --------------------------------------------------------------
+// | Address(29b) | tBIR(3b) |
+// --------------------------------------------------------------
+//
+//
+typedef struct {
+ UINT8 NumEntries; // The number of PM feature interface instances in this VSEC space
+ UINT8 EntrySize; // The entry size for each PM interface instance in 32-bit DWORDs
+ UINT32 Address; // The offset from the BAR register which is used for HPM to point to the base of the discovery entry. i.e. the PFS (PM Feature Structure)
+ UINT8 tBIR; // Which one of he function's BAR is used for the PFS offset
+} HPM_INFO;
+
+//
+//-------------------------------- - PFS Entry--------------------------------
+//| EntrySize(16b) | NumEntries(8b) | VSEC_SubID(8b) |
+//----------------------------------------------------------------------------
+//| RSVD(14b) | Attr(2b) | CapOffset(16b) |
+//----------------------------------------------------------------------------
+//
+typedef struct {
+ UINT32 TpmiId : 8;
+ UINT32 NumEntries : 8;
+ UINT32 EntrySize : 16;
+ UINT32 CapOffset : 16;
+ UINT32 Attribute : 2;
+ UINT32 EntryBitMap : 8;
+ UINT32 Rsvd : 6;
+} PFS_ENTRY;
+
+//
+// HPM (Hierarchical Power Management) VSEC resource allocation info
+//
+typedef struct {
+ BOOLEAN HpmEnabled; // HPM enabled or not in BIOS knob
+ BOOLEAN HpmInfraReady; // All the HPM infrastructure data is buffered
+ UINT32 OobMsmHpmBarBase; // The base of OOBMSM BAR1 for HPM PFS and LUT tables
+ UINT32 OobMsmHpmBarLimit; // The limit of OOBMSM BAR1 from where the required size will be allocated
+ UINT32 OobMsmHpmBarMmcfgAddress; // The OOBMSM BAR1 MMCFG address
+ UINT32 OobMsmHpmBarRequiredSize; // The required size of OOBMSM BAR1
+
+ HPM_INFO HpmVsecInfo; // For now, single VSEC is assumed
+ PFS_ENTRY Pfs[MAX_HPM_PFS_ENTRY_NUM]; // The buffered PFS structure
+
+} HPM_VSEC_RESOURCE;
+
+typedef struct {
+ UINT32 StackPresentBitmap[MAX_SOCKET]; ///< bitmap of present stacks per socket
+ UINT8 StackBus[MAX_SOCKET][MAX_LOGIC_IIO_STACK];///< Bus of each stack
+ UINT32 StackMmiol[MAX_SOCKET][MAX_IIO_STACK]; ///< mmiol of each IIO stack, if it works as CXL, the mmiol base is RCRBBAR
+ UINT8 SocketFirstBus[MAX_SOCKET];
+ UINT8 Socket10nmUboxBus0[MAX_SOCKET]; //10nm CPU use only
+ UINT8 TotIoDie[MAX_SOCKET]; //GNR & SRF CPU use only
+ UINT8 TotCmpDie[MAX_SOCKET]; //GNR & SRF CPU use only
+ UINT8 SocketLastBus[MAX_SOCKET];
+ UINT8 segmentSocket[MAX_SOCKET];
+ UINT8 KtiPortCnt;
+ UINT32 socketPresentBitMap;
+ UINT32 FpgaPresentBitMap;
+ UINT32 mmCfgBase;
+ UINT64 SocketMmCfgBase[MAX_SOCKET];
+ UINT8 DdrMaxCh;
+ UINT8 DdrMaxImc; ///< Logical number of IMC count, ignoring logical holes
+ UINT8 DdrPhysicalMaxImc; ///< Physical number of IMC count from Capid
+ UINT8 DdrNumChPerMc;
+ UINT8 DdrNumPseudoChPerCh;
+ UINT8 imcEnabled[MAX_SOCKET][MAX_IMC];
+ UINT8 mcId[MAX_SOCKET][MAX_CH];
+ MRC_MST MemSsType[MAX_SOCKET]; ///< MemSsType global identifier for DDR vs. HBM
+ UINT32 MmioBar[MAX_SOCKET][TYPE_MAX_MMIO_BAR];
+ UINT8 HbmMaxCh;
+ UINT8 HbmMaxIoInst;
+ UINT8 HbmNumChPerMc;
+ UINT8 HbmNumChPerIo;
+ UINT32 LastCsrAddress[2];
+ UINT32 LastCsrMmioAddr;
+ UINT8 CsrCachingEnable;
+ UINT32 LastCsrMcAddress[2];
+ UINT32 LastCsrMcMmioPhyAddr;
+ UINT8 CsrPciBarCachingEnable;
+ UINT32 LastCsrPciBarAddr[2];
+ UINT64 LastCsrPciBarPhyAddr;
+ UINT32 LastSBPortId[MAX_SOCKET];
+ UPI_CONNECTION_TYPE UpiConnectionType[MAX_SOCKET];
+ BOOLEAN PostedCsrAccessAllowed; // SW is allowed to use posted CSR writes method when TRUE
+ BOOLEAN PostedWritesEnabled; // All CSR writes use posted method when TRUE, non-posted when FALSE
+ BOOLEAN DataPopulated; // CPU_CSR_ACCESS_VAR is unavailable when FALSE
+ HPM_VSEC_RESOURCE SocketHpmVsecRes[MAX_SOCKET]; // HPM VSEC info for all sockets
+ BOOLEAN HbmSku;
+ UINT64 Cxl1p1Rcrb[MAX_SOCKET][MAX_IIO_STACK]; // CXL 1.1 RCRB, one per PI5 stack
+ UINT64 CxlRbBar[MAX_SOCKET][MAX_IIO_STACK]; // CXL RBBAR, one per PI5 stack
+ UINT32 DmiRcrb[MAX_SOCKET]; // DMI RCRB region, one per socket
+ UINT8 FabricType; //Compute die 10x6, 10x5, and 6x5 type is stored
+ UINT8 ChopType; //Compute Die Chop Type
+ UINT8 MdfInstCount;
+ UINT32 UboxMmioSize;
+ UINT32 UboxScfMmioSize;
+ UINT64 PpinValue[MAX_SOCKET]; // The Protected Processor Inventory Number from CPU MSRs
+ UINT32 OobMsmPciBaseAddress[MAX_SOCKET];
+ UINT32 S3mControlRegisterBaseAddress[MAX_SOCKET];
+} CPU_CSR_ACCESS_VAR;
+
+typedef struct {
+ UINT32 MeRequestedSizeNv;
+ UINT32 MeRequestedAlignmentNv;
+ UINT8 SbspSocketIdNv;
+} SYS_INFO_VAR_NVRAM;
+
+typedef struct _CPUID_REGISTER_INFO {
+ UINT32 Eax;
+ UINT32 Ebx;
+ UINT32 Ecx;
+ UINT32 Edx;
+} CPUID_REGISTER_INFO;
+
+typedef struct _PROCESSOR_COMMON_INFO {
+ UINT32 capid0;
+ UINT32 capid1;
+ UINT32 capid2;
+ UINT32 capid3;
+ UINT32 capid4;
+ UINT32 capid5;
+ UINT32 capid6lo;
+ UINT32 capid6hi;
+ CPUID_REGISTER_INFO ExtCpuid7;
+ CPUID_REGISTER_INFO ExtCpuid1B;
+} PROCESSOR_COMMON_INFO;
+
+typedef struct {
+ UINT32 MeRequestedSize;
+ UINT32 MeRequestedAlignment;
+ UINT32 CheckPoint;
+ UINT8 ResetRequired;
+ UINT8 Emulation;
+ BOOT_MODE SysBootMode;
+ CPU_CSR_ACCESS_VAR CpuCsrAccessVarHost; // Common resource for CsrAccessRoutines
+ UINT64 CpuFreq;
+ UINT8 SocketId;
+ SYS_INFO_VAR_NVRAM SysInfoVarNvram;
+ BOOLEAN UsraTraceControl;
+ UINT16 UsraTraceConfiguration; // Bit 7 6 5 4 3:0
+ // Write, Modify, GetAddr, Long/Short, Trace 0x5 as signature
+ // Bit 15 14:11 10 9 8
+ // DumpCpuCsrAccessVar, TBD, CSR, PCIE, Read
+ BOOLEAN CpuCsrAccessVarInfoDumped;
+ PROCESSOR_COMMON_INFO ProcessorCommonInfo[MAX_SOCKET];
+ EFI_PHYSICAL_ADDRESS SocAddrMapData;
+ UINTN UsraPpiPtr;
+} SYSTEM_INFO_VAR;
+
+
+#pragma pack ()
+
+#endif //#ifndef _SYSTEM_INFO_HOB_H_