summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAmirah Abdul Rahim <amirah.abdul.rahim@intel.com>2025-06-19 11:12:42 +0300
committerAmirah Abdul Rahim <amirah.abdul.rahim@intel.com>2025-06-19 11:12:42 +0300
commit570ac0f5fa03a5ac273783c614948c63243f0728 (patch)
tree4d8bf179be3635e5e57cba6e58dfbcb905e05113
parent8681dceeca0f5756709bbb01c14fdaa3ccdffaad (diff)
downloadFSP-570ac0f5fa03a5ac273783c614948c63243f0728.tar.xz
Edge Platforms MTL-UH_MTL-PS MR3 (5124_47) FSP
Diffstat
-rw-r--r--MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.bsf164
-rw-r--r--MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.fdbin1245184 -> 1245184 bytes
-rw-r--r--MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspUpd.h2
-rw-r--r--MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspmUpd.h405
-rw-r--r--MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspsUpd.h1529
-rw-r--r--MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FsptUpd.h2
-rw-r--r--MeteorLakeFspBinPkg/IoT/MeteorLake/Include/MemInfoHob.h30
-rw-r--r--MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/VBT_MTL.bin (renamed from MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/Vbt.bin)bin7680 -> 7680 bytes
-rw-r--r--MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/Vbt_MTL.json1739
-rw-r--r--MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/Vbt_MTLS.binbin7680 -> 0 bytes
10 files changed, 2533 insertions, 1338 deletions
diff --git a/MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.bsf b/MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.bsf
index 96e6a83..e7b97c4 100644
--- a/MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.bsf
+++ b/MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.bsf
@@ -2,7 +2,7 @@
Boot Setting File for Platform Configuration.
- Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -213,7 +213,10 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_FreqLimitMaskEn 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_lp5GlitchWAEnable 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_TxVrefOverride 2 bytes $_DEFAULT_ = 0x0
- Skip 56 bytes
+ $gPlatformFspPkgTokenSpaceGuid_IsForceCkdBypass 1 bytes $_DEFAULT_ = 0x00
+ $gPlatformFspPkgTokenSpaceGuid_VendorForceDdr5G4 1 bytes $_DEFAULT_ = 0x0
+ $gPlatformFspPkgTokenSpaceGuid_Ddr5WrLvlMinLimit 1 bytes $_DEFAULT_ = 0x00
+ Skip 53 bytes
$gPlatformFspPkgTokenSpaceGuid_Vdd2Mv 2 bytes $_DEFAULT_ = 0x0000
$gPlatformFspPkgTokenSpaceGuid_RefClk 1 bytes $_DEFAULT_ = 0x00
Skip 1 bytes
@@ -270,7 +273,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_RxVrefOffset 2 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_MmioSizeAdjustment 2 bytes $_DEFAULT_ = 0
$gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay 1 bytes $_DEFAULT_ = 0x3
- Skip 1 bytes
+ $gPlatformFspPkgTokenSpaceGuid_IgdGsm2Size 1 bytes $_DEFAULT_ = 0xFF
$gPlatformFspPkgTokenSpaceGuid_GmAdr 4 bytes $_DEFAULT_ = 0xB0000000
$gPlatformFspPkgTokenSpaceGuid_GttMmAdr 4 bytes $_DEFAULT_ = 0xAF000000
$gPlatformFspPkgTokenSpaceGuid_TxtImplemented 1 bytes $_DEFAULT_ = 0x1
@@ -555,7 +558,16 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_RingPllCurrentRefTuningOffset 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_IaAtomPllCurrentRefTuningOffset 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PerCoreDisableConfiguration 1 bytes $_DEFAULT_ = 0x00
- Skip 76 bytes
+ $gPlatformFspPkgTokenSpaceGuid_NpuMaxOcRatio 1 bytes $_DEFAULT_ = 0x00
+ $gPlatformFspPkgTokenSpaceGuid_NpuVoltageMode 1 bytes $_DEFAULT_ = 0x00
+ $gPlatformFspPkgTokenSpaceGuid_NpuVoltageOverride 2 bytes $_DEFAULT_ = 0x00
+ $gPlatformFspPkgTokenSpaceGuid_NpuAdaptiveVoltage 2 bytes $_DEFAULT_ = 0x00
+ $gPlatformFspPkgTokenSpaceGuid_NpuVoltageOffset 2 bytes $_DEFAULT_ = 0x00
+ $gPlatformFspPkgTokenSpaceGuid_MaxVoltageLimitNew 18 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+ $gPlatformFspPkgTokenSpaceGuid_ForcePcoreResidency 1 bytes $_DEFAULT_ = 0x00
+ $gPlatformFspPkgTokenSpaceGuid_VrLimitBypass 1 bytes $_DEFAULT_ = 0x00
+ $gPlatformFspPkgTokenSpaceGuid_TurboThermalProtection 1 bytes $_DEFAULT_ = 0x01
+ Skip 47 bytes
$gPlatformFspPkgTokenSpaceGuid_BiosGuard 1 bytes $_DEFAULT_ = 0x01
Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_Txt 1 bytes $_DEFAULT_ = 0x00
@@ -758,7 +770,9 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionMask 16 bytes $_DEFAULT_ = 0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F,0xFF,0x3F
$gPlatformFspPkgTokenSpaceGuid_IbeccProtectedRegionOverallBase 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl 1 bytes $_DEFAULT_ = 0x0
- Skip 3 bytes
+ $gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl1Enable 1 bytes $_DEFAULT_ = 0x1
+ $gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl2Enable 1 bytes $_DEFAULT_ = 0x1
+ Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_IbeccEccInjAddrBase 4 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_IbeccEccInjAddrMask 4 bytes $_DEFAULT_ = 0xFFFFFFFF
$gPlatformFspPkgTokenSpaceGuid_IbeccEccInjCount 1 bytes $_DEFAULT_ = 0x1
@@ -855,12 +869,9 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_UsbTcPortEnPreMem 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PwDownMode 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort 2 bytes $_DEFAULT_ = 0x80
- $gPlatformFspPkgTokenSpaceGuid_I2cPostCodeEnable 1 bytes $_DEFAULT_ = 0x1
$gPlatformFspPkgTokenSpaceGuid_RMTLoopCount 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_CridEnable 1 bytes $_DEFAULT_ = 0x0
- Skip 1 bytes
$gPlatformFspPkgTokenSpaceGuid_PwDownIdleTimer 2 bytes $_DEFAULT_ = 0x00
- Skip 2 bytes
$gPlatformFspPkgTokenSpaceGuid_BclkRfiFreq 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_PcieImrSize 2 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PcieImrEnabled 1 bytes $_DEFAULT_ = 0x00
@@ -870,7 +881,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_DdrOneDpc 1 bytes $_DEFAULT_ = 0x03
$gPlatformFspPkgTokenSpaceGuid_OverrideDriverType 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_Lp5BypassVddqLimits 1 bytes $_DEFAULT_ = 0x00
- Skip 1 bytes
+ $gPlatformFspPkgTokenSpaceGuid_I2cPostCodeEnable 1 bytes $_DEFAULT_ = 0x1
$gPlatformFspPkgTokenSpaceGuid_VddqVoltageOverride 2 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_VccIogVoltageOverride 2 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_VccClkVoltageOverride 2 bytes $_DEFAULT_ = 0x00
@@ -946,7 +957,7 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_KtDeviceEnable 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_SkipCpuReplacementCheck 1 bytes $_DEFAULT_ = 0x00
Skip 100 bytes
- $gPlatformFspPkgTokenSpaceGuid_Avx2VoltageScaleFactor 1 bytes $_DEFAULT_ = 0x00
+ $gPlatformFspPkgTokenSpaceGuid_Avx2VoltageScaleFactor 1 bytes $_DEFAULT_ = 0x64
$gPlatformFspPkgTokenSpaceGuid_Avx512VoltageScaleFactor 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoUartDebugMode 1 bytes $_DEFAULT_ = 0x02
Skip 2 bytes
@@ -984,11 +995,12 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_GtVfPointCount 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_MrcTimeMeasure 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_MrcMustStaticSpdData 2 bytes $_DEFAULT_ = 0x00
- Skip 4 bytes
$gPlatformFspPkgTokenSpaceGuid_TmeExcludeBase 8 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_TmeExcludeSize 8 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_GenerateNewTmeKey 1 bytes $_DEFAULT_ = 0x0
$gPlatformFspPkgTokenSpaceGuid_CkdAddressTable 16 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+ $gPlatformFspPkgTokenSpaceGuid_ChannelToCkdQckMapping 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+ $gPlatformFspPkgTokenSpaceGuid_PhyClockToCkdDimm 8 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
Find "MTLUPD_S"
$gPlatformFspPkgTokenSpaceGuid_Revision 1 bytes $_DEFAULT_ = 0x02
@@ -1034,7 +1046,8 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDefaultCsOutput 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsMode 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsState 7 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- Skip 1 bytes
+ $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDelayRxClk 7 bytes $_DEFAULT_ = 0x00, 0x01, 0x02, 0x03, 0x00, 0x00, 0x00
+ Skip 2 bytes
$gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsPinMux 56 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoSpiClkPinMux 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
$gPlatformFspPkgTokenSpaceGuid_SerialIoSpiMisoPinMux 28 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
@@ -1115,12 +1128,10 @@ StructDef
$gPlatformFspPkgTokenSpaceGuid_PchTsn1MacAddressHigh 4 bytes $_DEFAULT_ = 0x00000000
$gPlatformFspPkgTokenSpaceGuid_PchTsn1MacAddressLow 4 bytes $_DEFAULT_ = 0x00000000
$gPlatformFspPkgTokenSpaceGuid_PciePtm 29 bytes $_DEFAULT_ = 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
- $gPlatformFspPkgTokenSpaceGuid_PcieMultiVc 29 bytes $_DEFAULT_ = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
- Skip 2 bytes
$gPlatformFspPkgTokenSpaceGuid_DmiPowerGatingDis 1 bytes $_DEFAULT_ = 0x01
Skip 28 bytes
$gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming 1 bytes $_DEFAULT_ = 0x01
- Skip 6 bytes
+ Skip 5 bytes
$gPlatformFspPkgTokenSpaceGuid_PmcPowerButtonDebounce 4 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_PchEspiBmeHostDeviceEnabled 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_PchEspiLockLinkConfiguration 1 bytes $_DEFAULT_ = 0x01
@@ -1207,8 +1218,7 @@ StructDef
Skip 2 bytes
$gPlatformFspPkgTokenSpaceGuid_VbtSize 4 bytes $_DEFAULT_ = 0x00000000
$gPlatformFspPkgTokenSpaceGuid_LidStatus 1 bytes $_DEFAULT_ = 0x0
- $gPlatformFspPkgTokenSpaceGuid_SaPostMemRsvd 7 bytes $_DEFAULT_ = 0x00
- $gPlatformFspPkgTokenSpaceGuid_SaXdciIrq 1 bytes $_DEFAULT_ = 0x23
+ $gPlatformFspPkgTokenSpaceGuid_SaPostMemRsvd 8 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_VmdEnable 1 bytes $_DEFAULT_ = 0x01
$gPlatformFspPkgTokenSpaceGuid_VmdGlobalMapping 1 bytes $_DEFAULT_ = 0x00
$gPlatformFspPkgTokenSpaceGuid_VmdPort 31 bytes $_DEFAULT_ = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
@@ -2150,6 +2160,26 @@ List &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay
Selection 4 , "Hybrid Graphics"
EndList
+List &gPlatformFspPkgTokenSpaceGuid_IgdGsm2Size
+ Selection 0 , "2GB"
+ Selection 1 , "4GB"
+ Selection 2 , "6GB"
+ Selection 3 , "8GB"
+ Selection 4 , "10GB"
+ Selection 5 , "12GB"
+ Selection 6 , "14GB"
+ Selection 7 , "16GB"
+ Selection 8 , "18GB"
+ Selection 9 , "20GB"
+ Selection 10 , "22GB"
+ Selection 11 , "24GB"
+ Selection 12 , "26GB"
+ Selection 13 , "28GB"
+ Selection 14 , "30GB"
+ Selection 15 , "32GB"
+ Selection 0xFF , "No Allocation"
+EndList
+
List &gPlatformFspPkgTokenSpaceGuid_GtVoltageMode
Selection 0 , " Adaptive"
Selection 1 , " Override"
@@ -2320,6 +2350,11 @@ List &gPlatformFspPkgTokenSpaceGuid_EnableFastVmode
Selection 1 , " Enable"
EndList
+List &gPlatformFspPkgTokenSpaceGuid_TurboThermalProtection
+ Selection 1 , "Enable"
+ Selection 0 , "Disable"
+EndList
+
List &gPlatformFspPkgTokenSpaceGuid_PchHdaVcType
Selection 0 , " VC0"
Selection 1 , " VC1"
@@ -2422,6 +2457,16 @@ List &gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl
Selection 7 , "Inject Uncorrectable Error on insertion counter"
EndList
+List &gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl1Enable
+ Selection 0 , " Disabled"
+ Selection 1 , "Enabled"
+EndList
+
+List &gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl2Enable
+ Selection 0 , " Disabled"
+ Selection 1 , "Enabled"
+EndList
+
List &gPlatformFspPkgTokenSpaceGuid_RhSelect
Selection 0 , "Disable"
Selection 1 , "RFM"
@@ -3192,6 +3237,13 @@ Page "Memory Reference Code"
EditNum $gPlatformFspPkgTokenSpaceGuid_TxVrefOverride, "Initial DDR5 TxVref Override", DEC,
Help "Override for initial DDR5 TxVref value , 0 = Auto (default), valid range from 350 to 975, in increments of 5"
"Valid range: 0 ~ 975"
+ Combo $gPlatformFspPkgTokenSpaceGuid_IsForceCkdBypass, "Force CKD in Bypass Mode", &EN_DIS,
+ Help "Enable/Disable Force CKD in Bypass Mode"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_VendorForceDdr5G4, "VendorForceDdr5G4", HEX,
+ Help "Default = 0. Range from 0-2"
+ "Valid range: 0x0 ~ 0x10"
+ Combo $gPlatformFspPkgTokenSpaceGuid_Ddr5WrLvlMinLimit, "Increase External Coarse WrLvl sweep", &EN_DIS,
+ Help "Enable/Disable Increase two extra clocks to External Coarse WrLvl sweep"
Combo $gPlatformFspPkgTokenSpaceGuid_Vdd2Mv, "Vdd2Mv", &gPlatformFspPkgTokenSpaceGuid_Vdd2Mv,
Help "VDD2 in MilliVolts. <b>0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc. "
Combo $gPlatformFspPkgTokenSpaceGuid_RefClk, "Memory Reference Clock", &gPlatformFspPkgTokenSpaceGuid_RefClk,
@@ -3322,6 +3374,8 @@ Page "Memory Reference Code"
"Valid range: 0 ~ 0xFFFF"
Combo $gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay, "Selection of the primary display device", &gPlatformFspPkgTokenSpaceGuid_PrimaryDisplay,
Help "0=iGFX, 3(Default)=AUTO, 4=Hybrid Graphics"
+ Combo $gPlatformFspPkgTokenSpaceGuid_IgdGsm2Size, "Internal Graphics Data Stolen Memory GSM2", &gPlatformFspPkgTokenSpaceGuid_IgdGsm2Size,
+ Help "Size of memory preallocated for internal graphics GSM2."
EditNum $gPlatformFspPkgTokenSpaceGuid_GmAdr, "Temporary MMIO address for GMADR", HEX,
Help "Obsolete field now and it has been extended to 64 bit address, used LMemBar "
"Valid range: 0x00 ~ 0xFFFFFFFF"
@@ -3849,7 +3903,7 @@ Page "Memory Reference Code"
Help "Core PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15"
"Valid range: 0x00 ~ 0x0F"
EditNum $gPlatformFspPkgTokenSpaceGuid_RingPllCurrentRefTuningOffset, "Ring PLL Current Reference Tuning Offset", HEX,
- Help "Ring PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15"
+ Help "DEPRECATED. Ring PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15"
"Valid range: 0x00 ~ 0x0F"
EditNum $gPlatformFspPkgTokenSpaceGuid_IaAtomPllCurrentRefTuningOffset, "IaAtom PLL Current Reference Tuning Offset", HEX,
Help "IaAtom PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15"
@@ -3857,6 +3911,29 @@ Page "Memory Reference Code"
EditNum $gPlatformFspPkgTokenSpaceGuid_PerCoreDisableConfiguration, "Per Core Disable Configuration", HEX,
Help "This configuration can be used only when OC is enabled,user can either use legacy num of cores option or the OC specific per core disable configuration. <b>0: Disable</b>, 1: Enable"
"Valid range: 0x0 ~ 0x1"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_NpuMaxOcRatio, "Maximum Npu turbo ratio override", HEX,
+ Help "DEPRECATED. Maximum Npu turbo ratio override allows to increase NPU frequency beyond the fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-120"
+ "Valid range: 0x00 ~ 0x55"
+ Combo $gPlatformFspPkgTokenSpaceGuid_NpuVoltageMode, "NPU voltage mode", &EN_DIS,
+ Help "DEPRECATED. NPU voltage mode; <b>0: Adaptive</b>; 1: Override."
+ EditNum $gPlatformFspPkgTokenSpaceGuid_NpuVoltageOverride, "NPU voltage override", HEX,
+ Help "DEPRECATED. The NPU voltage override which is applied to the entire range of cpu NPU frequencies. Valid Range 0 to 2000"
+ "Valid range: 0x00 ~ 0x7D0"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_NpuAdaptiveVoltage, "adaptive voltage applied during turbo frequencies", HEX,
+ Help "DEPRECATED. 0(Default)=Minimal, 2000=Maximum"
+ "Valid range: 0x00 ~ 0x7D0"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_NpuVoltageOffset, "NPU Turbo voltage Offset", HEX,
+ Help "DEPRECATED. The voltage offset applied to the NPU while operating in turbo mode. Valid Range 0 to 1000"
+ "Valid range: 0x00 ~ 0x3E8"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_MaxVoltageLimitNew, "OC Max Voltage limits", HEX,
+ Help "DEPRECATED. OC Max Voltage limits"
+ "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
+ Combo $gPlatformFspPkgTokenSpaceGuid_ForcePcoreResidency, "Force Pcore Residency", &EN_DIS,
+ Help "Enable/Disable Force Pcore Residency. <b>0: Disable</b>; 1: Enable."
+ Combo $gPlatformFspPkgTokenSpaceGuid_VrLimitBypass, "VR Limit Bypass", &EN_DIS,
+ Help "Enable/Disable VR Limit Bypass. <b>0: Disable</b>; 1: Enable."
+ Combo $gPlatformFspPkgTokenSpaceGuid_TurboThermalProtection, "Turbo Thermal Protection", &gPlatformFspPkgTokenSpaceGuid_TurboThermalProtection,
+ Help "This control allow user to disable Turbo Thermal Protection (TTP) for overclocking. <b>1: Enable</b>; 0: Disable"
Combo $gPlatformFspPkgTokenSpaceGuid_BiosGuard, "BiosGuard", &EN_DIS,
Help "Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable"
Combo $gPlatformFspPkgTokenSpaceGuid_Txt, "Txt", &EN_DIS,
@@ -4060,6 +4137,10 @@ Page "Memory Reference Code"
"Valid range: 0x00 ~ 0xFFFF"
Combo $gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl, "IbeccEccInjControl", &gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl,
Help "IBECC Error Injection Control"
+ Combo $gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl1Enable, "IbeccEccInjControl1Enable", &gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl1Enable,
+ Help "IBECC Error Injection Control"
+ Combo $gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl2Enable, "IbeccEccInjControl2Enable", &gPlatformFspPkgTokenSpaceGuid_IbeccEccInjControl2Enable,
+ Help "IBECC Error Injection Control"
EditNum $gPlatformFspPkgTokenSpaceGuid_IbeccEccInjAddrBase, "IbeccEccInjAddrBase", HEX,
Help "Address to match against for ECC error injection. Example: 1 = 32MB, 2 = 64MB"
"Valid range: 0x00 ~ 0x1FFFFFFFF"
@@ -4308,8 +4389,6 @@ Page "Memory Reference Code"
EditNum $gPlatformFspPkgTokenSpaceGuid_PostCodeOutputPort, "Post Code Output Port", HEX,
Help "This option configures Post Code Output Port"
"Valid range: 0x0 ~ 0xFFFF"
- Combo $gPlatformFspPkgTokenSpaceGuid_I2cPostCodeEnable, "Enable/Disable I2cPostcode", &EN_DIS,
- Help "Enable (Default): Postcode via I2C, Disable: Postcode via Port80"
EditNum $gPlatformFspPkgTokenSpaceGuid_RMTLoopCount, "RMTLoopCount", HEX,
Help "Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO"
"Valid range: 0 ~ 0x20"
@@ -4341,6 +4420,8 @@ Page "Memory Reference Code"
EditNum $gPlatformFspPkgTokenSpaceGuid_Lp5BypassVddqLimits, "Lp5 Bypass Vddq Limits", HEX,
Help "Bypass Lp5 Vccddq Fuse limits. Advised to keep disabled"
"Valid range: 0x0 ~ 0x1"
+ Combo $gPlatformFspPkgTokenSpaceGuid_I2cPostCodeEnable, "Enable/Disable I2cPostcode", &EN_DIS,
+ Help "Enable (Default): Postcode via I2C, Disable: Postcode via Port80"
EditNum $gPlatformFspPkgTokenSpaceGuid_VddqVoltageOverride, "Vddq Voltage Override for CMOS", HEX,
Help "# is multiple of 1mV where 0 means Auto."
"Valid range: 0x00 ~ 0xFFFF"
@@ -4788,7 +4869,7 @@ Page "PCH(PreMem)"
Help "The voltage offset applied to the memory while operating in turbo mode. Valid Range 0 to 1000"
"Valid range: 0x00 ~ 0x3E8"
Combo $gPlatformFspPkgTokenSpaceGuid_CpuDlvrMode, "Select Core(s) and RING DLVR Mode", &gPlatformFspPkgTokenSpaceGuid_CpuDlvrMode,
- Help "Select Core(s) and RING DLVR Mode). <b>0: Regulation Mode</b>; 1: Power Gate Mode"
+ Help "DEPRECATED. Select Core(s) and RING DLVR Mode). <b>0: Regulation Mode</b>; 1: Power Gate Mode"
EditNum $gPlatformFspPkgTokenSpaceGuid_NguMaxOcRatio, "Maximum clr turbo ratio override", HEX,
Help "Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85"
"Valid range: 0x00 ~ 0x55"
@@ -4850,6 +4931,12 @@ Page "PCH(PreMem)"
EditNum $gPlatformFspPkgTokenSpaceGuid_CkdAddressTable, "CkdAddress Tabl", HEX,
Help "Specify CKD Address table for CH0D0/CH0D1/CH1D0&CH1D1"
"Valid range: 0x00 ~ 0xFFFFFFFF"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_ChannelToCkdQckMapping, "Channel to CKD QCK Mapping", HEX,
+ Help "Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1"
+ "Valid range: 0x00 ~ 0xFF"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_PhyClockToCkdDimm, "DDRIO Clock to CKD DIMM", HEX,
+ Help "Specify DDRIO Clock to CKD DIMM for CH0D0/CH0D1/CH1D0&CH1D1"
+ "Valid range: 0x00 ~ 0xFF"
EndPage
Page "System Agent(PostMem)"
@@ -4912,6 +4999,33 @@ Page "System Agent(PostMem)"
Help "LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen."
Combo $gPlatformFspPkgTokenSpaceGuid_SaPostMemRsvd, "PchPostMemRsvd", &EN_DIS,
Help "Reserved for PCH Post-Mem"
+ Combo $gPlatformFspPkgTokenSpaceGuid_VmdEnable, "Enable VMD controller", &EN_DIS,
+ Help "Enable/disable to VMD controller.0: Disable; 1: Enable(Default)"
+ Combo $gPlatformFspPkgTokenSpaceGuid_VmdGlobalMapping, "Enable VMD Global Mapping", &EN_DIS,
+ Help "Enable/disable to VMD controller.0: Disable(Default); 1: Enable"
+ Combo $gPlatformFspPkgTokenSpaceGuid_VmdPort, "Map port under VMD", &EN_DIS,
+ Help "Map/UnMap port under VMD"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_VmdPortBus, "VMD Port Bus", DEC,
+ Help "VMD Root port bus number."
+ "Valid range: 0 ~ 255"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_VmdPortDev, "VMD Port Device", DEC,
+ Help "VMD Root port device number."
+ "Valid range: 0 ~ 31"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_VmdPortFunc, "VMD Port Func", DEC,
+ Help "VMD Root port function number."
+ "Valid range: 0 ~ 7"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_VmdVariablePtr, "VMD Variable", HEX,
+ Help "VMD Variable Pointer."
+ "Valid range: 0x00 ~ 0xFFFFFFFF"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_VmdCfgBarBase, "Temporary CfgBar address for VMD", HEX,
+ Help "VMD Variable Pointer."
+ "Valid range: 0x00 ~ 0xFFFFFFFF"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_VmdMemBar1Base, "Temporary MemBar1 address for VMD", HEX,
+ Help "VMD Variable Pointer."
+ "Valid range: 0x00 ~ 0xFFFFFFFF"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_VmdMemBar2Base, "Temporary MemBar2 address for VMD", HEX,
+ Help "VMD Variable Pointer."
+ "Valid range: 0x00 ~ 0xFFFFFFFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_BgpdtHash, "BgpdtHash[4]", HEX,
Help "BgpdtHash values"
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
@@ -5339,6 +5453,9 @@ Page "PCH(PostMem)"
EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsState, "SPIn Default Chip Select State Low/High", HEX,
Help "Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... Available options: 0:Low, 1:High"
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF"
+ EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiDelayRxClk, "SPIn Delayed Rx Clock setting", HEX,
+ Help "00:default, 01:Internal, 10:NegEdge Tx Clock, 11:NegEdge Delayed Rx Clk. Configure Delayed Rx Clock"
+ "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFF"
EditNum $gPlatformFspPkgTokenSpaceGuid_SerialIoSpiCsPinMux, "Serial IO SPI CS Pin Muxing", HEX,
Help "Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* for possible values."
"Valid range: 0 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
@@ -5549,9 +5666,6 @@ Page "PCH(PostMem)"
EditNum $gPlatformFspPkgTokenSpaceGuid_PciePtm, "PCIe PTM enable/disable", HEX,
Help "Enable/disable Precision Time Measurement for PCIE Root Ports."
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
- EditNum $gPlatformFspPkgTokenSpaceGuid_PcieMultiVc, "Multi-VC for PCIE RP Mask", HEX,
- Help "Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on."
- "Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"
Combo $gPlatformFspPkgTokenSpaceGuid_DmiPowerGatingDis, "Disable DMI Power Gating", &EN_DIS,
Help "Enable/disable DMI Power Gating Disable."
Combo $gPlatformFspPkgTokenSpaceGuid_UsbPdoProgramming, "USB PDO Programming", &EN_DIS,
@@ -5763,7 +5877,7 @@ Page "PCH(PostMem)"
"Valid range: 0x00 ~ 0xFFFFFFFFFFFFFFFF"
Combo $gPlatformFspPkgTokenSpaceGuid_PchIshPdtUnlock, "PCH ISH PDT Unlock Msg", &EN_DIS,
Help "0: False; 1: True."
- Combo $gPlatformFspPkgTokenSpaceGuid_PchIshMsiInterrupt, "PCH ISH MSI Interrupts", &EN_DIS,
+ Combo $gPlatformFspPkgTokenSpaceGuid_PchIshMsiInterrupt, "PCH ISH Disable MSI Interrupts", &EN_DIS,
Help "0: False; 1: True."
Combo $gPlatformFspPkgTokenSpaceGuid_PchLanLtrEnable, "Enable PCH Lan LTR capabilty of PCH internal LAN", &EN_DIS,
Help "0: Disable; 1: Enable."
diff --git a/MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.fd b/MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.fd
index 0fa6acc..02ba392 100644
--- a/MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.fd
+++ b/MeteorLakeFspBinPkg/IoT/MeteorLake/Fsp.fd
Binary files differ
diff --git a/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspUpd.h b/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspUpd.h
index f07ee2f..8cec707 100644
--- a/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspUpd.h
+++ b/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
diff --git a/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspmUpd.h b/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspmUpd.h
index e5b46b0..3eb3846 100644
--- a/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspmUpd.h
+++ b/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspmUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -857,9 +857,26 @@ typedef struct {
**/
UINT16 TxVrefOverride;
-/** Offset 0x01C8
+/** Offset 0x01C8 - Force CKD in Bypass Mode
+ Enable/Disable Force CKD in Bypass Mode
+ $EN_DIS
+**/
+ UINT8 IsForceCkdBypass;
+
+/** Offset 0x01C9 - VendorForceDdr5G4
+ Default = 0. Range from 0-2
+**/
+ UINT8 VendorForceDdr5G4;
+
+/** Offset 0x01CA - Increase External Coarse WrLvl sweep
+ Enable/Disable Increase two extra clocks to External Coarse WrLvl sweep
+ $EN_DIS
+**/
+ UINT8 Ddr5WrLvlMinLimit;
+
+/** Offset 0x01CB
**/
- UINT8 Rsvd036[56];
+ UINT8 Rsvd036[53];
/** Offset 0x0200 - Vdd2Mv
VDD2 in MilliVolts. <b>0=Platform Default (no override), 1200=1.2V, 1350=1.35V etc.
@@ -1182,9 +1199,12 @@ typedef struct {
**/
UINT8 PrimaryDisplay;
-/** Offset 0x028F
+/** Offset 0x028F - Internal Graphics Data Stolen Memory GSM2
+ Size of memory preallocated for internal graphics GSM2.
+ 0:2GB, 1:4GB, 2:6GB, 3:8GB, 4:10GB, 5:12GB, 6:14GB, 7:16GB, 8:18GB, 9:20GB, 10:22GB,
+ 11:24GB, 12:26GB, 13:28GB, 14:30GB, 15:32GB, 0xFF:No Allocation
**/
- UINT8 Rsvd060[1];
+ UINT8 IgdGsm2Size;
/** Offset 0x0290 - Temporary MMIO address for GMADR
Obsolete field now and it has been extended to 64 bit address, used LMemBar
@@ -2898,7 +2918,7 @@ typedef struct {
UINT8 CorePllCurrentRefTuningOffset;
/** Offset 0x07B5 - Ring PLL Current Reference Tuning Offset
- Ring PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15
+ DEPRECATED. Ring PLL Current Reference Tuning Offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 RingPllCurrentRefTuningOffset;
@@ -2913,9 +2933,62 @@ typedef struct {
**/
UINT8 PerCoreDisableConfiguration;
-/** Offset 0x07B8
+/** Offset 0x07B8 - Maximum Npu turbo ratio override
+ DEPRECATED. Maximum Npu turbo ratio override allows to increase NPU frequency beyond
+ the fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-120
+**/
+ UINT8 NpuMaxOcRatio;
+
+/** Offset 0x07B9 - NPU voltage mode
+ DEPRECATED. NPU voltage mode; <b>0: Adaptive</b>; 1: Override.
+ $EN_DIS
+**/
+ UINT8 NpuVoltageMode;
+
+/** Offset 0x07BA - NPU voltage override
+ DEPRECATED. The NPU voltage override which is applied to the entire range of cpu
+ NPU frequencies. Valid Range 0 to 2000
+**/
+ UINT16 NpuVoltageOverride;
+
+/** Offset 0x07BC - adaptive voltage applied during turbo frequencies
+ DEPRECATED. 0(Default)=Minimal, 2000=Maximum
+**/
+ UINT16 NpuAdaptiveVoltage;
+
+/** Offset 0x07BE - NPU Turbo voltage Offset
+ DEPRECATED. The voltage offset applied to the NPU while operating in turbo mode.
+ Valid Range 0 to 1000
+**/
+ UINT16 NpuVoltageOffset;
+
+/** Offset 0x07C0 - OC Max Voltage limits
+ DEPRECATED. OC Max Voltage limits
+**/
+ UINT16 MaxVoltageLimitNew[9];
+
+/** Offset 0x07D2 - Force Pcore Residency
+ Enable/Disable Force Pcore Residency. <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 ForcePcoreResidency;
+
+/** Offset 0x07D3 - VR Limit Bypass
+ Enable/Disable VR Limit Bypass. <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
**/
- UINT8 CpuFspmUpdRsvd[76];
+ UINT8 VrLimitBypass;
+
+/** Offset 0x07D4 - Turbo Thermal Protection
+ This control allow user to disable Turbo Thermal Protection (TTP) for overclocking.
+ <b>1: Enable</b>; 0: Disable
+ 1:Enable, 0:Disable
+**/
+ UINT8 TurboThermalProtection;
+
+/** Offset 0x07D5
+**/
+ UINT8 CpuFspmUpdRsvd[47];
/** Offset 0x0804 - BiosGuard
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
@@ -4044,9 +4117,21 @@ typedef struct {
**/
UINT8 IbeccEccInjControl;
-/** Offset 0x0BE5
+/** Offset 0x0BE5 - IbeccEccInjControl1Enable
+ IBECC Error Injection Control
+ 0: Disabled, 1:Enabled
+**/
+ UINT8 IbeccEccInjControl1Enable;
+
+/** Offset 0x0BE6 - IbeccEccInjControl2Enable
+ IBECC Error Injection Control
+ 0: Disabled, 1:Enabled
+**/
+ UINT8 IbeccEccInjControl2Enable;
+
+/** Offset 0x0BE7
**/
- UINT8 UnusedUpdSpace0[3];
+ UINT8 UnusedUpdSpace0;
/** Offset 0x0BE8 - IbeccEccInjAddrBase
Address to match against for ECC error injection. Example: 1 = 32MB, 2 = 64MB
@@ -4584,67 +4669,53 @@ typedef struct {
**/
UINT16 PostCodeOutputPort;
-/** Offset 0x0C58 - Enable/Disable I2cPostcode
- Enable (Default): Postcode via I2C, Disable: Postcode via Port80
- $EN_DIS
-**/
- UINT8 I2cPostCodeEnable;
-
-/** Offset 0x0C59 - RMTLoopCount
+/** Offset 0x0C58 - RMTLoopCount
Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
**/
UINT8 RMTLoopCount;
-/** Offset 0x0C5A - Enable/Disable SA CRID
+/** Offset 0x0C59 - Enable/Disable SA CRID
Enable: SA CRID, Disable (Default): SA CRID
$EN_DIS
**/
UINT8 CridEnable;
-/** Offset 0x0C5B
-**/
- UINT8 UnusedUpdSpace3;
-
-/** Offset 0x0C5C - Pwr Down Idle Timer
+/** Offset 0x0C5A - Pwr Down Idle Timer
Default 0 = AUTO. Range is 30 to 2000(in us)
**/
UINT16 PwDownIdleTimer;
-/** Offset 0x0C5E
-**/
- UINT8 UnusedUpdSpace4[2];
-
-/** Offset 0x0C60 - BCLK RFI Frequency
+/** Offset 0x0C5C - BCLK RFI Frequency
Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
RFI Tuning</b>. Range is 98Mhz-100Mhz.
**/
UINT32 BclkRfiFreq[4];
-/** Offset 0x0C70 - Size of PCIe IMR.
+/** Offset 0x0C6C - Size of PCIe IMR.
Size of PCIe IMR in megabytes
**/
UINT16 PcieImrSize;
-/** Offset 0x0C72 - Enable PCIe IMR
+/** Offset 0x0C6E - Enable PCIe IMR
0: Disable(AUTO), 1: Enable
$EN_DIS
**/
UINT8 PcieImrEnabled;
-/** Offset 0x0C73 - Enable PCIe IMR
+/** Offset 0x0C6F - Enable PCIe IMR
1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select
the Root port location from PCH PCIe or SA PCIe
$EN_DIS
**/
UINT8 PcieImrRpLocation;
-/** Offset 0x0C74 - Root port number for IMR.
+/** Offset 0x0C70 - Root port number for IMR.
Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port
from 0 to 23 and if it is SA PCIe then select root port from 0 to 3
**/
UINT8 PcieImrRpSelection;
-/** Offset 0x0C75 - SerialDebugMrcLevel
+/** Offset 0x0C71 - SerialDebugMrcLevel
MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose.
@@ -4653,104 +4724,106 @@ typedef struct {
**/
UINT8 SerialDebugMrcLevel;
-/** Offset 0x0C76 - DdrOneDpc
+/** Offset 0x0C72 - DdrOneDpc
DDR 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only,
or on both (default)
0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled
**/
UINT8 DdrOneDpc;
-/** Offset 0x0C77 - Override Driver Type
+/** Offset 0x0C73 - Override Driver Type
Override Driver Type. 0=Auto, 1=CMOS, 2=NMOS
**/
UINT8 OverrideDriverType;
-/** Offset 0x0C78 - Lp5 Bypass Vddq Limits
+/** Offset 0x0C74 - Lp5 Bypass Vddq Limits
Bypass Lp5 Vccddq Fuse limits. Advised to keep disabled
**/
UINT8 Lp5BypassVddqLimits;
-/** Offset 0x0C79
+/** Offset 0x0C75 - Enable/Disable I2cPostcode
+ Enable (Default): Postcode via I2C, Disable: Postcode via Port80
+ $EN_DIS
**/
- UINT8 Rsvd320[1];
+ UINT8 I2cPostCodeEnable;
-/** Offset 0x0C7A - Vddq Voltage Override for CMOS
+/** Offset 0x0C76 - Vddq Voltage Override for CMOS
# is multiple of 1mV where 0 means Auto.
**/
UINT16 VddqVoltageOverride;
-/** Offset 0x0C7C - VccIog Voltage Override
+/** Offset 0x0C78 - VccIog Voltage Override
# is multiple of 1mV where 0 means Auto.
**/
UINT16 VccIogVoltageOverride;
-/** Offset 0x0C7E - VccClk Voltage Override
+/** Offset 0x0C7A - VccClk Voltage Override
# is multiple of 1mV where 0 means Auto.
**/
UINT16 VccClkVoltageOverride;
-/** Offset 0x0C80 - Extended Bank Hashing
+/** Offset 0x0C7C - Extended Bank Hashing
Eanble/Disable ExtendedBankHashing
$EN_DIS
**/
UINT8 ExtendedBankHashing;
-/** Offset 0x0C81 - RH pTRR LFSR1 Mask
+/** Offset 0x0C7D - RH pTRR LFSR1 Mask
Row Hammer pTRR LFSR1 Mask, 1/2^(value)
**/
UINT8 Lfsr1Mask;
-/** Offset 0x0C82 - Refresh Watermarks
+/** Offset 0x0C7E - Refresh Watermarks
Refresh Watermarks: 0-Low, 1-High (default)
0:Set Refresh Watermarks to Low, 1:Set Refresh Watermarks to High (Default)
**/
UINT8 RefreshWm;
-/** Offset 0x0C83 - Command Pins Mapping
+/** Offset 0x0C7F - Command Pins Mapping
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
**/
UINT8 Lp5CccConfig;
-/** Offset 0x0C84 - Command Pins Mirrored
+/** Offset 0x0C80 - Command Pins Mirrored
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
**/
UINT8 CmdMirror;
-/** Offset 0x0C85 - Skip override boot mode When Fw Update.
+/** Offset 0x0C81 - Skip override boot mode When Fw Update.
When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, skip setting boot mode to
BOOT_WITH_FULL_CONFIGURATION in PEI memory init.
$EN_DIS
**/
UINT8 SiSkipOverrideBootModeWhenFwUpdate;
-/** Offset 0x0C86 - Opportunistic Self Refresh IdleTimer
+/** Offset 0x0C82 - Opportunistic Self Refresh IdleTimer
Default 0 = AUTO. Range is 500 to 10000(in us)
**/
UINT16 OppSrefIdleTmr;
-/** Offset 0x0C88 - LowerBasicMemTestSize
+/** Offset 0x0C84 - LowerBasicMemTestSize
Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 LowerBasicMemTestSize;
-/** Offset 0x0C89 - Board Topology
+/** Offset 0x0C85 - Board Topology
0: Daisy, 1: Tee
**/
UINT8 BoardTopology;
-/** Offset 0x0C8A - RxDqsDelayTempCoeff
+/** Offset 0x0C86 - RxDqsDelayTempCoeff
Default = 4. Range from 0-255
**/
UINT8 RxDqsDelayTempCoeff;
-/** Offset 0x0C8B
+/** Offset 0x0C87
**/
UINT8 MrcFspmUpdRsvd[15];
-/** Offset 0x0C9A - PPR Test Type
+/** Offset 0x0C96 - PPR Test Type
Select memory tests used in Post Package Repair flow. This option is only valid
if PPR=1, otherwise ignored. Bit 0: WCMATS8 test, Bit 1: Data Retention test, Bit
2: X March test, Bit 3: X March G test, Bit 4: Y March Short test, Bit 5: Y March
@@ -4758,414 +4831,414 @@ typedef struct {
**/
UINT8 PprTestType;
-/** Offset 0x0C9B - PreMemRsvd
+/** Offset 0x0C97 - PreMemRsvd
Reserved for Pre-Mem
$EN_DIS
**/
UINT8 ReservedFspmUpd[2];
-/** Offset 0x0C9D - Skip external display device scanning
+/** Offset 0x0C99 - Skip external display device scanning
Enable: Do not scan for external display device, Disable (Default): Scan external
display devices
$EN_DIS
**/
UINT8 SkipExtGfxScan;
-/** Offset 0x0C9E - Generate BIOS Data ACPI Table
+/** Offset 0x0C9A - Generate BIOS Data ACPI Table
Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
$EN_DIS
**/
UINT8 BdatEnable;
-/** Offset 0x0C9F - Lock PCU Thermal Management registers
+/** Offset 0x0C9B - Lock PCU Thermal Management registers
Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
$EN_DIS
**/
UINT8 LockPTMregs;
-/** Offset 0x0CA0 - Panel Power Enable
+/** Offset 0x0C9C - Panel Power Enable
Control for enabling/disabling VDD force bit (Required only for early enabling of
eDP panel). 0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 PanelPowerEnable;
-/** Offset 0x0CA1 - BdatTestType
+/** Offset 0x0C9D - BdatTestType
Indicates the type of Memory Training data to populate into the BDAT ACPI table.
0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
**/
UINT8 BdatTestType;
-/** Offset 0x0CA2
+/** Offset 0x0C9E
**/
UINT8 Rsvd330[2];
-/** Offset 0x0CA4 - PMR Size
+/** Offset 0x0CA0 - PMR Size
Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
**/
UINT32 DmaBufferSize;
-/** Offset 0x0CA8 - The policy for VTd driver behavior
+/** Offset 0x0CA4 - The policy for VTd driver behavior
BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS
**/
UINT8 PreBootDmaMask;
-/** Offset 0x0CA9
+/** Offset 0x0CA5
**/
UINT8 Rsvd340[1];
-/** Offset 0x0CAA - Delta T12 Power Cycle Delay required in ms
+/** Offset 0x0CA6 - Delta T12 Power Cycle Delay required in ms
Select the value for delay required. 0= No delay, 0xFFFF(Default) = Auto calculate
T12 Delay to max 500ms
0 : No Delay, 0xFFFF : Auto Calulate T12 Delay
**/
UINT16 DeltaT12PowerCycleDelay;
-/** Offset 0x0CAC - HgSubSystemId
+/** Offset 0x0CA8 - HgSubSystemId
Hybrid Graphics SubSystemId
**/
UINT16 HgSubSystemId;
-/** Offset 0x0CAE - Platform LID Status for LFP Displays.
+/** Offset 0x0CAA - Platform LID Status for LFP Displays.
LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
0: LidClosed, 1: LidOpen
**/
UINT8 LidStatus;
-/** Offset 0x0CAF - Control VGA Initialition sequence
+/** Offset 0x0CAB - Control VGA Initialition sequence
Initialise VGA Init, Set BIT0 - 0 (No VGA Support), BIT0 = 1 (VGA Supported) BIT1
= 1 (VGA Exit)
0x0: NO VGA Init, 0x1: VGA Init, 0x3: VGA Init and VGA Exit
**/
UINT8 VgaInitControl;
-/** Offset 0x0CB0 - Graphics Configuration Ptr
+/** Offset 0x0CAC - Graphics Configuration Ptr
Points to VBT
**/
UINT32 VbtPtr;
-/** Offset 0x0CB4 - Intel Graphics VBT (Video BIOS Table) Size
+/** Offset 0x0CB0 - Intel Graphics VBT (Video BIOS Table) Size
Size of Graphics VBT Image
**/
UINT32 VbtSize;
-/** Offset 0x0CB8 - VGA Training Message Pointer
+/** Offset 0x0CB4 - VGA Training Message Pointer
Points to VGA Message Array
**/
UINT32 VgaMessage;
-/** Offset 0x0CBC - SaPreMemTestRsvd
+/** Offset 0x0CB8 - SaPreMemTestRsvd
Reserved for SA Pre-Mem Test
$EN_DIS
**/
UINT8 SaPreMemTestRsvd[75];
-/** Offset 0x0D07 - PPR Run Once
+/** Offset 0x0D03 - PPR Run Once
When Eanble, PPR will run only once and then is disabled at next training cycle
$EN_DIS
**/
UINT8 PprRunOnce;
-/** Offset 0x0D08 - PPR Run During Fastboot
+/** Offset 0x0D04 - PPR Run During Fastboot
When Eanble, PPR will run during fastboot
$EN_DIS
**/
UINT8 PprRunAtFastboot;
-/** Offset 0x0D09 - PPR Repair Type
+/** Offset 0x0D05 - PPR Repair Type
PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
**/
UINT8 PprRepairType;
-/** Offset 0x0D0A - PPR Error Injection
+/** Offset 0x0D06 - PPR Error Injection
When Eanble, PPR will inject bad rows during testing
$EN_DIS
**/
UINT8 PprErrorInjection;
-/** Offset 0x0D0B - PPR ForceRepair
+/** Offset 0x0D07 - PPR ForceRepair
When Eanble, PPR will force repair some rows many times (90)
$EN_DIS
**/
UINT8 PprForceRepair;
-/** Offset 0x0D0C - PPR Repair Controller
+/** Offset 0x0D08 - PPR Repair Controller
PPR repair controller: User chooses to force repair specifc address
**/
UINT8 PprRepairController;
-/** Offset 0x0D0D - PPR Repair Channel
+/** Offset 0x0D09 - PPR Repair Channel
PPR repair Channel: User chooses to force repair specifc address
**/
UINT8 PprRepairChannel;
-/** Offset 0x0D0E - PPR Repair Dimm
+/** Offset 0x0D0A - PPR Repair Dimm
PPR repair Dimm: User chooses to force repair specifc address
**/
UINT8 PprRepairDimm;
-/** Offset 0x0D0F - PPR Repair Rank
+/** Offset 0x0D0B - PPR Repair Rank
PPR repair Rank: User chooses to force repair specifc address
**/
UINT8 PprRepairRank;
-/** Offset 0x0D10 - PPR Repair Row
+/** Offset 0x0D0C - PPR Repair Row
PPR repair Row: User chooses to force repair specifc address
**/
UINT32 PprRepairRow;
-/** Offset 0x0D14 - PPR Repair Physical Address Low
+/** Offset 0x0D10 - PPR Repair Physical Address Low
PPR repair Physical Address Low: User chooses to force repair specifc address
**/
UINT32 PprRepairPhysicalAddrLow;
-/** Offset 0x0D18 - PPR Repair Physical Address High
+/** Offset 0x0D14 - PPR Repair Physical Address High
PPR repair Physical Address High: User chooses to force repair specifc address
**/
UINT32 PprRepairPhysicalAddrHigh;
-/** Offset 0x0D1C - PPR Repair BankGroup
+/** Offset 0x0D18 - PPR Repair BankGroup
PPR repair BankGroup: User chooses to force repair specifc address
**/
UINT8 PprRepairBankGroup;
-/** Offset 0x0D1D - PPR Repair Bank
+/** Offset 0x0D19 - PPR Repair Bank
PPR repair Bank: User chooses to force repair specifc address
**/
UINT8 PprRepairBank;
-/** Offset 0x0D1E - DIMM CA ODT Split Training
+/** Offset 0x0D1A - DIMM CA ODT Split Training
Enable/Disable DIMM CA ODT Split Training
$EN_DIS
**/
UINT8 DIMMODTCASPLIT;
-/** Offset 0x0D1F - CMD Drive Strength Split
+/** Offset 0x0D1B - CMD Drive Strength Split
Enable/Disable CMD Drive Strength Split
$EN_DIS
**/
UINT8 CMDDSSPLIT;
-/** Offset 0x0D20 - CMD Slew Rate Split Training
+/** Offset 0x0D1C - CMD Slew Rate Split Training
Enable/Disable CMD Slew Rate Split Training
$EN_DIS
**/
UINT8 CMDSRSPLIT;
-/** Offset 0x0D21
+/** Offset 0x0D1D
**/
UINT8 SaFspmUpdRsvd[23];
-/** Offset 0x0D38 - TotalFlashSize
+/** Offset 0x0D34 - TotalFlashSize
Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
**/
UINT16 TotalFlashSize;
-/** Offset 0x0D3A - BiosSize
+/** Offset 0x0D36 - BiosSize
The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected
Range) so that a BIOS Update Script can be stored in the DPR.
**/
UINT16 BiosSize;
-/** Offset 0x0D3C - SecurityTestRsvd
+/** Offset 0x0D38 - SecurityTestRsvd
Reserved for SA Pre-Mem Test
$EN_DIS
**/
UINT8 SecurityTestRsvd[12];
-/** Offset 0x0D48
+/** Offset 0x0D44
**/
UINT8 SecFspmUpdRsvd[16];
-/** Offset 0x0D58 - Smbus dynamic power gating
+/** Offset 0x0D54 - Smbus dynamic power gating
Disable or Enable Smbus dynamic power gating.
$EN_DIS
**/
UINT8 SmbusDynamicPowerGating;
-/** Offset 0x0D59 - Disable and Lock Watch Dog Register
+/** Offset 0x0D55 - Disable and Lock Watch Dog Register
Set 1 to clear WDT status, then disable and lock WDT registers.
$EN_DIS
**/
UINT8 WdtDisableAndLock;
-/** Offset 0x0D5A - SoC BCLK PLL configuration
+/** Offset 0x0D56 - SoC BCLK PLL configuration
Configure SoC BCLK PLL state
$EN_DIS
**/
UINT8 SocBclkPllOn;
-/** Offset 0x0D5B - CPU BCLK PLL configuration
+/** Offset 0x0D57 - CPU BCLK PLL configuration
Configure CPU BCLK PLL state
$EN_DIS
**/
UINT8 CpuBclkPllOn;
-/** Offset 0x0D5C - SMBUS SPD Write Disable
+/** Offset 0x0D58 - SMBUS SPD Write Disable
Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
Disable bit. For security recommendations, SPD write disable bit must be set.
$EN_DIS
**/
UINT8 SmbusSpdWriteDisable;
-/** Offset 0x0D5D - Dmi Tran Co Over En
+/** Offset 0x0D59 - Dmi Tran Co Over En
Enable/Disable Lane Transmitter Coefficient.
**/
UINT8 PchDmiTranCoOverEn[8];
-/** Offset 0x0D65 - Dmi Tran Co Over Post Cur
+/** Offset 0x0D61 - Dmi Tran Co Over Post Cur
Lane Transmitter Post-Cursor Coefficient Override.
**/
UINT8 PchDmiTranCoOverPostCur[8];
-/** Offset 0x0D6D - Dmi Tran Co Over Pre Cur
+/** Offset 0x0D69 - Dmi Tran Co Over Pre Cur
Lane Transmitter Pre-Cursor Coefficient Override.
**/
UINT8 PchDmiTranCoOverPreCur[8];
-/** Offset 0x0D75 - Dmi Up Port Tran Preset
+/** Offset 0x0D71 - Dmi Up Port Tran Preset
Upstream Port Lane Transmitter Preset.
**/
UINT8 PchDmiUpPortTranPreset[8];
-/** Offset 0x0D7D - Dmi UpPort Tran Preset En
+/** Offset 0x0D79 - Dmi UpPort Tran Preset En
0: POR setting, 1: force enable, 2: force disable.
**/
UINT8 PchDmiUpPortTranPresetEn;
-/** Offset 0x0D7E - Dmi Rtlepceb
+/** Offset 0x0D7A - Dmi Rtlepceb
DMI Remote Transmit Link Equalization Preset/Coefficient Evaluation Bypass (RTLEPCEB).
**/
UINT8 PchDmiRtlepceb;
-/** Offset 0x0D7F - HECI Timeouts
+/** Offset 0x0D7B - HECI Timeouts
0: Disable, 1: Enable (Default) timeout check for HECI
$EN_DIS
**/
UINT8 HeciTimeouts;
-/** Offset 0x0D80 - Force ME DID Init Status
+/** Offset 0x0D7C - Force ME DID Init Status
Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
ME DID init stat value
$EN_DIS
**/
UINT8 DidInitStat;
-/** Offset 0x0D81 - CPU Replaced Polling Disable
+/** Offset 0x0D7D - CPU Replaced Polling Disable
Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
$EN_DIS
**/
UINT8 DisableCpuReplacedPolling;
-/** Offset 0x0D82 - Check HECI message before send
+/** Offset 0x0D7E - Check HECI message before send
Test, 0: disable, 1: enable, Enable/Disable message check.
$EN_DIS
**/
UINT8 DisableMessageCheck;
-/** Offset 0x0D83 - Skip MBP HOB
+/** Offset 0x0D7F - Skip MBP HOB
Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob.
$EN_DIS
**/
UINT8 SkipMbpHob;
-/** Offset 0x0D84 - HECI2 Interface Communication
+/** Offset 0x0D80 - HECI2 Interface Communication
Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
$EN_DIS
**/
UINT8 HeciCommunication2;
-/** Offset 0x0D85 - Enable KT device
+/** Offset 0x0D81 - Enable KT device
Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device.
$EN_DIS
**/
UINT8 KtDeviceEnable;
-/** Offset 0x0D86 - Skip CPU replacement check
+/** Offset 0x0D82 - Skip CPU replacement check
Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
$EN_DIS
**/
UINT8 SkipCpuReplacementCheck;
-/** Offset 0x0D87
+/** Offset 0x0D83
**/
UINT8 PchMeFspmUpdRsvd[100];
-/** Offset 0x0DEB - Avx2 Voltage Guardband Scaling Factor
+/** Offset 0x0DE7 - Avx2 Voltage Guardband Scaling Factor
AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
1/100 units, where a value of 125 would apply a 1.25 scale factor.
**/
UINT8 Avx2VoltageScaleFactor;
-/** Offset 0x0DEC - Avx512 Voltage Guardband Scaling Factor
+/** Offset 0x0DE8 - Avx512 Voltage Guardband Scaling Factor
DEPRECATED. AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range
is 0-200 in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
**/
UINT8 Avx512VoltageScaleFactor;
-/** Offset 0x0DED - Serial Io Uart Debug Mode
+/** Offset 0x0DE9 - Serial Io Uart Debug Mode
Select SerialIo Uart Controller mode
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
4:SerialIoUartSkipInit
**/
UINT8 SerialIoUartDebugMode;
-/** Offset 0x0DEE
+/** Offset 0x0DEA
**/
UINT16 Rsvd391;
-/** Offset 0x0DF0 - SerialIoUartDebugRxPinMux - FSPM
+/** Offset 0x0DEC - SerialIoUartDebugRxPinMux - FSPM
Select RX pin muxing for SerialIo UART used for debug
**/
UINT32 SerialIoUartDebugRxPinMux;
-/** Offset 0x0DF4 - SerialIoUartDebugTxPinMux - FSPM
+/** Offset 0x0DF0 - SerialIoUartDebugTxPinMux - FSPM
Select TX pin muxing for SerialIo UART used for debug
**/
UINT32 SerialIoUartDebugTxPinMux;
-/** Offset 0x0DF8 - SerialIoUartDebugRtsPinMux - FSPM
+/** Offset 0x0DF4 - SerialIoUartDebugRtsPinMux - FSPM
Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
for possible values.
**/
UINT32 SerialIoUartDebugRtsPinMux;
-/** Offset 0x0DFC - SerialIoUartDebugCtsPinMux - FSPM
+/** Offset 0x0DF8 - SerialIoUartDebugCtsPinMux - FSPM
Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
for possible values.
**/
UINT32 SerialIoUartDebugCtsPinMux;
-/** Offset 0x0E00 - Serial Io Uart Debug Pci Base
+/** Offset 0x0DFC - Serial Io Uart Debug Pci Base
Specify PciCfgBase address. Allows for SerialIO UART functionality outside Bus 0
**/
UINT32 SerialIoUartDebugPciCfgBase;
-/** Offset 0x0E04 - Memory Subsystem voltage mode
+/** Offset 0x0E00 - Memory Subsystem voltage mode
Memory Subsystem voltage mode; <b>0: Adaptive</b>; 1: Override.
$EN_DIS
**/
UINT8 MemSSVoltageMode;
-/** Offset 0x0E05
+/** Offset 0x0E01
**/
UINT8 Rsvd390;
-/** Offset 0x0E06 - Memory Subsystem Adaptive Voltage
+/** Offset 0x0E02 - Memory Subsystem Adaptive Voltage
Adaptive voltage applied to the memory when the cpu is operating in adaptive mode.
Valid Range 0 to 2000
**/
UINT16 MemSSAdaptiveVoltage;
-/** Offset 0x0E08 - Memory Subsystem voltage override
+/** Offset 0x0E04 - Memory Subsystem voltage override
The Memory Subsystem voltage override which is applied to the entire range of memory
frequencies. Valid Range 0 to 2000
**/
UINT16 MemSSVoltageOverride;
-/** Offset 0x0E0A - Memory Subsystem VF Point Offset Mode
+/** Offset 0x0E06 - Memory Subsystem VF Point Offset Mode
Selects Memory Subsystem Voltage & Frequency Offset mode between Legacy and Selection
modes. In Legacy Mode, setting a global offset for the entire VF curve. In Selection
Mode, setting a selected VF point; <b>0: Legacy</b>; 1: Selection.
@@ -5173,36 +5246,36 @@ typedef struct {
**/
UINT8 MemSSVfPointOffsetMode;
-/** Offset 0x0E0B - Maximum Memory Subsystem turbo ratio override
+/** Offset 0x0E07 - Maximum Memory Subsystem turbo ratio override
Maximum Memory Subsystem turbo ratio override allows to increase memory frequency
beyond the fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85
**/
UINT8 MemSSMaxOcRatio;
-/** Offset 0x0E0C - Memory Subsystem Turbo voltage Offset
+/** Offset 0x0E08 - Memory Subsystem Turbo voltage Offset
The voltage offset applied to the memory while operating in turbo mode. Valid Range 0 to 1000
**/
UINT16 MemSSVoltageOffset;
-/** Offset 0x0E0E - Select Core(s) and RING DLVR Mode
- Select Core(s) and RING DLVR Mode). <b>0: Regulation Mode</b>; 1: Power Gate Mode
+/** Offset 0x0E0A - Select Core(s) and RING DLVR Mode
+ DEPRECATED. Select Core(s) and RING DLVR Mode). <b>0: Regulation Mode</b>; 1: Power Gate Mode
0:Regulation Mode, 1:Power Gate Mode
**/
UINT8 CpuDlvrMode;
-/** Offset 0x0E0F - Maximum clr turbo ratio override
+/** Offset 0x0E0B - Maximum clr turbo ratio override
Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85
**/
UINT8 NguMaxOcRatio;
-/** Offset 0x0E10 - NGU voltage mode
+/** Offset 0x0E0C - NGU voltage mode
NGU voltage mode; <b>0: Adaptive</b>; 1: Override.
$EN_DIS
**/
UINT8 NguVoltageMode;
-/** Offset 0x0E11 - NGU Ratio
+/** Offset 0x0E0D - NGU Ratio
Sets the Ratio for NGU when SAGV is enabled, using SAVG B2P Mailbox cmd 0x22 and
subcommand 0x1. When this value is zero, dynamic mode is selected and NGU ratio
can be modified using OCMB cmd 0x11. When valid ratio value is set, static mode
@@ -5211,23 +5284,23 @@ typedef struct {
**/
UINT8 NguRatio;
-/** Offset 0x0E12 - NGU voltage override
+/** Offset 0x0E0E - NGU voltage override
The NGU voltage override which is applied to the entire range of cpu NGU frequencies.
Valid Range 0 to 2000
**/
UINT16 NguVoltageOverride;
-/** Offset 0x0E14 - adaptive voltage applied during turbo frequencies
+/** Offset 0x0E10 - adaptive voltage applied during turbo frequencies
0(Default)=Minimal, 2000=Maximum
**/
UINT16 NguAdaptiveVoltage;
-/** Offset 0x0E16 - NGU Turbo voltage Offset
+/** Offset 0x0E12 - NGU Turbo voltage Offset
The voltage offset applied to the NGU while operating in turbo mode. Valid Range 0 to 1000
**/
UINT16 NguVoltageOffset;
-/** Offset 0x0E18 - NGU VF Point Offset Mode
+/** Offset 0x0E14 - NGU VF Point Offset Mode
Selects NGU Voltage & Frequency Offset mode between Legacy and Selection modes.
In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode,
setting a selected VF point; <b>0: Legacy</b>; 1: Selection.
@@ -5235,37 +5308,37 @@ typedef struct {
**/
UINT8 NguVfPointOffsetMode;
-/** Offset 0x0E19
+/** Offset 0x0E15
**/
UINT8 Rsvd410[1];
-/** Offset 0x0E1A - NGU VF Point Offset
+/** Offset 0x0E16 - NGU VF Point Offset
Array used to specifies the NGU Voltage Offset applied to the each selected VF Point.
This voltage is specified in millivolts.
**/
UINT16 NguVfPointOffset[15];
-/** Offset 0x0E38 - NGU VF Point Offset Prefix
+/** Offset 0x0E34 - NGU VF Point Offset Prefix
Sets the NguVfPointOffset value as positive or negative for corresponding core VF
Point; <b>0: Positive </b>; 1: Negative.
**/
UINT8 NguVfPointOffsetPrefix[15];
-/** Offset 0x0E47 - NGU VF Point Ratio
+/** Offset 0x0E43 - NGU VF Point Ratio
Array for the each selected NGU VF Point to display the ration.
**/
UINT8 NguVfPointRatio[15];
-/** Offset 0x0E56 - NGU VF Point Count
+/** Offset 0x0E52 - NGU VF Point Count
Number of supported NGU Voltage & Frequency Point Offset
**/
UINT8 NguVfPointCount;
-/** Offset 0x0E57
+/** Offset 0x0E53
**/
UINT8 Rsvd420[11];
-/** Offset 0x0E62 - GT VF Point Offset Mode
+/** Offset 0x0E5E - GT VF Point Offset Mode
Selects GT Voltage & Frequency Offset mode between Legacy and Selection modes. In
Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode,
setting a selected VF point; <b>0: Legacy</b>; 1: Selection.
@@ -5273,69 +5346,75 @@ typedef struct {
**/
UINT8 GtVfPointOffsetMode;
-/** Offset 0x0E63
+/** Offset 0x0E5F
**/
UINT8 Rsvd430[1];
-/** Offset 0x0E64 - GT VF Point Offset
+/** Offset 0x0E60 - GT VF Point Offset
Array used to specifies the GT Voltage Offset applied to the each selected VF Point.
This voltage is specified in millivolts.
**/
UINT16 GtVfPointOffset[15];
-/** Offset 0x0E82 - GT VF Point Offset Prefix
+/** Offset 0x0E7E - GT VF Point Offset Prefix
Sets the GtVfPointOffset value as positive or negative for corresponding core VF
Point; <b>0: Positive </b>; 1: Negative.
**/
UINT8 GtVfPointOffsetPrefix[15];
-/** Offset 0x0E91 - GT VF Point Ratio
+/** Offset 0x0E8D - GT VF Point Ratio
Array for the each selected GT VF Point to display the ration.
**/
UINT8 GtVfPointRatio[15];
-/** Offset 0x0EA0 - GT VF Point Count
+/** Offset 0x0E9C - GT VF Point Count
Number of supported GT Voltage & Frequency Point Offset
**/
UINT8 GtVfPointCount;
-/** Offset 0x0EA1 - Time Measure
+/** Offset 0x0E9D - Time Measure
Time Measure: 0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 MrcTimeMeasure;
-/** Offset 0x0EA2 - Must use static SPD data from VPD
+/** Offset 0x0E9E - Must use static SPD data from VPD
Must use static SPD data from VPD and Spd Address is correct: Each bit maps to one dimm
**/
UINT16 MrcMustStaticSpdData;
-/** Offset 0x0EA4
-**/
- UINT8 UnusedUpdSpace5[4];
-
-/** Offset 0x0EA8 - TME Exclude Base Address
+/** Offset 0x0EA0 - TME Exclude Base Address
TME Exclude Base Address.
**/
UINT64 TmeExcludeBase;
-/** Offset 0x0EB0 - TME Exclude Size Value
+/** Offset 0x0EA8 - TME Exclude Size Value
TME Exclude Size Value.
**/
UINT64 TmeExcludeSize;
-/** Offset 0x0EB8 - Generate New TME Key
+/** Offset 0x0EB0 - Generate New TME Key
Enable: Generate New TME Key, Disable(Default): TME key determine by type of reset
$EN_DIS
**/
UINT8 GenerateNewTmeKey;
-/** Offset 0x0EB9 - CkdAddress Tabl
+/** Offset 0x0EB1 - CkdAddress Tabl
Specify CKD Address table for CH0D0/CH0D1/CH1D0&CH1D1
**/
UINT8 CkdAddressTable[16];
-/** Offset 0x0EC9
+/** Offset 0x0EC1 - Channel to CKD QCK Mapping
+ Specify Channel to CKD QCK Mapping for CH0D0/CH0D1/CH1D0&CH1D1
+**/
+ UINT8 ChannelToCkdQckMapping[8];
+
+/** Offset 0x0EC9 - DDRIO Clock to CKD DIMM
+ Specify DDRIO Clock to CKD DIMM for CH0D0/CH0D1/CH1D0&CH1D1
+**/
+ UINT8 PhyClockToCkdDimm[8];
+
+/** Offset 0x0ED1
**/
UINT8 ReservedFspmUpd2[7];
} FSP_M_CONFIG;
@@ -5356,11 +5435,11 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
-/** Offset 0x0ED0
+/** Offset 0x0ED8
**/
UINT8 Rsvd500[6];
-/** Offset 0x0ED6
+/** Offset 0x0EDE
**/
UINT16 UpdTerminator;
} FSPM_UPD;
diff --git a/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspsUpd.h b/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspsUpd.h
index 1a72e9a..7baeb79 100644
--- a/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspsUpd.h
+++ b/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FspsUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -314,272 +314,282 @@ typedef struct {
**/
UINT8 SerialIoSpiCsState[7];
-/** Offset 0x011F
+/** Offset 0x011F - SPIn Delayed Rx Clock setting
+ 00:default, 01:Internal, 10:NegEdge Tx Clock, 11:NegEdge Delayed Rx Clk. Configure
+ Delayed Rx Clock
+**/
+ UINT8 SerialIoSpiDelayRxClk[7];
+
+/** Offset 0x0126
**/
UINT8 Rsvd050[1];
-/** Offset 0x0120 - Serial IO SPI CS Pin Muxing
+/** Offset 0x0127
+**/
+ UINT8 UnusedUpdSpace1[1];
+
+/** Offset 0x0128 - Serial IO SPI CS Pin Muxing
Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CS* for
possible values.
**/
UINT32 SerialIoSpiCsPinMux[14];
-/** Offset 0x0158 - Serial IO SPI CLK Pin Muxing
+/** Offset 0x0160 - Serial IO SPI CLK Pin Muxing
Select SerialIo SPI CS pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_CLK* for
possible values.
**/
UINT32 SerialIoSpiClkPinMux[7];
-/** Offset 0x0174 - Serial IO SPI MISO Pin Muxing
+/** Offset 0x017C - Serial IO SPI MISO Pin Muxing
Select SerialIo SPI MISO pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MISO*
for possible values.
**/
UINT32 SerialIoSpiMisoPinMux[7];
-/** Offset 0x0190 - Serial IO SPI MOSI Pin Muxing
+/** Offset 0x0198 - Serial IO SPI MOSI Pin Muxing
Select SerialIo SPI MOSI pin muxing. Refer to GPIO_*_MUXING_SERIALIO_SPIx_MOSI*
for possible values.
**/
UINT32 SerialIoSpiMosiPinMux[7];
-/** Offset 0x01AC - UARTn Device Mode
+/** Offset 0x01B4 - UARTn Device Mode
Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
4:SerialIoUartSkipInit
**/
UINT8 SerialIoUartMode[7];
-/** Offset 0x01B3
+/** Offset 0x01BB
**/
UINT8 Rsvd060[1];
-/** Offset 0x01B4 - Default BaudRate for each Serial IO UART
+/** Offset 0x01BC - Default BaudRate for each Serial IO UART
Set default BaudRate Supported from 0 - default to 6000000
**/
UINT32 SerialIoUartBaudRate[7];
-/** Offset 0x01D0 - Default ParityType for each Serial IO UART
+/** Offset 0x01D8 - Default ParityType for each Serial IO UART
Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
**/
UINT8 SerialIoUartParity[7];
-/** Offset 0x01D7 - Default DataBits for each Serial IO UART
+/** Offset 0x01DF - Default DataBits for each Serial IO UART
Set default word length. 0: Default, 5,6,7,8
**/
UINT8 SerialIoUartDataBits[7];
-/** Offset 0x01DE - Default StopBits for each Serial IO UART
+/** Offset 0x01E6 - Default StopBits for each Serial IO UART
Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3:
TwoStopBits
**/
UINT8 SerialIoUartStopBits[7];
-/** Offset 0x01E5 - Power Gating mode for each Serial IO UART that works in COM mode
+/** Offset 0x01ED - Power Gating mode for each Serial IO UART that works in COM mode
Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto
**/
UINT8 SerialIoUartPowerGating[7];
-/** Offset 0x01EC - Enable Dma for each Serial IO UART that supports it
+/** Offset 0x01F4 - Enable Dma for each Serial IO UART that supports it
Set DMA/PIO mode. 0: Disabled, 1: Enabled
**/
UINT8 SerialIoUartDmaEnable[7];
-/** Offset 0x01F3 - Enables UART hardware flow control, CTS and RTS lines
+/** Offset 0x01FB - Enables UART hardware flow control, CTS and RTS lines
Enables UART hardware flow control, CTS and RTS lines.
**/
UINT8 SerialIoUartAutoFlow[7];
-/** Offset 0x01FA
+/** Offset 0x0202
**/
UINT8 Rsvd070[2];
-/** Offset 0x01FC - SerialIoUartRtsPinMuxPolicy
+/** Offset 0x0204 - SerialIoUartRtsPinMuxPolicy
Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
for possible values.
**/
UINT32 SerialIoUartRtsPinMuxPolicy[7];
-/** Offset 0x0218 - SerialIoUartCtsPinMuxPolicy
+/** Offset 0x0220 - SerialIoUartCtsPinMuxPolicy
Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
for possible values.
**/
UINT32 SerialIoUartCtsPinMuxPolicy[7];
-/** Offset 0x0234 - SerialIoUartRxPinMuxPolicy
+/** Offset 0x023C - SerialIoUartRxPinMuxPolicy
Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for
possible values.
**/
UINT32 SerialIoUartRxPinMuxPolicy[7];
-/** Offset 0x0250 - SerialIoUartTxPinMuxPolicy
+/** Offset 0x0258 - SerialIoUartTxPinMuxPolicy
Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for
possible values.
**/
UINT32 SerialIoUartTxPinMuxPolicy[7];
-/** Offset 0x026C - Serial IO UART DBG2 table
+/** Offset 0x0274 - Serial IO UART DBG2 table
Enable or disable Serial Io UART DBG2 table, default is Disable; <b>0: Disable;</b>
1: Enable.
**/
UINT8 SerialIoUartDbg2[7];
-/** Offset 0x0273 - I2Cn Device Mode
+/** Offset 0x027B - I2Cn Device Mode
Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
**/
UINT8 SerialIoI2cMode[8];
-/** Offset 0x027B
+/** Offset 0x0283
**/
UINT8 Rsvd080[1];
-/** Offset 0x027C - Serial IO I2C SDA Pin Muxing
+/** Offset 0x0284 - Serial IO I2C SDA Pin Muxing
Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
possible values.
**/
UINT32 PchSerialIoI2cSdaPinMux[8];
-/** Offset 0x029C - Serial IO I2C SCL Pin Muxing
+/** Offset 0x02A4 - Serial IO I2C SCL Pin Muxing
Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for
possible values.
**/
UINT32 PchSerialIoI2cSclPinMux[8];
-/** Offset 0x02BC - PCH SerialIo I2C Pads Termination
+/** Offset 0x02C4 - PCH SerialIo I2C Pads Termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination
respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
**/
UINT8 PchSerialIoI2cPadsTermination[8];
-/** Offset 0x02C4 - I3C Device Mode
+/** Offset 0x02CC - I3C Device Mode
Selects I3c operation mode. Available modes: 0:SerialIoI3cDisabled, 1:SerialIoI3cPci,
2:SerialIoI3cPhantom (only applicable to I3C1, controlls GPIO enabling)
**/
UINT8 SerialIoI3cMode[2];
-/** Offset 0x02C6
+/** Offset 0x02CE
**/
UINT8 Rsvd090[2];
-/** Offset 0x02C8 - Serial IO I3C SDA Pin Muxing
+/** Offset 0x02D0 - Serial IO I3C SDA Pin Muxing
Select SerialIo I3c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SDA* for
possible values.
**/
UINT32 SerialIoI3cSdaPinMux[2];
-/** Offset 0x02D0 - Serial IO I3C SDA Pad Termination
+/** Offset 0x02D8 - Serial IO I3C SDA Pad Termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
**/
UINT8 SerialIoI3cSdaPadTermination[2];
-/** Offset 0x02D2
+/** Offset 0x02DA
**/
UINT8 Rsvd100[2];
-/** Offset 0x02D4 - Serial IO I3C SCL Pin Muxing
+/** Offset 0x02DC - Serial IO I3C SCL Pin Muxing
Select SerialIo I3c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL* for
possible values.
**/
UINT32 SerialIoI3cSclPinMux[2];
-/** Offset 0x02DC - Serial IO I3C SCL Pad Termination
+/** Offset 0x02E4 - Serial IO I3C SCL Pad Termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
**/
UINT8 SerialIoI3cSclPadTermination[2];
-/** Offset 0x02DE
+/** Offset 0x02E6
**/
UINT8 Rsvd110[2];
-/** Offset 0x02E0 - Serial IO I3C SCL FB Pin Muxing
+/** Offset 0x02E8 - Serial IO I3C SCL FB Pin Muxing
Select SerialIo I3c SclFb pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I3Cx_SCL FB*
for possible values.
**/
UINT32 SerialIoI3cSclFbPinMux[2];
-/** Offset 0x02E8 - Serial IO I3C SCL FB Pad Termination
+/** Offset 0x02F0 - Serial IO I3C SCL FB Pad Termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I3C0,I3C1,... pads termination
respectively. One byte for each controller, byte0 for I3C0, byte1 for I3C1, and so on.
**/
UINT8 SerialIoI3cSclFbPadTermination[2];
-/** Offset 0x02EA
+/** Offset 0x02F2
**/
UINT8 Rsvd120[2];
-/** Offset 0x02EC - ISH GP GPIO Pin Muxing
+/** Offset 0x02F4 - ISH GP GPIO Pin Muxing
Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER
**/
UINT32 IshGpGpioPinMuxing[12];
-/** Offset 0x031C - ISH UART Rx Pin Muxing
+/** Offset 0x0324 - ISH UART Rx Pin Muxing
Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_*
**/
UINT32 IshUartRxPinMuxing[3];
-/** Offset 0x0328 - ISH UART Tx Pin Muxing
+/** Offset 0x0330 - ISH UART Tx Pin Muxing
Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_*
**/
UINT32 IshUartTxPinMuxing[3];
-/** Offset 0x0334 - ISH UART Rts Pin Muxing
+/** Offset 0x033C - ISH UART Rts Pin Muxing
Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values.
**/
UINT32 IshUartRtsPinMuxing[3];
-/** Offset 0x0340 - ISH UART Rts Pin Muxing
+/** Offset 0x0348 - ISH UART Rts Pin Muxing
Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values.
**/
UINT32 IshUartCtsPinMuxing[3];
-/** Offset 0x034C - ISH I2C SDA Pin Muxing
+/** Offset 0x0354 - ISH I2C SDA Pin Muxing
Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values.
**/
UINT32 IshI2cSdaPinMuxing[3];
-/** Offset 0x0358 - ISH I2C SCL Pin Muxing
+/** Offset 0x0360 - ISH I2C SCL Pin Muxing
Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values.
**/
UINT32 IshI2cSclPinMuxing[3];
-/** Offset 0x0364 - ISH I3C SDA Pin Muxing
+/** Offset 0x036C - ISH I3C SDA Pin Muxing
Select ISH I3C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SDA_* for possible values.
**/
UINT32 IshI3cSdaPinMuxing;
-/** Offset 0x0368 - ISH I3C SCL Pin Muxing
+/** Offset 0x0370 - ISH I3C SCL Pin Muxing
Select ISH I3C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I3Cx_SCL_* for possible values.
**/
UINT32 IshI3cSclPinMuxing;
-/** Offset 0x036C - ISH SPI MOSI Pin Muxing
+/** Offset 0x0374 - ISH SPI MOSI Pin Muxing
Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values.
**/
UINT32 IshSpiMosiPinMuxing[2];
-/** Offset 0x0374 - ISH SPI MISO Pin Muxing
+/** Offset 0x037C - ISH SPI MISO Pin Muxing
Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values.
**/
UINT32 IshSpiMisoPinMuxing[2];
-/** Offset 0x037C - ISH SPI CLK Pin Muxing
+/** Offset 0x0384 - ISH SPI CLK Pin Muxing
Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values.
**/
UINT32 IshSpiClkPinMuxing[2];
-/** Offset 0x0384 - ISH SPI CS#N Pin Muxing
+/** Offset 0x038C - ISH SPI CS#N Pin Muxing
Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS<N>_* for possible
values. N-SPI number, 0-1.
**/
UINT32 IshSpiCsPinMuxing[4];
-/** Offset 0x0394 - ISH GP GPIO Pad termination
+/** Offset 0x039C - ISH GP GPIO Pad termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination
respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index
@@ -587,7 +597,7 @@ typedef struct {
**/
UINT8 IshGpGpioPadTermination[12];
-/** Offset 0x03A0 - ISH UART Rx Pad termination
+/** Offset 0x03A8 - ISH UART Rx Pad termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination
respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1
@@ -595,7 +605,7 @@ typedef struct {
**/
UINT8 IshUartRxPadTermination[3];
-/** Offset 0x03A3 - ISH UART Tx Pad termination
+/** Offset 0x03AB - ISH UART Tx Pad termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination
respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1
@@ -603,7 +613,7 @@ typedef struct {
**/
UINT8 IshUartTxPadTermination[3];
-/** Offset 0x03A6 - ISH UART Rts Pad termination
+/** Offset 0x03AE - ISH UART Rts Pad termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination
respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1
@@ -611,7 +621,7 @@ typedef struct {
**/
UINT8 IshUartRtsPadTermination[3];
-/** Offset 0x03A9 - ISH UART Rts Pad termination
+/** Offset 0x03B1 - ISH UART Rts Pad termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination
respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1
@@ -619,7 +629,7 @@ typedef struct {
**/
UINT8 IshUartCtsPadTermination[3];
-/** Offset 0x03AC - ISH I2C SDA Pad termination
+/** Offset 0x03B4 - ISH I2C SDA Pad termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination
respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda,
@@ -627,7 +637,7 @@ typedef struct {
**/
UINT8 IshI2cSdaPadTermination[3];
-/** Offset 0x03AF - ISH I3C SDA Pad termination
+/** Offset 0x03B7 - ISH I3C SDA Pad termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination
respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda,
@@ -635,7 +645,7 @@ typedef struct {
**/
UINT8 IshI3cSdaPadTermination;
-/** Offset 0x03B0 - ISH I2C SCL Pad termination
+/** Offset 0x03B8 - ISH I2C SCL Pad termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination
respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl,
@@ -643,7 +653,7 @@ typedef struct {
**/
UINT8 IshI2cSclPadTermination[3];
-/** Offset 0x03B3 - ISH I3C SCL Pad termination
+/** Offset 0x03BB - ISH I3C SCL Pad termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination
respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl,
@@ -651,7 +661,7 @@ typedef struct {
**/
UINT8 IshI3cSclPadTermination;
-/** Offset 0x03B4 - ISH SPI MOSI Pad termination
+/** Offset 0x03BC - ISH SPI MOSI Pad termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination
respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1
@@ -659,7 +669,7 @@ typedef struct {
**/
UINT8 IshSpiMosiPadTermination[2];
-/** Offset 0x03B6 - ISH SPI MISO Pad termination
+/** Offset 0x03BE - ISH SPI MISO Pad termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination
respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1
@@ -667,7 +677,7 @@ typedef struct {
**/
UINT8 IshSpiMisoPadTermination[2];
-/** Offset 0x03B8 - ISH SPI CLK Pad termination
+/** Offset 0x03C0 - ISH SPI CLK Pad termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination
respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk,
@@ -675,7 +685,7 @@ typedef struct {
**/
UINT8 IshSpiClkPadTermination[2];
-/** Offset 0x03BA - ISH SPI CS#N Pad termination
+/** Offset 0x03C2 - ISH SPI CS#N Pad termination
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination
respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1
@@ -683,858 +693,839 @@ typedef struct {
**/
UINT8 IshSpiCsPadTermination[4];
-/** Offset 0x03BE - Enable PCH ISH SPI Cs#N pins assigned
+/** Offset 0x03C6 - Enable PCH ISH SPI Cs#N pins assigned
Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs
number: 0-1
**/
UINT8 PchIshSpiCsEnable[4];
-/** Offset 0x03C2 - USB Per Port HS Preemphasis Bias
+/** Offset 0x03CA - USB Per Port HS Preemphasis Bias
USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
**/
UINT8 Usb2PhyPetxiset[16];
-/** Offset 0x03D2 - USB Per Port HS Transmitter Bias
+/** Offset 0x03DA - USB Per Port HS Transmitter Bias
USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
**/
UINT8 Usb2PhyTxiset[16];
-/** Offset 0x03E2 - USB Per Port HS Transmitter Emphasis
+/** Offset 0x03EA - USB Per Port HS Transmitter Emphasis
USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
**/
UINT8 Usb2PhyPredeemp[16];
-/** Offset 0x03F2 - USB Per Port Half Bit Pre-emphasis
+/** Offset 0x03FA - USB Per Port Half Bit Pre-emphasis
USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
One byte for each port.
**/
UINT8 Usb2PhyPehalfbit[16];
-/** Offset 0x0402 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
+/** Offset 0x040A - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
in arrary can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxDeEmphEnable[10];
-/** Offset 0x040C - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
+/** Offset 0x0414 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
<b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
**/
UINT8 Usb3HsioTxDeEmph[10];
-/** Offset 0x0416 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
+/** Offset 0x041E - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
in arrary can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxDownscaleAmpEnable[10];
-/** Offset 0x0420 - USB 3.0 TX Output Downscale Amplitude Adjustment
+/** Offset 0x0428 - USB 3.0 TX Output Downscale Amplitude Adjustment
USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
= 00h</b>. One byte for each port.
**/
UINT8 Usb3HsioTxDownscaleAmp[10];
-/** Offset 0x042A
+/** Offset 0x0432
**/
UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10];
-/** Offset 0x0434
+/** Offset 0x043C
**/
UINT8 PchUsb3HsioFilterSelNEnable[10];
-/** Offset 0x043E
+/** Offset 0x0446
**/
UINT8 PchUsb3HsioFilterSelPEnable[10];
-/** Offset 0x0448
+/** Offset 0x0450
**/
UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10];
-/** Offset 0x0452
+/** Offset 0x045A
**/
UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10];
-/** Offset 0x045C
+/** Offset 0x0464
**/
UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10];
-/** Offset 0x0466
+/** Offset 0x046E
**/
UINT8 PchUsb3HsioFilterSelN[10];
-/** Offset 0x0470
+/** Offset 0x0478
**/
UINT8 PchUsb3HsioFilterSelP[10];
-/** Offset 0x047A - Enable LAN
+/** Offset 0x0482 - Enable LAN
Enable/disable LAN controller.
$EN_DIS
**/
UINT8 PchLanEnable;
-/** Offset 0x047B - Enable PCH TSN
+/** Offset 0x0483 - Enable PCH TSN
Enable/disable TSN on the PCH.
$EN_DIS
**/
UINT8 PchTsnEnable;
-/** Offset 0x047C - TSN Link Speed
+/** Offset 0x0484 - TSN Link Speed
Set TSN Link Speed.
0: 24Mhz 2.5Gbps, 1: 24Mhz 1Gbps, 2: 38.4Mhz 2.5Gbps, 3: 38.4Mhz 1Gbps
**/
UINT8 PchTsnLinkSpeed;
-/** Offset 0x047D
+/** Offset 0x0485
**/
UINT8 Rsvd130[3];
-/** Offset 0x0480 - PCH TSN MAC Address High Bits
+/** Offset 0x0488 - PCH TSN MAC Address High Bits
Set TSN MAC Address High.
**/
UINT32 PchTsnMacAddressHigh;
-/** Offset 0x0484 - PCH TSN MAC Address Low Bits
+/** Offset 0x048C - PCH TSN MAC Address Low Bits
Set TSN MAC Address Low.
**/
UINT32 PchTsnMacAddressLow;
-/** Offset 0x0488 - PCH TSN MAC Address High Bits
+/** Offset 0x0490 - PCH TSN MAC Address High Bits
Set TSN MAC Address High.
**/
UINT32 PchTsn1MacAddressHigh;
-/** Offset 0x048C - PCH TSN MAC Address Low Bits
+/** Offset 0x0494 - PCH TSN MAC Address Low Bits
Set TSN MAC Address Low.
**/
UINT32 PchTsn1MacAddressLow;
-/** Offset 0x0490 - PCIe PTM enable/disable
+/** Offset 0x0498 - PCIe PTM enable/disable
Enable/disable Precision Time Measurement for PCIE Root Ports.
**/
UINT8 PciePtm[29];
-/** Offset 0x04AD - Multi-VC for PCIE RP Mask
- Enable/disable Multiple Virtual Channel for PCIE Root Ports. 0: disable, 1: enable.
- One bit for each port, bit0 for port1, bit1 for port2, and so on.
-**/
- UINT8 PcieMultiVc[29];
-
-/** Offset 0x04CA
-**/
- UINT8 EmbReserved2FspsUpd[2];
-
-/** Offset 0x04CC - Disable DMI Power Gating
+/** Offset 0x04B5 - Disable DMI Power Gating
Enable/disable DMI Power Gating Disable.
$EN_DIS
**/
UINT8 DmiPowerGatingDis;
-/** Offset 0x04CD
+/** Offset 0x04B6
**/
UINT8 Rsvd135[28];
-/** Offset 0x04E9 - USB PDO Programming
+/** Offset 0x04D2 - USB PDO Programming
Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
during later phase. 1: enable, 0: disable
$EN_DIS
**/
UINT8 UsbPdoProgramming;
-/** Offset 0x04EA
+/** Offset 0x04D3
**/
UINT8 Rsvd140[5];
-/** Offset 0x04EF
-**/
- UINT8 UnusedUpdSpace1;
-
-/** Offset 0x04F0 - Power button debounce configuration
+/** Offset 0x04D8 - Power button debounce configuration
Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
**/
UINT32 PmcPowerButtonDebounce;
-/** Offset 0x04F4 - PCH eSPI Host and Device BME enabled
+/** Offset 0x04DC - PCH eSPI Host and Device BME enabled
PCH eSPI Host and Device BME enabled
$EN_DIS
**/
UINT8 PchEspiBmeHostDeviceEnabled;
-/** Offset 0x04F5 - PCH eSPI Link Configuration Lock (SBLCL)
+/** Offset 0x04DD - PCH eSPI Link Configuration Lock (SBLCL)
Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target
addresseses from range 0x0 - 0x7FF
$EN_DIS
**/
UINT8 PchEspiLockLinkConfiguration;
-/** Offset 0x04F6 - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
+/** Offset 0x04DE - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
**/
UINT8 PchFivrExtV1p05RailEnabledStates;
-/** Offset 0x04F7 - Mask to enable the platform configuration of external V1p05 VR rail
+/** Offset 0x04DF - Mask to enable the platform configuration of external V1p05 VR rail
External V1P05 Rail Supported Configuration
**/
UINT8 PchFivrExtV1p05RailSupportedVoltageStates;
-/** Offset 0x04F8 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
+/** Offset 0x04E0 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
**/
UINT16 PchFivrExtV1p05RailVoltage;
-/** Offset 0x04FA - External V1P05 Icc Max Value
+/** Offset 0x04E2 - External V1P05 Icc Max Value
Granularity of this setting is 1mA and maximal possible value is 200mA
**/
UINT8 PchFivrExtV1p05RailIccMax;
-/** Offset 0x04FB - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
+/** Offset 0x04E3 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
**/
UINT8 PchFivrExtVnnRailEnabledStates;
-/** Offset 0x04FC - Mask to enable the platform configuration of external Vnn VR rail
+/** Offset 0x04E4 - Mask to enable the platform configuration of external Vnn VR rail
External Vnn Rail Supported Configuration
**/
UINT8 PchFivrExtVnnRailSupportedVoltageStates;
-/** Offset 0x04FD
+/** Offset 0x04E5
**/
UINT8 Rsvd150;
-/** Offset 0x04FE - External Vnn Voltage Value that will be used in S0ix/Sx states
+/** Offset 0x04E6 - External Vnn Voltage Value that will be used in S0ix/Sx states
Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
**/
UINT16 PchFivrExtVnnRailVoltage;
-/** Offset 0x0500 - External Vnn Icc Max Value that will be used in S0ix/Sx states
+/** Offset 0x04E8 - External Vnn Icc Max Value that will be used in S0ix/Sx states
Granularity of this setting is 1mA and maximal possible value is 200mA
**/
UINT8 PchFivrExtVnnRailIccMax;
-/** Offset 0x0501 - Mask to enable the usage of external Vnn VR rail in Sx states
+/** Offset 0x04E9 - Mask to enable the usage of external Vnn VR rail in Sx states
Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in
Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5
**/
UINT8 PchFivrExtVnnRailSxEnabledStates;
-/** Offset 0x0502 - External Vnn Voltage Value that will be used in Sx states
+/** Offset 0x04EA - External Vnn Voltage Value that will be used in Sx states
Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments
(0=0mV, 1=2.5mV, 2=5mV...)
**/
UINT16 PchFivrExtVnnRailSxVoltage;
-/** Offset 0x0504 - External Vnn Icc Max Value that will be used in Sx states
+/** Offset 0x04EC - External Vnn Icc Max Value that will be used in Sx states
Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
is 1mA and maximal possible value is 200mA
**/
UINT8 PchFivrExtVnnRailSxIccMax;
-/** Offset 0x0505 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
+/** Offset 0x04ED - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
to low current mode voltage.
**/
UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime;
-/** Offset 0x0506 - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
+/** Offset 0x04EE - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
to retention mode voltage.
**/
UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime;
-/** Offset 0x0507 - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
+/** Offset 0x04EF - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
to retention mode voltage.
**/
UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime;
-/** Offset 0x0508 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
+/** Offset 0x04F0 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
This field has 1us resolution. When value is 0 Transition to 0V is disabled.
**/
UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime;
-/** Offset 0x050A - PMC Debug Message Enable
+/** Offset 0x04F2 - PMC Debug Message Enable
When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW
will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix
$EN_DIS
**/
UINT8 PmcDbgMsgEn;
-/** Offset 0x050B
+/** Offset 0x04F3
**/
UINT8 Rsvd160;
-/** Offset 0x050C - Pointer to ChipsetInit Binary
+/** Offset 0x04F4 - Pointer to ChipsetInit Binary
ChipsetInit Binary Pointer.
**/
UINT32 ChipsetInitBinPtr;
-/** Offset 0x0510 - Length of ChipsetInit Binary
+/** Offset 0x04F8 - Length of ChipsetInit Binary
ChipsetInit Binary Length.
**/
UINT32 ChipsetInitBinLen;
-/** Offset 0x0514 - Pointer to NPHY Binary
+/** Offset 0x04FC - Pointer to NPHY Binary
Nphy Binary Pointer.
**/
UINT32 NphyBinPtr;
-/** Offset 0x0518 - Length of NPHY Binary
+/** Offset 0x0500 - Length of NPHY Binary
Nphy Binary Length.
**/
UINT32 NphyBinLen;
-/** Offset 0x051C - Pointer to SYNPS PHY Binary
+/** Offset 0x0504 - Pointer to SYNPS PHY Binary
Synps Binary Pointer.
**/
UINT32 SynpsPhyBinPtr;
-/** Offset 0x0520 - Length of SYNPS PHY Binary
+/** Offset 0x0508 - Length of SYNPS PHY Binary
Synps Binary Length.
**/
UINT32 SynpsPhyBinLen;
-/** Offset 0x0524 - FIVR Dynamic Power Management
+/** Offset 0x050C - FIVR Dynamic Power Management
Enable/Disable FIVR Dynamic Power Management.
$EN_DIS
**/
UINT8 PchFivrDynPm;
-/** Offset 0x0525
+/** Offset 0x050D
**/
UINT8 Rsvd170;
-/** Offset 0x0526 - External V1P05 Icc Max Value
+/** Offset 0x050E - External V1P05 Icc Max Value
Granularity of this setting is 1mA and maximal possible value is 500mA
**/
UINT16 PchFivrExtV1p05RailIccMaximum;
-/** Offset 0x0528 - External Vnn Icc Max Value that will be used in S0ix/Sx states
+/** Offset 0x0510 - External Vnn Icc Max Value that will be used in S0ix/Sx states
Granularity of this setting is 1mA and maximal possible value is 500mA
**/
UINT16 PchFivrExtVnnRailIccMaximum;
-/** Offset 0x052A - External Vnn Icc Max Value that will be used in Sx states
+/** Offset 0x0512 - External Vnn Icc Max Value that will be used in Sx states
Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
is 1mA and maximal possible value is 500mA
**/
UINT16 PchFivrExtVnnRailSxIccMaximum;
-/** Offset 0x052C - USB Audio Offload enable
+/** Offset 0x0514 - USB Audio Offload enable
Enable/Disable USB Audio Offload capabilites. 0: disabled, 1: enabled (default)
$EN_DIS
**/
UINT8 PchXhciUaolEnable;
-/** Offset 0x052D - PCH xHCI enable HS Interrupt IN Alarm
+/** Offset 0x0515 - PCH xHCI enable HS Interrupt IN Alarm
PCH xHCI enable HS Interrupt IN Alarm. 0: disabled (default), 1: enabled
$EN_DIS
**/
UINT8 PchXhciHsiiEnable;
-/** Offset 0x052E
+/** Offset 0x0516
**/
UINT8 Rsvd175[2];
-/** Offset 0x0530 - PCH GPIOV2 Unlock Data Buffer Address
+/** Offset 0x0518 - PCH GPIOV2 Unlock Data Buffer Address
Address of GPIO Unlock Data buffer
**/
UINT32 PchGpioUnlockDataPtr;
-/** Offset 0x0534 - PCH GPIOV2 Unlock Data Buffer Size
+/** Offset 0x051C - PCH GPIOV2 Unlock Data Buffer Size
Size of PCH GPIO Unlock Data Buffer
**/
UINT32 PchGpioUnlockDataSize;
-/** Offset 0x0538 - PchPostMemRsvd
+/** Offset 0x0520 - PchPostMemRsvd
Reserved for PCH Post-Mem
$EN_DIS
**/
UINT8 PchPostMemRsvd[2];
-/** Offset 0x053A - CNVi Configuration
+/** Offset 0x0522 - CNVi Configuration
This option allows for automatic detection of Connectivity Solution. [Auto Detection]
assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
0:Disable, 1:Auto
**/
UINT8 CnviMode;
-/** Offset 0x053B - CNVi Wi-Fi Core
+/** Offset 0x0523 - CNVi Wi-Fi Core
Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviWifiCore;
-/** Offset 0x053C - CNVi BT Core
+/** Offset 0x0524 - CNVi BT Core
Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviBtCore;
-/** Offset 0x053D - CNVi BT Audio Offload
+/** Offset 0x0525 - CNVi BT Audio Offload
Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviBtAudioOffload;
-/** Offset 0x053E
+/** Offset 0x0526
**/
UINT8 Rsvd180[2];
-/** Offset 0x0540 - CNVi RF_RESET pin muxing
+/** Offset 0x0528 - CNVi RF_RESET pin muxing
Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default)
or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
**/
UINT32 CnviRfResetPinMux;
-/** Offset 0x0544 - CNVi CLKREQ pin muxing
+/** Offset 0x052C - CNVi CLKREQ pin muxing
Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default)
or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in
GpioPins*.h.
**/
UINT32 CnviClkreqPinMux;
-/** Offset 0x0548 - Enable Host C10 reporting through eSPI
+/** Offset 0x0530 - Enable Host C10 reporting through eSPI
Enable/disable Host C10 reporting to Device via eSPI Virtual Wire.
$EN_DIS
**/
UINT8 PchEspiHostC10ReportEnable;
-/** Offset 0x0549 - PCH USB2 PHY Power Gating enable
+/** Offset 0x0531 - PCH USB2 PHY Power Gating enable
1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
Sus Well PG
$EN_DIS
**/
UINT8 PmcUsb2PhySusPgEnable;
-/** Offset 0x054A - PCH USB OverCurrent mapping enable
+/** Offset 0x0532 - PCH USB OverCurrent mapping enable
1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
mapping allow for NOA usage of OC pins
$EN_DIS
**/
UINT8 PchUsbOverCurrentEnable;
-/** Offset 0x054B - Espi Lgmr Memory Range decode
+/** Offset 0x0533 - Espi Lgmr Memory Range decode
This option enables or disables espi lgmr
$EN_DIS
**/
UINT8 PchEspiLgmrEnable;
-/** Offset 0x054C - External V1P05 Control Ramp Timer value
+/** Offset 0x0534 - External V1P05 Control Ramp Timer value
Hold off time to be used when changing the v1p05_ctrl for external bypass value in us
**/
UINT8 PchFivrExtV1p05RailCtrlRampTmr;
-/** Offset 0x054D - External VNN Control Ramp Timer value
+/** Offset 0x0535 - External VNN Control Ramp Timer value
Hold off time to be used when changing the vnn_ctrl for external bypass value in us
**/
UINT8 PchFivrExtVnnRailCtrlRampTmr;
-/** Offset 0x054E - Set SATA DEVSLP GPIO Reset Config
+/** Offset 0x0536 - Set SATA DEVSLP GPIO Reset Config
Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset,
0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte
for each port, byte0 for port0, byte1 for port1, and so on.
**/
UINT8 SataPortsDevSlpResetConfig[8];
-/** Offset 0x0556 - PCHHOT# pin
+/** Offset 0x053E - PCHHOT# pin
Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PchHotEnable;
-/** Offset 0x0557 - SATA LED
+/** Offset 0x053F - SATA LED
SATA LED indicating SATA controller activity. 0: disable, 1: enable
$EN_DIS
**/
UINT8 SataLedEnable;
-/** Offset 0x0558 - VRAlert# Pin
+/** Offset 0x0540 - VRAlert# Pin
When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PchPmVrAlert;
-/** Offset 0x0559 - AMT Switch
+/** Offset 0x0541 - AMT Switch
Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
$EN_DIS
**/
UINT8 AmtEnabled;
-/** Offset 0x055A - WatchDog Timer Switch
+/** Offset 0x0542 - WatchDog Timer Switch
Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting
is invalid if AmtEnabled is 0.
$EN_DIS
**/
UINT8 WatchDogEnabled;
-/** Offset 0x055B - PET Progress
+/** Offset 0x0543 - PET Progress
Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
PET Events. Setting is invalid if AmtEnabled is 0.
$EN_DIS
**/
UINT8 FwProgress;
-/** Offset 0x055C - SOL Switch
+/** Offset 0x0544 - SOL Switch
Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx.
Setting is invalid if AmtEnabled is 0.
$EN_DIS
**/
UINT8 AmtSolEnabled;
-/** Offset 0x055D
+/** Offset 0x0545
**/
UINT8 Rsvd190;
-/** Offset 0x055E - OS Timer
+/** Offset 0x0546 - OS Timer
16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
**/
UINT16 WatchDogTimerOs;
-/** Offset 0x0560 - BIOS Timer
+/** Offset 0x0548 - BIOS Timer
16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0.
**/
UINT16 WatchDogTimerBios;
-/** Offset 0x0562 - PCH PCIe root port connection type
+/** Offset 0x054A - PCH PCIe root port connection type
0: built-in device, 1:slot
**/
UINT8 PcieRpSlotImplemented[29];
-/** Offset 0x057F - PCIE RP Access Control Services Extended Capability
+/** Offset 0x0567 - PCIE RP Access Control Services Extended Capability
Enable/Disable PCIE RP Access Control Services Extended Capability
**/
UINT8 PcieRpAcsEnabled[29];
-/** Offset 0x059C - PCIE RP Clock Power Management
+/** Offset 0x0584 - PCIE RP Clock Power Management
Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
can still be controlled by L1 PM substates mechanism
**/
UINT8 PcieRpEnableCpm[29];
-/** Offset 0x05B9
+/** Offset 0x05A1
**/
UINT8 Rsvd200[3];
-/** Offset 0x05BC - PCIE RP Detect Timeout Ms
+/** Offset 0x05A4 - PCIE RP Detect Timeout Ms
The number of milliseconds within 0~65535 in reference code will wait for link to
exit Detect state for enabled ports before assuming there is no device and potentially
disabling the port.
**/
UINT16 PcieRpDetectTimeoutMs[29];
-/** Offset 0x05F6 - ModPHY SUS Power Domain Dynamic Gating
+/** Offset 0x05DE - ModPHY SUS Power Domain Dynamic Gating
Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
PCH-H. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PmcModPhySusPgEnable;
-/** Offset 0x05F7 - V1p05-PHY supply external FET control
+/** Offset 0x05DF - V1p05-PHY supply external FET control
Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY
supply. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PmcV1p05PhyExtFetControlEn;
-/** Offset 0x05F8 - V1p05-IS supply external FET control
+/** Offset 0x05E0 - V1p05-IS supply external FET control
Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS
supply. 0: disable, 1: enable
$EN_DIS
**/
UINT8 PmcV1p05IsExtFetControlEn;
-/** Offset 0x05F9 - Enable/Disable PavpEnable
+/** Offset 0x05E1 - Enable/Disable PavpEnable
Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
$EN_DIS
**/
UINT8 PavpEnable;
-/** Offset 0x05FA - Enable/Disable PeiGraphicsPeimInit
+/** Offset 0x05E2 - Enable/Disable PeiGraphicsPeimInit
<b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
Disable: FSP will NOT initialize the framebuffer.
$EN_DIS
**/
UINT8 PeiGraphicsPeimInit;
-/** Offset 0x05FB - Enable D3 Hot in TCSS
+/** Offset 0x05E3 - Enable D3 Hot in TCSS
This policy will enable/disable D3 hot support in IOM
$EN_DIS
**/
UINT8 D3HotEnable;
-/** Offset 0x05FC - Enable or disable GNA device
+/** Offset 0x05E4 - Enable or disable GNA device
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 GnaEnable;
-/** Offset 0x05FD
+/** Offset 0x05E5
**/
UINT8 Rsvd210[3];
-/** Offset 0x0600 - TypeC port GPIO setting
+/** Offset 0x05E8 - TypeC port GPIO setting
GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Mtl
= MeteorLake)
**/
UINT32 IomTypeCPortPadCfg[12];
-/** Offset 0x0630 - CPU USB3 Port Over Current Pin
+/** Offset 0x0618 - CPU USB3 Port Over Current Pin
Describe the specific over current pin number of USBC Port N.
**/
UINT8 CpuUsb3OverCurrentPin[8];
-/** Offset 0x0638 - Enable D3 Cold in TCSS
+/** Offset 0x0620 - Enable D3 Cold in TCSS
This policy will enable/disable D3 cold support in IOM
$EN_DIS
**/
UINT8 D3ColdEnable;
-/** Offset 0x0639 - Enable/Disable PCIe tunneling for USB4
+/** Offset 0x0621 - Enable/Disable PCIe tunneling for USB4
Enable/Disable PCIe tunneling for USB4, default is enable
$EN_DIS
**/
UINT8 ITbtPcieTunnelingForUsb4;
-/** Offset 0x063A - Enable/Disable SkipFspGop
+/** Offset 0x0622 - Enable/Disable SkipFspGop
Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver
$EN_DIS
**/
UINT8 SkipFspGop;
-/** Offset 0x063B - Enable/Disable VPU Device
+/** Offset 0x0623 - Enable/Disable VPU Device
Enable(Default): Enable VPU Device, Disable: Disable VPU Device
$EN_DIS
**/
UINT8 VpuEnable;
-/** Offset 0x063C - TC State in TCSS
+/** Offset 0x0624 - TC State in TCSS
This TC C-State Limit in IOM
**/
UINT8 TcCstateLimit;
-/** Offset 0x063D - Display port support policy in TCSS
+/** Offset 0x0625 - Display port support policy in TCSS
This policy will enable/disable Display port support in IOM
$EN_DIS
**/
UINT8 TcNotifyIgd;
-/** Offset 0x063E
+/** Offset 0x0626
**/
UINT8 Rsvd220[2];
-/** Offset 0x0640 - Intel Graphics VBT (Video BIOS Table) Size
+/** Offset 0x0628 - Intel Graphics VBT (Video BIOS Table) Size
Size of Internal Graphics VBT Image
**/
UINT32 VbtSize;
-/** Offset 0x0644 - Platform LID Status for LFP Displays.
+/** Offset 0x062C - Platform LID Status for LFP Displays.
LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
0: LidClosed, 1: LidOpen
**/
UINT8 LidStatus;
-/** Offset 0x0645 - PchPostMemRsvd
+/** Offset 0x062D - PchPostMemRsvd
Reserved for PCH Post-Mem
$EN_DIS
**/
- UINT8 SaPostMemRsvd[7];
+ UINT8 SaPostMemRsvd[8];
-/** Offset 0x064C - Set XDCI Interrupt
- Set XDCI Interrupt from 24-119
-**/
- UINT8 SaXdciIrq;
-
-/** Offset 0x064D - Enable VMD controller
+/** Offset 0x0635 - Enable VMD controller
Enable/disable to VMD controller.0: Disable; 1: Enable(Default)
$EN_DIS
**/
UINT8 VmdEnable;
-/** Offset 0x064E - Enable VMD Global Mapping
+/** Offset 0x0636 - Enable VMD Global Mapping
Enable/disable to VMD controller.0: Disable(Default); 1: Enable
$EN_DIS
**/
UINT8 VmdGlobalMapping;
-/** Offset 0x064F - Map port under VMD
+/** Offset 0x0637 - Map port under VMD
Map/UnMap port under VMD
$EN_DIS
**/
UINT8 VmdPort[31];
-/** Offset 0x066E - VMD Port Bus
+/** Offset 0x0656 - VMD Port Bus
VMD Root port bus number.
**/
UINT8 VmdPortBus[31];
-/** Offset 0x068D - VMD Port Device
+/** Offset 0x0675 - VMD Port Device
VMD Root port device number.
**/
UINT8 VmdPortDev[31];
-/** Offset 0x06AC - VMD Port Func
+/** Offset 0x0694 - VMD Port Func
VMD Root port function number.
**/
UINT8 VmdPortFunc[31];
-/** Offset 0x06CB
+/** Offset 0x06B3
**/
UINT8 Rsvd230;
-/** Offset 0x06CC - VMD Variable
+/** Offset 0x06B4 - VMD Variable
VMD Variable Pointer.
**/
UINT32 VmdVariablePtr;
-/** Offset 0x06D0 - Temporary CfgBar address for VMD
+/** Offset 0x06B8 - Temporary CfgBar address for VMD
VMD Variable Pointer.
**/
UINT32 VmdCfgBarBase;
-/** Offset 0x06D4 - Temporary MemBar1 address for VMD
+/** Offset 0x06BC - Temporary MemBar1 address for VMD
VMD Variable Pointer.
**/
UINT32 VmdMemBar1Base;
-/** Offset 0x06D8 - Temporary MemBar2 address for VMD
+/** Offset 0x06C0 - Temporary MemBar2 address for VMD
VMD Variable Pointer.
**/
UINT32 VmdMemBar2Base;
-/** Offset 0x06DC - TCSS CPU USB PDO Programming
+/** Offset 0x06C4 - TCSS CPU USB PDO Programming
Enable/disable PDO programming for TCSS CPU USB in PEI phase. Disabling will allow
for programming during later phase. 1: enable, 0: disable
$EN_DIS
**/
UINT8 TcssCpuUsbPdoProgramming;
-/** Offset 0x06DD - Enable/Disable PMC-PD Solution
+/** Offset 0x06C5 - Enable/Disable PMC-PD Solution
This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
$EN_DIS
**/
UINT8 PmcPdEnable;
-/** Offset 0x06DE - TCSS Aux Orientation Override Enable
+/** Offset 0x06C6 - TCSS Aux Orientation Override Enable
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
**/
UINT16 TcssAuxOri;
-/** Offset 0x06E0 - TCSS HSL Orientation Override Enable
+/** Offset 0x06C8 - TCSS HSL Orientation Override Enable
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
**/
UINT16 TcssHslOri;
-/** Offset 0x06E2 - USB override in IOM
+/** Offset 0x06CA - USB override in IOM
This policy will enable/disable USB Connect override in IOM
$EN_DIS
**/
UINT8 UsbOverride;
-/** Offset 0x06E3 - ITBT Root Port Enable
+/** Offset 0x06CB - ITBT Root Port Enable
ITBT Root Port Enable, 0:Disable, 1:Enable
0:Disable, 1:Enable
**/
UINT8 ITbtPcieRootPortEn[4];
-/** Offset 0x06E7 - TCSS USB Port Enable
+/** Offset 0x06CF - TCSS USB Port Enable
Bits 0, 1, ... max Type C port control enables
**/
UINT8 UsbTcPortEn;
-/** Offset 0x06E8 - ITBTForcePowerOn Timeout value
+/** Offset 0x06D0 - ITBTForcePowerOn Timeout value
ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000.
100 = 100 ms.
**/
UINT16 ITbtForcePowerOnTimeoutInMs;
-/** Offset 0x06EA - ITbtConnectTopology Timeout value
+/** Offset 0x06D2 - ITbtConnectTopology Timeout value
ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
is 0-10000. 100 = 100 ms.
**/
UINT16 ITbtConnectTopologyTimeoutInMs;
-/** Offset 0x06EC - VCCST request for IOM
+/** Offset 0x06D4 - VCCST request for IOM
This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5
$EN_DIS
**/
UINT8 VccSt;
-/** Offset 0x06ED
+/** Offset 0x06D5
**/
UINT8 Rsvd240[1];
-/** Offset 0x06EE - ITBT DMA LTR
+/** Offset 0x06D6 - ITBT DMA LTR
TCSS DMA1, DMA2 LTR value
**/
UINT16 ITbtDmaLtr[2];
-/** Offset 0x06F2 - Enable/Disable CrashLog
+/** Offset 0x06DA - Enable/Disable CrashLog
Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog
$EN_DIS
**/
UINT8 CpuCrashLogEnable;
-/** Offset 0x06F3 - Enable/Disable PTM
+/** Offset 0x06DB - Enable/Disable PTM
This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
$EN_DIS
**/
UINT8 PtmEnabled[4];
-/** Offset 0x06F7 - PCIE RP Ltr Enable
+/** Offset 0x06DF - PCIE RP Ltr Enable
Latency Tolerance Reporting Mechanism.
**/
UINT8 SaPcieItbtRpLtrEnable[4];
-/** Offset 0x06FB - PCIE RP Snoop Latency Override Mode
+/** Offset 0x06E3 - PCIE RP Snoop Latency Override Mode
Latency Tolerance Reporting, Snoop Latency Override Mode.
**/
UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4];
-/** Offset 0x06FF - PCIE RP Snoop Latency Override Multiplier
+/** Offset 0x06E7 - PCIE RP Snoop Latency Override Multiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
**/
UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4];
-/** Offset 0x0703
+/** Offset 0x06EB
**/
UINT8 Rsvd250[1];
-/** Offset 0x0704 - PCIE RP Snoop Latency Override Value
+/** Offset 0x06EC - PCIE RP Snoop Latency Override Value
Latency Tolerance Reporting, Snoop Latency Override Value.
**/
UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4];
-/** Offset 0x070C - PCIE RP Non Snoop Latency Override Mode
+/** Offset 0x06F4 - PCIE RP Non Snoop Latency Override Mode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
**/
UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4];
-/** Offset 0x0710 - PCIE RP Non Snoop Latency Override Multiplier
+/** Offset 0x06F8 - PCIE RP Non Snoop Latency Override Multiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
**/
UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4];
-/** Offset 0x0714 - PCIE RP Non Snoop Latency Override Value
+/** Offset 0x06FC - PCIE RP Non Snoop Latency Override Value
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
**/
UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4];
-/** Offset 0x071C - Force LTR Override
+/** Offset 0x0704 - Force LTR Override
Force LTR Override.
**/
UINT8 SaPcieItbtRpForceLtrOverride[4];
-/** Offset 0x0720 - PCIE RP Ltr Config Lock
+/** Offset 0x0708 - PCIE RP Ltr Config Lock
0: Disable; 1: Enable.
**/
UINT8 SaPcieItbtRpLtrConfigLock[4];
-/** Offset 0x0724 - Enable or Disable TXT
+/** Offset 0x070C - Enable or Disable TXT
Enables utilization of additional hardware capabilities provided by Intel (R) Trusted
Execution Technology. Changes require a full power cycle to take effect. <b>0:
Disable</b>, 1: Enable.
@@ -1542,38 +1533,38 @@ typedef struct {
**/
UINT8 TxtEnable;
-/** Offset 0x0725
+/** Offset 0x070D
**/
UINT8 Rsvd260[3];
-/** Offset 0x0728 - CpuBistData
+/** Offset 0x0710 - CpuBistData
Pointer CPU BIST Data
**/
UINT32 CpuBistData;
-/** Offset 0x072C - CpuMpPpi
+/** Offset 0x0714 - CpuMpPpi
<b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
If not NULL, FSP will use the boot loader's implementation of multiprocessing.
See section 5.1.4 of the FSP Integration Guide for more details.
**/
UINT32 CpuMpPpi;
-/** Offset 0x0730 - Boot frequency
+/** Offset 0x0718 - Boot frequency
Select the performance state that the BIOS will set starting from reset vector.
0: Maximum battery performance. 1: Maximum non-turbo performance. <b>2: Turbo performance </b>
0:0, 1:1, 2:2
**/
UINT8 BootFrequency;
-/** Offset 0x0731
+/** Offset 0x0719
**/
UINT8 CpuPostMemRsvd[2];
-/** Offset 0x0733
+/** Offset 0x071B
**/
UINT8 Rsvd270[1];
-/** Offset 0x0734 - PpinSupport to view Protected Processor Inventory Number
+/** Offset 0x071C - PpinSupport to view Protected Processor Inventory Number
PPIN Feature Support to view Protected Processor Inventory Number. Disable to turn
off this feature. When 'PPIN Enable Mode' is selected, this shows second option
where feature can be enabled based on EOM (End of Manufacturing) flag or it is
@@ -1582,7 +1573,7 @@ typedef struct {
**/
UINT8 PpinSupport;
-/** Offset 0x0735 - Memory size per thread allocated for Processor Trace
+/** Offset 0x071D - Memory size per thread allocated for Processor Trace
Memory size per thread for Processor Trace. Processor Trace requires 2^N alignment
and size in bytes per thread, from 4KB to 128MB.\n
<b> 0xff:none </b>, 0:4k, 0x1:8k, 0x2:16k, 0x3:32k, 0x4:64k, 0x5:128k, 0x6:256k,
@@ -1590,1365 +1581,1365 @@ typedef struct {
**/
UINT8 ProcessorTraceMemSize;
-/** Offset 0x0736 - Smbios Type4 Max Speed Override
+/** Offset 0x071E - Smbios Type4 Max Speed Override
Provide the option for platform to override the MaxSpeed field of Smbios Type 4.
If this value is not zero, it dominates the field.
**/
UINT16 SmbiosType4MaxSpeedOverride;
-/** Offset 0x0738 - Advanced Encryption Standard (AES) feature
+/** Offset 0x0720 - Advanced Encryption Standard (AES) feature
Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
$EN_DIS
**/
UINT8 AesEnable;
-/** Offset 0x0739 - AvxDisable
+/** Offset 0x0721 - AvxDisable
Enable/Disable the AVX and AVX2 Instructions
0: Enable, 1: Disable
**/
UINT8 AvxDisable;
-/** Offset 0x073A - X2ApicEnable
+/** Offset 0x0722 - X2ApicEnable
Enable/Disable X2APIC Operating Mode. When this option is configured as 'Enabled',
'VT-d' option must be 'Enabled' and 'X2APIC Opt Out' option must be 'Disabled' as well.
$EN_DIS
**/
UINT8 X2ApicEnable;
-/** Offset 0x073B - ProcHot Demotion Algorithm configuration
+/** Offset 0x0723 - ProcHot Demotion Algorithm configuration
ProcHot Demotion Algorithm configuration. Hardware Default/Disable; 0: Disable;<b>
1: Hardware Default</b>
0: Disable, 1: Hardware Default
**/
UINT8 ProcHotDemotion;
-/** Offset 0x073C - AC Split Lock
+/** Offset 0x0724 - AC Split Lock
Enable/Disable #AC check on split lock. <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 AcSplitLock;
-/** Offset 0x073D - GP Fault UC Lock
+/** Offset 0x0725 - GP Fault UC Lock
Enable/Disable GP Fault check on UC lock. <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 GpfaultUcLock;
-/** Offset 0x073E - L2 QoS Enumeration
+/** Offset 0x0726 - L2 QoS Enumeration
Enable/Disable L2 QoS Enumeration. <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 L2QosEnumeration;
-/** Offset 0x073F
+/** Offset 0x0727
**/
UINT8 EmbReserved1FspsUpd[1];
-/** Offset 0x0740 - ReservedCpuPostMemProduction
+/** Offset 0x0728 - ReservedCpuPostMemProduction
Reserved for CPU Post-Mem Production
$EN_DIS
**/
UINT8 ReservedCpuPostMemProduction[56];
-/** Offset 0x0778 - Enable Power Optimizer
+/** Offset 0x0760 - Enable Power Optimizer
Enable DMI Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 PchPwrOptEnable;
-/** Offset 0x0779 - PCH Flash Protection Ranges Write Enble
+/** Offset 0x0761 - PCH Flash Protection Ranges Write Enble
Write or erase is blocked by hardware.
**/
UINT8 PchWriteProtectionEnable[5];
-/** Offset 0x077E - PCH Flash Protection Ranges Read Enble
+/** Offset 0x0766 - PCH Flash Protection Ranges Read Enble
Read is blocked by hardware.
**/
UINT8 PchReadProtectionEnable[5];
-/** Offset 0x0783
+/** Offset 0x076B
**/
UINT8 Rsvd280[1];
-/** Offset 0x0784 - PCH Protect Range Limit
+/** Offset 0x076C - PCH Protect Range Limit
Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
limit comparison.
**/
UINT16 PchProtectedRangeLimit[5];
-/** Offset 0x078E - PCH Protect Range Base
+/** Offset 0x0776 - PCH Protect Range Base
Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
**/
UINT16 PchProtectedRangeBase[5];
-/** Offset 0x0798 - Enable Pme
+/** Offset 0x0780 - Enable Pme
Enable Azalia wake-on-ring.
$EN_DIS
**/
UINT8 PchHdaPme;
-/** Offset 0x0799 - HD Audio Link Frequency
+/** Offset 0x0781 - HD Audio Link Frequency
HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
0: 6MHz, 1: 12MHz, 2: 24MHz
**/
UINT8 PchHdaLinkFrequency;
-/** Offset 0x079A - Enable PCH ISH SPI Cs0 pins assigned
+/** Offset 0x0782 - Enable PCH ISH SPI Cs0 pins assigned
Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshSpiCs0Enable[1];
-/** Offset 0x079B - Enable PCH Io Apic Entry 24-119
+/** Offset 0x0783 - Enable PCH Io Apic Entry 24-119
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchIoApicEntry24_119;
-/** Offset 0x079C - PCH Io Apic ID
+/** Offset 0x0784 - PCH Io Apic ID
This member determines IOAPIC ID. Default is 0x02.
**/
UINT8 PchIoApicId;
-/** Offset 0x079D - Enable PCH ISH SPI pins assigned
+/** Offset 0x0785 - Enable PCH ISH SPI pins assigned
Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshSpiEnable[1];
-/** Offset 0x079E - Enable PCH ISH UART pins assigned
+/** Offset 0x0786 - Enable PCH ISH UART pins assigned
Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshUartEnable[2];
-/** Offset 0x07A0 - Enable PCH ISH I2C pins assigned
+/** Offset 0x0788 - Enable PCH ISH I2C pins assigned
Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshI2cEnable[3];
-/** Offset 0x07A3 - Enable PCH ISH I3C pins assigned
+/** Offset 0x078B - Enable PCH ISH I3C pins assigned
Set if ISH I3C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshI3cEnable;
-/** Offset 0x07A4 - Enable PCH ISH GP pins assigned
+/** Offset 0x078C - Enable PCH ISH GP pins assigned
Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshGpEnable[12];
-/** Offset 0x07B0 - PCH ISH PDT Unlock Msg
+/** Offset 0x0798 - PCH ISH PDT Unlock Msg
0: False; 1: True.
$EN_DIS
**/
UINT8 PchIshPdtUnlock;
-/** Offset 0x07B1 - PCH ISH MSI Interrupts
+/** Offset 0x0799 - PCH ISH Disable MSI Interrupts
0: False; 1: True.
$EN_DIS
**/
UINT8 PchIshMsiInterrupt;
-/** Offset 0x07B2 - Enable PCH Lan LTR capabilty of PCH internal LAN
+/** Offset 0x079A - Enable PCH Lan LTR capabilty of PCH internal LAN
0: Disable; 1: Enable.
$EN_DIS
**/
UINT8 PchLanLtrEnable;
-/** Offset 0x07B3 - Enable LOCKDOWN BIOS LOCK
+/** Offset 0x079B - Enable LOCKDOWN BIOS LOCK
Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
protection.
$EN_DIS
**/
UINT8 PchLockDownBiosLock;
-/** Offset 0x07B4 - PCH Compatibility Revision ID
+/** Offset 0x079C - PCH Compatibility Revision ID
This member describes whether or not the CRID feature of PCH should be enabled.
$EN_DIS
**/
UINT8 PchCrid;
-/** Offset 0x07B5 - RTC BIOS Interface Lock
+/** Offset 0x079D - RTC BIOS Interface Lock
Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed.
$EN_DIS
**/
UINT8 RtcBiosInterfaceLock;
-/** Offset 0x07B6 - RTC Cmos Memory Lock
+/** Offset 0x079E - RTC Cmos Memory Lock
Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
and and lower 128-byte bank of RTC RAM.
$EN_DIS
**/
UINT8 RtcMemoryLock;
-/** Offset 0x07B7 - Enable PCIE RP HotPlug
+/** Offset 0x079F - Enable PCIE RP HotPlug
Indicate whether the root port is hot plug available.
**/
UINT8 PcieRpHotPlug[29];
-/** Offset 0x07D4 - Enable PCIE RP Pm Sci
+/** Offset 0x07BC - Enable PCIE RP Pm Sci
Indicate whether the root port power manager SCI is enabled.
$EN_DIS
**/
UINT8 PcieRpPmSci[29];
-/** Offset 0x07F1 - Enable PCIE RP Transmitter Half Swing
+/** Offset 0x07D9 - Enable PCIE RP Transmitter Half Swing
Indicate whether the Transmitter Half Swing is enabled.
**/
UINT8 PcieRpTransmitterHalfSwing[29];
-/** Offset 0x080E - Enable PCIE RP Clk Req Detect
+/** Offset 0x07F6 - Enable PCIE RP Clk Req Detect
Probe CLKREQ# signal before enabling CLKREQ# based power management.
**/
UINT8 PcieRpClkReqDetect[29];
-/** Offset 0x082B - PCIE RP Advanced Error Report
+/** Offset 0x0813 - PCIE RP Advanced Error Report
Indicate whether the Advanced Error Reporting is enabled.
**/
UINT8 PcieRpAdvancedErrorReporting[29];
-/** Offset 0x0848 - PCIE RP Unsupported Request Report
+/** Offset 0x0830 - PCIE RP Unsupported Request Report
Indicate whether the Unsupported Request Report is enabled.
**/
UINT8 PcieRpUnsupportedRequestReport[29];
-/** Offset 0x0865 - PCIE RP Fatal Error Report
+/** Offset 0x084D - PCIE RP Fatal Error Report
Indicate whether the Fatal Error Report is enabled.
**/
UINT8 PcieRpFatalErrorReport[29];
-/** Offset 0x0882 - PCIE RP No Fatal Error Report
+/** Offset 0x086A - PCIE RP No Fatal Error Report
Indicate whether the No Fatal Error Report is enabled.
**/
UINT8 PcieRpNoFatalErrorReport[29];
-/** Offset 0x089F - PCIE RP Correctable Error Report
+/** Offset 0x0887 - PCIE RP Correctable Error Report
Indicate whether the Correctable Error Report is enabled.
**/
UINT8 PcieRpCorrectableErrorReport[29];
-/** Offset 0x08BC - PCIE RP System Error On Fatal Error
+/** Offset 0x08A4 - PCIE RP System Error On Fatal Error
Indicate whether the System Error on Fatal Error is enabled.
**/
UINT8 PcieRpSystemErrorOnFatalError[29];
-/** Offset 0x08D9 - PCIE RP System Error On Non Fatal Error
+/** Offset 0x08C1 - PCIE RP System Error On Non Fatal Error
Indicate whether the System Error on Non Fatal Error is enabled.
**/
UINT8 PcieRpSystemErrorOnNonFatalError[29];
-/** Offset 0x08F6 - PCIE RP System Error On Correctable Error
+/** Offset 0x08DE - PCIE RP System Error On Correctable Error
Indicate whether the System Error on Correctable Error is enabled.
**/
UINT8 PcieRpSystemErrorOnCorrectableError[29];
-/** Offset 0x0913 - PCIE RP Max Payload
+/** Offset 0x08FB - PCIE RP Max Payload
Max Payload Size supported, Default 256B, see enum PCH_PCIE_MAX_PAYLOAD.
**/
UINT8 PcieRpMaxPayload[29];
-/** Offset 0x0930 - Touch Host Controller Assignment
+/** Offset 0x0918 - Touch Host Controller Assignment
Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1
**/
UINT8 ThcAssignment[2];
-/** Offset 0x0932 - Touch Host Controller Interrupt Pin Mux
+/** Offset 0x091A - Touch Host Controller Interrupt Pin Mux
Set THC Pin Muxing Value if signal can be enabled on multiple pads. Refer to GPIO_*_MUXING_THC_SPIx_INTB_*
for possible values.
**/
UINT8 ThcInterruptPinMuxing[8];
-/** Offset 0x093A - Touch Host Controller Mode
+/** Offset 0x0922 - Touch Host Controller Mode
Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid
**/
UINT8 ThcMode[2];
-/** Offset 0x093C - Touch Host Controller Wake On Touch
+/** Offset 0x0924 - Touch Host Controller Wake On Touch
Based on this setting vGPIO for given THC will be in native mode, and additional
_CRS for wake will be exposed in ACPI
**/
UINT8 ThcWakeOnTouch[2];
-/** Offset 0x093E
+/** Offset 0x0926
**/
UINT8 Rsvd290[2];
-/** Offset 0x0940 - Touch Host Controller Active Ltr
+/** Offset 0x0928 - Touch Host Controller Active Ltr
Expose Active Ltr for OS driver to set
**/
UINT32 ThcActiveLtr[2];
-/** Offset 0x0948 - Touch Host Controller Idle Ltr
+/** Offset 0x0930 - Touch Host Controller Idle Ltr
Expose Idle Ltr for OS driver to set
**/
UINT32 ThcIdleLtr[2];
-/** Offset 0x0950 - Touch Host Controller Hid Over Spi ResetPad
+/** Offset 0x0938 - Touch Host Controller Hid Over Spi ResetPad
Hid Over Spi ResetPad
**/
UINT32 ThcResetPad[2];
-/** Offset 0x0958 - Touch Host Controller Hid Over Spi ResetPad Trigger
+/** Offset 0x0940 - Touch Host Controller Hid Over Spi ResetPad Trigger
Hid Over Spi Reset Pad Trigger 0x0:Low, 0x1:High
**/
UINT32 ThcResetPadTrigger[2];
-/** Offset 0x0960 - Touch Host Controller Hid Over Spi Connection Speed
+/** Offset 0x0948 - Touch Host Controller Hid Over Spi Connection Speed
Hid Over Spi Connection Speed - SPI Frequency
**/
UINT32 ThcHidSpiConnectionSpeed[2];
-/** Offset 0x0968 - Touch Host Controller Hid Over Spi Limit PacketSize
+/** Offset 0x0950 - Touch Host Controller Hid Over Spi Limit PacketSize
When set, limits SPI read & write packet size to 64B. Otherwise, THC uses Max Soc
packet size for SPI Read and Write 0x0- Max Soc Packet Size, 0x11 - 64 Bytes
**/
UINT32 ThcHidSpiLimitPacketSize[2];
-/** Offset 0x0970 - Touch Host Controller Hid Over Spi Limit PacketSize
+/** Offset 0x0958 - Touch Host Controller Hid Over Spi Limit PacketSize
Minimum amount of delay the THC/QUICKSPI driver must wait between end of write operation
and begin of read operation. This value shall be in 10us multiples 0x0: Disabled,
1-65535 (0xFFFF) - up to 655350 us
**/
UINT32 ThcPerformanceLimitation[2];
-/** Offset 0x0978 - Touch Host Controller Hid Over Spi Input Report Header Address
+/** Offset 0x0960 - Touch Host Controller Hid Over Spi Input Report Header Address
Hid Over Spi Input Report Header Address
**/
UINT32 ThcHidSpiInputReportHeaderAddress[2];
-/** Offset 0x0980 - Touch Host Controller Hid Over Spi Input Report Body Address
+/** Offset 0x0968 - Touch Host Controller Hid Over Spi Input Report Body Address
Hid Over Spi Input Report Body Address
**/
UINT32 ThcHidSpiInputReportBodyAddress[2];
-/** Offset 0x0988 - Touch Host Controller Hid Over Spi Output Report Address
+/** Offset 0x0970 - Touch Host Controller Hid Over Spi Output Report Address
Hid Over Spi Output Report Address
**/
UINT32 ThcHidSpiOutputReportAddress[2];
-/** Offset 0x0990 - Touch Host Controller Hid Over Spi Read Opcode
+/** Offset 0x0978 - Touch Host Controller Hid Over Spi Read Opcode
Hid Over Spi Read Opcode
**/
UINT32 ThcHidSpiReadOpcode[2];
-/** Offset 0x0998 - Touch Host Controller Hid Over Spi Write Opcode
+/** Offset 0x0980 - Touch Host Controller Hid Over Spi Write Opcode
Hid Over Spi Write Opcode
**/
UINT32 ThcHidSpiWriteOpcode[2];
-/** Offset 0x09A0 - Touch Host Controller Hid Over Spi Flags
+/** Offset 0x0988 - Touch Host Controller Hid Over Spi Flags
Hid Over Spi Flags 0x0:Single SPI Mode, 0x4000:Dual SPI Mode, 0x8000:Quad SPI Mode
**/
UINT32 ThcHidSpiFlags[2];
-/** Offset 0x09A8 - Touch Host Controller Hid Over Spi Reset Sequencing Delay [ms]
+/** Offset 0x0990 - Touch Host Controller Hid Over Spi Reset Sequencing Delay [ms]
Policy control for reset sequencing delay (ACPI _INI, _RST) default 300ms
**/
UINT16 ThcResetSequencingDelay[2];
-/** Offset 0x09AC - PCIE RP Pcie Speed
+/** Offset 0x0994 - PCIE RP Pcie Speed
Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
PCIE_SPEED).
**/
UINT8 PcieRpPcieSpeed[29];
-/** Offset 0x09C9 - PCIE RP Physical Slot Number
+/** Offset 0x09B1 - PCIE RP Physical Slot Number
Indicates the slot number for the root port. Default is the value as root port index.
**/
UINT8 PcieRpPhysicalSlotNumber[29];
-/** Offset 0x09E6 - PCIE RP Completion Timeout
+/** Offset 0x09CE - PCIE RP Completion Timeout
The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
**/
UINT8 PcieRpCompletionTimeout[29];
-/** Offset 0x0A03 - PCIE RP Aspm
+/** Offset 0x09EB - PCIE RP Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
PchPcieAspmAutoConfig.
**/
UINT8 PcieRpAspm[29];
-/** Offset 0x0A20 - PCIE RP L1 Substates
+/** Offset 0x0A08 - PCIE RP L1 Substates
The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
Default is PchPcieL1SubstatesL1_1_2.
**/
UINT8 PcieRpL1Substates[29];
-/** Offset 0x0A3D - PCIE RP Ltr Enable
+/** Offset 0x0A25 - PCIE RP Ltr Enable
Latency Tolerance Reporting Mechanism.
**/
UINT8 PcieRpLtrEnable[29];
-/** Offset 0x0A5A - PCIE RP Ltr Config Lock
+/** Offset 0x0A42 - PCIE RP Ltr Config Lock
0: Disable; 1: Enable.
**/
UINT8 PcieRpLtrConfigLock[29];
-/** Offset 0x0A77 - PCIE RP override default settings for EQ
+/** Offset 0x0A5F - PCIE RP override default settings for EQ
Choose PCIe EQ method
$EN_DIS
**/
UINT8 PcieEqOverrideDefault[29];
-/** Offset 0x0A94 - PCIE RP choose EQ method
+/** Offset 0x0A7C - PCIE RP choose EQ method
Choose PCIe EQ method
0: HardwareEq, 1: FixedEq
**/
UINT8 PcieGen3EqMethod[29];
-/** Offset 0x0AB1 - PCIE RP choose EQ mode
+/** Offset 0x0A99 - PCIE RP choose EQ mode
Choose PCIe EQ mode
0: PresetEq, 1: CoefficientEq
**/
UINT8 PcieGen3EqMode[29];
-/** Offset 0x0ACE - PCIE RP EQ local transmitter override
+/** Offset 0x0AB6 - PCIE RP EQ local transmitter override
Enable/Disable local transmitter override
$EN_DIS
**/
UINT8 PcieGen3EqLocalTxOverrideEn[29];
-/** Offset 0x0AEB - PCI RP number of valid list entries
+/** Offset 0x0AD3 - PCI RP number of valid list entries
Select number of presets or coefficients depending on the mode
**/
UINT8 PcieGen3EqPh3NoOfPresetOrCoeff[29];
-/** Offset 0x0B08 - PCIE RP pre-cursor coefficient list
+/** Offset 0x0AF0 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PreCursor0List[29];
-/** Offset 0x0B25 - PCIE RP post-cursor coefficient list
+/** Offset 0x0B0D - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PostCursor0List[29];
-/** Offset 0x0B42 - PCIE RP pre-cursor coefficient list
+/** Offset 0x0B2A - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PreCursor1List[29];
-/** Offset 0x0B5F - PCIE RP post-cursor coefficient list
+/** Offset 0x0B47 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PostCursor1List[29];
-/** Offset 0x0B7C - PCIE RP pre-cursor coefficient list
+/** Offset 0x0B64 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PreCursor2List[29];
-/** Offset 0x0B99 - PCIE RP post-cursor coefficient list
+/** Offset 0x0B81 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PostCursor2List[29];
-/** Offset 0x0BB6 - PCIR RP pre-cursor coefficient list
+/** Offset 0x0B9E - PCIR RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PreCursor3List[29];
-/** Offset 0x0BD3 - PCIE RP post-cursor coefficient list
+/** Offset 0x0BBB - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PostCursor3List[29];
-/** Offset 0x0BF0 - PCIE RP pre-cursor coefficient list
+/** Offset 0x0BD8 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PreCursor4List[29];
-/** Offset 0x0C0D - PCIE RP post-cursor coefficient list
+/** Offset 0x0BF5 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PostCursor4List[29];
-/** Offset 0x0C2A - PCIE RP pre-cursor coefficient list
+/** Offset 0x0C12 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PreCursor5List[29];
-/** Offset 0x0C47 - PCIE RP post-cursor coefficient list
+/** Offset 0x0C2F - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PostCursor5List[29];
-/** Offset 0x0C64 - PCIE RP pre-cursor coefficient list
+/** Offset 0x0C4C - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PreCursor6List[29];
-/** Offset 0x0C81 - PCIe post-cursor coefficient list
+/** Offset 0x0C69 - PCIe post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PostCursor6List[29];
-/** Offset 0x0C9E - PCIE RP pre-cursor coefficient list
+/** Offset 0x0C86 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PreCursor7List[29];
-/** Offset 0x0CBB - PCIE RP post-cursor coefficient list
+/** Offset 0x0CA3 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PostCursor7List[29];
-/** Offset 0x0CD8 - PCIE RP pre-cursor coefficient list
+/** Offset 0x0CC0 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PreCursor8List[29];
-/** Offset 0x0CF5 - PCIE RP post-cursor coefficient list
+/** Offset 0x0CDD - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PostCursor8List[29];
-/** Offset 0x0D12 - PCIE RP pre-cursor coefficient list
+/** Offset 0x0CFA - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PreCursor9List[29];
-/** Offset 0x0D2F - PCIE RP post-cursor coefficient list
+/** Offset 0x0D17 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3PostCursor9List[29];
-/** Offset 0x0D4C - PCIE RP preset list
+/** Offset 0x0D34 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3Preset0List[29];
-/** Offset 0x0D69 - PCIe preset list
+/** Offset 0x0D51 - PCIe preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3Preset1List[29];
-/** Offset 0x0D86 - PCIE RP preset list
+/** Offset 0x0D6E - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3Preset2List[29];
-/** Offset 0x0DA3 - PCIE RP preset list
+/** Offset 0x0D8B - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3Preset3List[29];
-/** Offset 0x0DC0 - PCIE RP preset list
+/** Offset 0x0DA8 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3Preset4List[29];
-/** Offset 0x0DDD - PCIE RP preset list
+/** Offset 0x0DC5 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3Preset5List[29];
-/** Offset 0x0DFA - PCIE RP preset list
+/** Offset 0x0DE2 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3Preset6List[29];
-/** Offset 0x0E17 - PCIE RP preset list
+/** Offset 0x0DFF - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3Preset7List[29];
-/** Offset 0x0E34 - PCIE RP preset list
+/** Offset 0x0E1C - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3Preset8List[29];
-/** Offset 0x0E51 - PCIE RP preset list
+/** Offset 0x0E39 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3Preset9List[29];
-/** Offset 0x0E6E - PCIE RP preset list
+/** Offset 0x0E56 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen3EqPh3Preset10List[29];
-/** Offset 0x0E8B - PCIe EQ phase 1 downstream transmitter port preset
+/** Offset 0x0E73 - PCIe EQ phase 1 downstream transmitter port preset
Allows to select the downstream port preset value that will be used during phase
1 of equalization
**/
UINT8 PcieGen3EqPh1DpTxPreset[29];
-/** Offset 0x0EA8 - PCIE RP EQ phase 1 upstream tranmitter port preset
+/** Offset 0x0E90 - PCIE RP EQ phase 1 upstream tranmitter port preset
Allows to select the upstream port preset value that will be used during phase 1
of equalization
**/
UINT8 PcieGen3EqPh1UpTxPreset[29];
-/** Offset 0x0EC5 - PCIE RP EQ phase 2 local transmitter override preset
+/** Offset 0x0EAD - PCIE RP EQ phase 2 local transmitter override preset
Allows to select the value of the preset used during phase 2 local transmitter override
**/
UINT8 PcieGen3EqPh2LocalTxOverridePreset[29];
-/** Offset 0x0EE2 - PCIE RP choose EQ method
+/** Offset 0x0ECA - PCIE RP choose EQ method
Choose PCIe EQ method
0: HardwareEq, 1: FixedEq
**/
UINT8 PcieGen4EqMethod[29];
-/** Offset 0x0EFF - PCIE RP choose EQ mode
+/** Offset 0x0EE7 - PCIE RP choose EQ mode
Choose PCIe EQ mode
0: PresetEq, 1: CoefficientEq
**/
UINT8 PcieGen4EqMode[29];
-/** Offset 0x0F1C - PCIE RP EQ local transmitter override
+/** Offset 0x0F04 - PCIE RP EQ local transmitter override
Enable/Disable local transmitter override
$EN_DIS
**/
UINT8 PcieGen4EqLocalTxOverrideEn[29];
-/** Offset 0x0F39 - PCI RP number of valid list entries
+/** Offset 0x0F21 - PCI RP number of valid list entries
Select number of presets or coefficients depending on the mode
**/
UINT8 PcieGen4EqPh3NoOfPresetOrCoeff[29];
-/** Offset 0x0F56 - PCIE RP pre-cursor coefficient list
+/** Offset 0x0F3E - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PreCursor0List[29];
-/** Offset 0x0F73 - PCIE RP post-cursor coefficient list
+/** Offset 0x0F5B - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PostCursor0List[29];
-/** Offset 0x0F90 - PCIE RP pre-cursor coefficient list
+/** Offset 0x0F78 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PreCursor1List[29];
-/** Offset 0x0FAD - PCIE RP post-cursor coefficient list
+/** Offset 0x0F95 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PostCursor1List[29];
-/** Offset 0x0FCA - PCIE RP pre-cursor coefficient list
+/** Offset 0x0FB2 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PreCursor2List[29];
-/** Offset 0x0FE7 - PCIE RP post-cursor coefficient list
+/** Offset 0x0FCF - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PostCursor2List[29];
-/** Offset 0x1004 - PCIR RP pre-cursor coefficient list
+/** Offset 0x0FEC - PCIR RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PreCursor3List[29];
-/** Offset 0x1021 - PCIE RP post-cursor coefficient list
+/** Offset 0x1009 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PostCursor3List[29];
-/** Offset 0x103E - PCIE RP pre-cursor coefficient list
+/** Offset 0x1026 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PreCursor4List[29];
-/** Offset 0x105B - PCIE RP post-cursor coefficient list
+/** Offset 0x1043 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PostCursor4List[29];
-/** Offset 0x1078 - PCIE RP pre-cursor coefficient list
+/** Offset 0x1060 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PreCursor5List[29];
-/** Offset 0x1095 - PCIE RP post-cursor coefficient list
+/** Offset 0x107D - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PostCursor5List[29];
-/** Offset 0x10B2 - PCIE RP pre-cursor coefficient list
+/** Offset 0x109A - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PreCursor6List[29];
-/** Offset 0x10CF - PCIe post-cursor coefficient list
+/** Offset 0x10B7 - PCIe post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PostCursor6List[29];
-/** Offset 0x10EC - PCIE RP pre-cursor coefficient list
+/** Offset 0x10D4 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PreCursor7List[29];
-/** Offset 0x1109 - PCIE RP post-cursor coefficient list
+/** Offset 0x10F1 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PostCursor7List[29];
-/** Offset 0x1126 - PCIE RP pre-cursor coefficient list
+/** Offset 0x110E - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PreCursor8List[29];
-/** Offset 0x1143 - PCIE RP post-cursor coefficient list
+/** Offset 0x112B - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PostCursor8List[29];
-/** Offset 0x1160 - PCIE RP pre-cursor coefficient list
+/** Offset 0x1148 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PreCursor9List[29];
-/** Offset 0x117D - PCIE RP post-cursor coefficient list
+/** Offset 0x1165 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3PostCursor9List[29];
-/** Offset 0x119A - PCIE RP preset list
+/** Offset 0x1182 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3Preset0List[29];
-/** Offset 0x11B7 - PCIe preset list
+/** Offset 0x119F - PCIe preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3Preset1List[29];
-/** Offset 0x11D4 - PCIE RP preset list
+/** Offset 0x11BC - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3Preset2List[29];
-/** Offset 0x11F1 - PCIE RP preset list
+/** Offset 0x11D9 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3Preset3List[29];
-/** Offset 0x120E - PCIE RP preset list
+/** Offset 0x11F6 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3Preset4List[29];
-/** Offset 0x122B - PCIE RP preset list
+/** Offset 0x1213 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3Preset5List[29];
-/** Offset 0x1248 - PCIE RP preset list
+/** Offset 0x1230 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3Preset6List[29];
-/** Offset 0x1265 - PCIE RP preset list
+/** Offset 0x124D - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3Preset7List[29];
-/** Offset 0x1282 - PCIE RP preset list
+/** Offset 0x126A - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3Preset8List[29];
-/** Offset 0x129F - PCIE RP preset list
+/** Offset 0x1287 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3Preset9List[29];
-/** Offset 0x12BC - PCIE RP preset list
+/** Offset 0x12A4 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen4EqPh3Preset10List[29];
-/** Offset 0x12D9 - PCIe EQ phase 1 downstream transmitter port preset
+/** Offset 0x12C1 - PCIe EQ phase 1 downstream transmitter port preset
Allows to select the downstream port preset value that will be used during phase
1 of equalization
**/
UINT8 PcieGen4EqPh1DpTxPreset[29];
-/** Offset 0x12F6 - PCIE RP EQ phase 1 upstream tranmitter port preset
+/** Offset 0x12DE - PCIE RP EQ phase 1 upstream tranmitter port preset
Allows to select the upstream port preset value that will be used during phase 1
of equalization
**/
UINT8 PcieGen4EqPh1UpTxPreset[29];
-/** Offset 0x1313 - PCIE RP EQ phase 2 local transmitter override preset
+/** Offset 0x12FB - PCIE RP EQ phase 2 local transmitter override preset
Allows to select the value of the preset used during phase 2 local transmitter override
**/
UINT8 PcieGen4EqPh2LocalTxOverridePreset[29];
-/** Offset 0x1330 - PCIE RP choose EQ method
+/** Offset 0x1318 - PCIE RP choose EQ method
Choose PCIe EQ method
0: HardwareEq, 1: FixedEq
**/
UINT8 PcieGen5EqMethod[29];
-/** Offset 0x134D - PCIE RP choose EQ mode
+/** Offset 0x1335 - PCIE RP choose EQ mode
Choose PCIe EQ mode
0: PresetEq, 1: CoefficientEq
**/
UINT8 PcieGen5EqMode[29];
-/** Offset 0x136A - PCIE RP EQ local transmitter override
+/** Offset 0x1352 - PCIE RP EQ local transmitter override
Enable/Disable local transmitter override
$EN_DIS
**/
UINT8 PcieGen5EqLocalTxOverrideEn[29];
-/** Offset 0x1387 - PCI RP number of valid list entries
+/** Offset 0x136F - PCI RP number of valid list entries
Select number of presets or coefficients depending on the mode
**/
UINT8 PcieGen5EqPh3NoOfPresetOrCoeff[29];
-/** Offset 0x13A4 - PCIE RP pre-cursor coefficient list
+/** Offset 0x138C - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PreCursor0List[29];
-/** Offset 0x13C1 - PCIE RP post-cursor coefficient list
+/** Offset 0x13A9 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PostCursor0List[29];
-/** Offset 0x13DE - PCIE RP pre-cursor coefficient list
+/** Offset 0x13C6 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PreCursor1List[29];
-/** Offset 0x13FB - PCIE RP post-cursor coefficient list
+/** Offset 0x13E3 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PostCursor1List[29];
-/** Offset 0x1418 - PCIE RP pre-cursor coefficient list
+/** Offset 0x1400 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PreCursor2List[29];
-/** Offset 0x1435 - PCIE RP post-cursor coefficient list
+/** Offset 0x141D - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PostCursor2List[29];
-/** Offset 0x1452 - PCIR RP pre-cursor coefficient list
+/** Offset 0x143A - PCIR RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PreCursor3List[29];
-/** Offset 0x146F - PCIE RP post-cursor coefficient list
+/** Offset 0x1457 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PostCursor3List[29];
-/** Offset 0x148C - PCIE RP pre-cursor coefficient list
+/** Offset 0x1474 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PreCursor4List[29];
-/** Offset 0x14A9 - PCIE RP post-cursor coefficient list
+/** Offset 0x1491 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PostCursor4List[29];
-/** Offset 0x14C6 - PCIE RP pre-cursor coefficient list
+/** Offset 0x14AE - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PreCursor5List[29];
-/** Offset 0x14E3 - PCIE RP post-cursor coefficient list
+/** Offset 0x14CB - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PostCursor5List[29];
-/** Offset 0x1500 - PCIE RP pre-cursor coefficient list
+/** Offset 0x14E8 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PreCursor6List[29];
-/** Offset 0x151D - PCIe post-cursor coefficient list
+/** Offset 0x1505 - PCIe post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PostCursor6List[29];
-/** Offset 0x153A - PCIE RP pre-cursor coefficient list
+/** Offset 0x1522 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PreCursor7List[29];
-/** Offset 0x1557 - PCIE RP post-cursor coefficient list
+/** Offset 0x153F - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PostCursor7List[29];
-/** Offset 0x1574 - PCIE RP pre-cursor coefficient list
+/** Offset 0x155C - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PreCursor8List[29];
-/** Offset 0x1591 - PCIE RP post-cursor coefficient list
+/** Offset 0x1579 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PostCursor8List[29];
-/** Offset 0x15AE - PCIE RP pre-cursor coefficient list
+/** Offset 0x1596 - PCIE RP pre-cursor coefficient list
Provide a list of pre-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PreCursor9List[29];
-/** Offset 0x15CB - PCIE RP post-cursor coefficient list
+/** Offset 0x15B3 - PCIE RP post-cursor coefficient list
Provide a list of post-cursor coefficients to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3PostCursor9List[29];
-/** Offset 0x15E8 - PCIE RP preset list
+/** Offset 0x15D0 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3Preset0List[29];
-/** Offset 0x1605 - PCIe preset list
+/** Offset 0x15ED - PCIe preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3Preset1List[29];
-/** Offset 0x1622 - PCIE RP preset list
+/** Offset 0x160A - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3Preset2List[29];
-/** Offset 0x163F - PCIE RP preset list
+/** Offset 0x1627 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3Preset3List[29];
-/** Offset 0x165C - PCIE RP preset list
+/** Offset 0x1644 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3Preset4List[29];
-/** Offset 0x1679 - PCIE RP preset list
+/** Offset 0x1661 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3Preset5List[29];
-/** Offset 0x1696 - PCIE RP preset list
+/** Offset 0x167E - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3Preset6List[29];
-/** Offset 0x16B3 - PCIE RP preset list
+/** Offset 0x169B - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3Preset7List[29];
-/** Offset 0x16D0 - PCIE RP preset list
+/** Offset 0x16B8 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3Preset8List[29];
-/** Offset 0x16ED - PCIE RP preset list
+/** Offset 0x16D5 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3Preset9List[29];
-/** Offset 0x170A - PCIE RP preset list
+/** Offset 0x16F2 - PCIE RP preset list
Provide a list of presets to be used during phase 3 EQ
**/
UINT8 PcieGen5EqPh3Preset10List[29];
-/** Offset 0x1727 - PCIe EQ phase 1 downstream transmitter port preset
+/** Offset 0x170F - PCIe EQ phase 1 downstream transmitter port preset
Allows to select the downstream port preset value that will be used during phase
1 of equalization
**/
UINT8 PcieGen5EqPh1DpTxPreset[29];
-/** Offset 0x1744 - PCIE RP EQ phase 1 upstream tranmitter port preset
+/** Offset 0x172C - PCIE RP EQ phase 1 upstream tranmitter port preset
Allows to select the upstream port preset value that will be used during phase 1
of equalization
**/
UINT8 PcieGen5EqPh1UpTxPreset[29];
-/** Offset 0x1761 - PCIE RP EQ phase 2 local transmitter override preset
+/** Offset 0x1749 - PCIE RP EQ phase 2 local transmitter override preset
Allows to select the value of the preset used during phase 2 local transmitter override
**/
UINT8 PcieGen5EqPh2LocalTxOverridePreset[29];
-/** Offset 0x177E - Phase3 RP Gen3 EQ enable
+/** Offset 0x1766 - Phase3 RP Gen3 EQ enable
Phase3 Gen3 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
0:Disable, 1:Enable, 2:Auto
**/
UINT8 PcieRpGen3EqPh3Bypass[29];
-/** Offset 0x179B - Phase3 RP Gen3 EQ enable
+/** Offset 0x1783 - Phase3 RP Gen3 EQ enable
Phase3 Gen3 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
0:Disable, 1:Enable, 2:Auto
**/
UINT8 PcieRpGen4EqPh3Bypass[29];
-/** Offset 0x17B8 - Phase3 RP Gen5 EQ enable
+/** Offset 0x17A0 - Phase3 RP Gen5 EQ enable
Phase3 Gen5 EQ enable. Disabled(0x0)(Default): Disable phase 3, Enabled(0x1): Enable phase 3
0:Disable, 1:Enable, 2:Auto
**/
UINT8 PcieRpGen5EqPh3Bypass[29];
-/** Offset 0x17D5 - Phase2-3 RP Gen3 EQ enable
+/** Offset 0x17BD - Phase2-3 RP Gen3 EQ enable
Phase2-3 Gen3 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
Enable Phase2-3
0:Disable, 1:Enable, 2:Auto
**/
UINT8 PcieRpGen3EqPh23Bypass[29];
-/** Offset 0x17F2 - Phase2-3 RP Gen4 EQ enable
+/** Offset 0x17DA - Phase2-3 RP Gen4 EQ enable
Phase2-3 Gen4 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
Enable Phase2-3
0:Disable, 1:Enable, 2:Auto
**/
UINT8 PcieRpGen4EqPh23Bypass[29];
-/** Offset 0x180F - Phase2-3 RP Gen5 EQ enable
+/** Offset 0x17F7 - Phase2-3 RP Gen5 EQ enable
Phase2-3 Gen5 EQ enable. Disabled(0x0)(Default): Disable Phase2-3, Enabled(0x1):
Enable Phase2-3
0:Disable, 1:Enable, 2:Auto
**/
UINT8 PcieRpGen5EqPh23Bypass[29];
-/** Offset 0x182C - RP Gen3 EQ Phase enable
+/** Offset 0x1814 - RP Gen3 EQ Phase enable
Gen3 EQ Phase enable. Disabled(0x0)(Default): Disable Eq Phase, Enabled(0x1): Enable Eq Phase
0:Disable, 1:Enable, 2:Auto
**/
UINT8 PcieRpGen3EqPhBypass[29];
-/** Offset 0x1849 - RP Gen4 EQ Phase enable
+/** Offset 0x1831 - RP Gen4 EQ Phase enable
Gen4 EQ Phase enable. Disabled(0x0)(Default): Disable Eq Phase, Enabled(0x1): Enable Eq Phase
0:Disable, 1:Enable, 2:Auto
**/
UINT8 PcieRpGen4EqPhBypass[29];
-/** Offset 0x1866 - RP Gen5 EQ Phase enable
+/** Offset 0x184E - RP Gen5 EQ Phase enable
Gen5 EQ Phase enable. Disabled(0x0)(Default): Disable Eq Phase, Enabled(0x1): Enable Eq Phase
0:Disable, 1:Enable, 2:Auto
**/
UINT8 PcieRpGen5EqPhBypass[29];
-/** Offset 0x1883 - PCET Timer
+/** Offset 0x186B - PCET Timer
Preset/Coefficient Evaluation Timeout Gen3 PCET Timer. See PCIE_GEN3_PCET. Default
is 0x0(2ms)
**/
UINT8 PcieGen3PcetTimer[29];
-/** Offset 0x18A0 - Gen4 PCET Timer
+/** Offset 0x1888 - Gen4 PCET Timer
Preset/Coefficient Evaluation Timeout - Gen4 PCET Timer. See PCIE_GEN4_PCET. Default
is 0x0(2ms)
**/
UINT8 PcieGen4PcetTimer[29];
-/** Offset 0x18BD - Gen5 PCET Timer
+/** Offset 0x18A5 - Gen5 PCET Timer
Preset/Coefficient Evaluation Timeout - Gen5 PCET Timer. See PCIE_GEN5_PCET. Default
is 0x0(2ms)
**/
UINT8 PcieGen5PcetTimer[29];
-/** Offset 0x18DA - TS Lock Timer for Gen3
+/** Offset 0x18C2 - TS Lock Timer for Gen3
Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen3 TS Lock
Timer. See PCIE_GEN3_TS_LOCK_TIMER. Default is 0x0
**/
UINT8 PcieGen3TsLockTimer[29];
-/** Offset 0x18F7 - PTS Lock Timer for Gen4
+/** Offset 0x18DF - PTS Lock Timer for Gen4
Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen4 TS Lock
Timer. See PCIE_GEN4_TS_LCOK_TIMER. Default is 0x0
**/
UINT8 PcieGen4TsLockTimer[29];
-/** Offset 0x1914 - PTS Lock Timer for Gen5
+/** Offset 0x18FC - PTS Lock Timer for Gen5
Training Sequence Wait Latency For Presets/Coefficients Evaluation - Gen5 TS Lock
Timer. See PCIE_GEN5_TS_LCOK_TIMER. Default is 0x0
**/
UINT8 PcieGen5TsLockTimer[29];
-/** Offset 0x1931 - PCIE Secure Register Lock
+/** Offset 0x1919 - PCIE Secure Register Lock
Describes whether Secure Register Lock is enaled or disabled. When it will be enbaled,
load PcieRpSetSecuredRegisterLock recipe. 0: Disable(Default); 1: Enable
$EN_DIS
**/
UINT8 PcieSetSecuredRegisterLock;
-/** Offset 0x1932 - DG Wait
+/** Offset 0x191A - DG Wait
0(Default) = Disable, 1 = Enable
$EN_DIS
**/
UINT8 DGWait;
-/** Offset 0x1933 - Enable/Disable ASPM Optionality Compliance
+/** Offset 0x191B - Enable/Disable ASPM Optionality Compliance
Enable/Disable ASPM Optionality Compliance.
**/
UINT8 PcieRpTestAspmOc[12];
-/** Offset 0x193F - PCIe Configuration Dump
+/** Offset 0x1927 - PCIe Configuration Dump
Enable/Disable ASPM Optionality Compliance.
0:Disable, 1:Enable
**/
UINT8 PcieCfgDump[12];
-/** Offset 0x194B - PCIE RP Enable Peer Memory Write
+/** Offset 0x1933 - PCIE RP Enable Peer Memory Write
This member describes whether Peer Memory Writes are enabled on the platform.
$EN_DIS
**/
UINT8 PcieEnablePeerMemoryWrite[12];
-/** Offset 0x1957 - PCIE Compliance Test Mode
+/** Offset 0x193F - PCIE Compliance Test Mode
Compliance Test Mode shall be enabled when using Compliance Load Board.
$EN_DIS
**/
UINT8 PcieComplianceTestMode;
-/** Offset 0x1958 - PCIE Rp Function Swap
+/** Offset 0x1940 - PCIE Rp Function Swap
Allows BIOS to use root port function number swapping when root port of function
0 is disabled.
$EN_DIS
**/
UINT8 PcieRpFunctionSwap;
-/** Offset 0x1959 - PCIe Fia Programming
+/** Offset 0x1941 - PCIe Fia Programming
Load Fia configuration if enable. 0: Disable; 1: Enable(Default).
$EN_DIS
**/
UINT8 PcieFiaProgramming;
-/** Offset 0x195A - PCH Pm PME_B0_S5_DIS
+/** Offset 0x1942 - PCH Pm PME_B0_S5_DIS
When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
$EN_DIS
**/
UINT8 PchPmPmeB0S5Dis;
-/** Offset 0x195B - PCIE IMR
+/** Offset 0x1943 - PCIE IMR
Enables Isolated Memory Region for PCIe.
$EN_DIS
**/
UINT8 PcieRpImrEnabled;
-/** Offset 0x195C - PCIE IMR port number
+/** Offset 0x1944 - PCIE IMR port number
Selects PCIE root port number for IMR feature.
**/
UINT8 PcieRpImrSelection;
-/** Offset 0x195D - PCH Pm Wol Enable Override
+/** Offset 0x1945 - PCH Pm Wol Enable Override
Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
$EN_DIS
**/
UINT8 PchPmWolEnableOverride;
-/** Offset 0x195E - PCH Pm WoW lan Enable
+/** Offset 0x1946 - PCH Pm WoW lan Enable
Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
$EN_DIS
**/
UINT8 PchPmWoWlanEnable;
-/** Offset 0x195F - PCH Pm WoW lan DeepSx Enable
+/** Offset 0x1947 - PCH Pm WoW lan DeepSx Enable
Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
PWRM_CFG3 register.
$EN_DIS
**/
UINT8 PchPmWoWlanDeepSxEnable;
-/** Offset 0x1960 - PCH Pm Lan Wake From DeepSx
+/** Offset 0x1948 - PCH Pm Lan Wake From DeepSx
Determine if enable LAN to wake from deep Sx.
$EN_DIS
**/
UINT8 PchPmLanWakeFromDeepSx;
-/** Offset 0x1961 - PCH Pm Deep Sx Pol
+/** Offset 0x1949 - PCH Pm Deep Sx Pol
Deep Sx Policy.
$EN_DIS
**/
UINT8 PchPmDeepSxPol;
-/** Offset 0x1962 - PCH Pm Disable Dsx Ac Present Pulldown
+/** Offset 0x194A - PCH Pm Disable Dsx Ac Present Pulldown
When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
$EN_DIS
**/
UINT8 PchPmDisableDsxAcPresentPulldown;
-/** Offset 0x1963 - PCH Pm Slp S3 Min Assert
+/** Offset 0x194B - PCH Pm Slp S3 Min Assert
SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
**/
UINT8 PchPmSlpS3MinAssert;
-/** Offset 0x1964 - PCH Pm Slp S4 Min Assert
+/** Offset 0x194C - PCH Pm Slp S4 Min Assert
SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
**/
UINT8 PchPmSlpS4MinAssert;
-/** Offset 0x1965 - PCH Pm Slp Sus Min Assert
+/** Offset 0x194D - PCH Pm Slp Sus Min Assert
SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
**/
UINT8 PchPmSlpSusMinAssert;
-/** Offset 0x1966 - PCH Pm Slp A Min Assert
+/** Offset 0x194E - PCH Pm Slp A Min Assert
SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
**/
UINT8 PchPmSlpAMinAssert;
-/** Offset 0x1967 - USB Overcurrent Override for VISA
+/** Offset 0x194F - USB Overcurrent Override for VISA
This option overrides USB Over Current enablement state that USB OC will be disabled
after enabling this option. Enable when VISA pin is muxed with USB OC
$EN_DIS
**/
UINT8 PchEnableDbcObs;
-/** Offset 0x1968 - PCH Pm Slp Strch Sus Up
+/** Offset 0x1950 - PCH Pm Slp Strch Sus Up
Enable SLP_X Stretching After SUS Well Power Up.
$EN_DIS
**/
UINT8 PchPmSlpStrchSusUp;
-/** Offset 0x1969 - PCH Pm Slp Lan Low Dc
+/** Offset 0x1951 - PCH Pm Slp Lan Low Dc
Enable/Disable SLP_LAN# Low on DC Power.
$EN_DIS
**/
UINT8 PchPmSlpLanLowDc;
-/** Offset 0x196A - PCH Pm Pwr Btn Override Period
+/** Offset 0x1952 - PCH Pm Pwr Btn Override Period
PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
**/
UINT8 PchPmPwrBtnOverridePeriod;
-/** Offset 0x196B - PCH Pm Disable Native Power Button
+/** Offset 0x1953 - PCH Pm Disable Native Power Button
Power button native mode disable.
$EN_DIS
**/
UINT8 PchPmDisableNativePowerButton;
-/** Offset 0x196C - PCH Pm ME_WAKE_STS
+/** Offset 0x1954 - PCH Pm ME_WAKE_STS
Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
$EN_DIS
**/
UINT8 PchPmMeWakeSts;
-/** Offset 0x196D - PCH Pm WOL_OVR_WK_STS
+/** Offset 0x1955 - PCH Pm WOL_OVR_WK_STS
Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
$EN_DIS
**/
UINT8 PchPmWolOvrWkSts;
-/** Offset 0x196E - PCH Pm Reset Power Cycle Duration
+/** Offset 0x1956 - PCH Pm Reset Power Cycle Duration
Could be customized in the unit of second. Please refer to EDS for all support settings.
0 is default, 1 is 1 second, 2 is 2 seconds, ...
**/
UINT8 PchPmPwrCycDur;
-/** Offset 0x196F - PCH Pm Pcie Pll Ssc
+/** Offset 0x1957 - PCH Pm Pcie Pll Ssc
Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
BIOS override.
**/
UINT8 PchPmPciePllSsc;
-/** Offset 0x1970 - PCH Legacy IO Low Latency Enable
+/** Offset 0x1958 - PCH Legacy IO Low Latency Enable
Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable
$EN_DIS
**/
UINT8 PchLegacyIoLowLatency;
-/** Offset 0x1971 - PCH Sata Pwr Opt Enable
+/** Offset 0x1959 - PCH Sata Pwr Opt Enable
SATA Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 SataPwrOptEnable;
-/** Offset 0x1972 - PCH Sata eSATA Speed Limit
+/** Offset 0x195A - PCH Sata eSATA Speed Limit
When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
$EN_DIS
**/
UINT8 EsataSpeedLimit;
-/** Offset 0x1973 - PCH Sata Speed Limit
+/** Offset 0x195B - PCH Sata Speed Limit
Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
**/
UINT8 SataSpeedLimit;
-/** Offset 0x1974 - Enable SATA Port HotPlug
+/** Offset 0x195C - Enable SATA Port HotPlug
Enable SATA Port HotPlug.
**/
UINT8 SataPortsHotPlug[8];
-/** Offset 0x197C - Enable SATA Port Interlock Sw
+/** Offset 0x1964 - Enable SATA Port Interlock Sw
Enable SATA Port Interlock Sw.
**/
UINT8 SataPortsInterlockSw[8];
-/** Offset 0x1984 - Enable SATA Port External
+/** Offset 0x196C - Enable SATA Port External
Enable SATA Port External.
**/
UINT8 SataPortsExternal[8];
-/** Offset 0x198C - Enable SATA Port SpinUp
+/** Offset 0x1974 - Enable SATA Port SpinUp
Enable the COMRESET initialization Sequence to the device.
**/
UINT8 SataPortsSpinUp[8];
-/** Offset 0x1994 - Enable SATA Port Solid State Drive
+/** Offset 0x197C - Enable SATA Port Solid State Drive
0: HDD; 1: SSD.
**/
UINT8 SataPortsSolidStateDrive[8];
-/** Offset 0x199C - Enable SATA Port Enable Dito Config
+/** Offset 0x1984 - Enable SATA Port Enable Dito Config
Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
**/
UINT8 SataPortsEnableDitoConfig[8];
-/** Offset 0x19A4 - Enable SATA Port DmVal
+/** Offset 0x198C - Enable SATA Port DmVal
DITO multiplier. Default is 15.
**/
UINT8 SataPortsDmVal[8];
-/** Offset 0x19AC - Pch Dmi Aspm Ctrl
+/** Offset 0x1994 - Pch Dmi Aspm Ctrl
ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
**/
UINT8 PchDmiAspm;
-/** Offset 0x19AD
+/** Offset 0x1995
**/
UINT8 Rsvd300[1];
-/** Offset 0x19AE - Enable SATA Port DmVal
+/** Offset 0x1996 - Enable SATA Port DmVal
DEVSLP Idle Timeout (DITO), Default is 625.
**/
UINT16 SataPortsDitoVal[8];
-/** Offset 0x19BE - Enable SATA Port ZpOdd
+/** Offset 0x19A6 - Enable SATA Port ZpOdd
Support zero power ODD.
**/
UINT8 SataPortsZpOdd[8];
-/** Offset 0x19C6 - PCH Sata Rst Raid Alternate Id
+/** Offset 0x19AE - PCH Sata Rst Raid Alternate Id
Enable RAID Alternate ID.
$EN_DIS
**/
UINT8 SataRstRaidDeviceId;
-/** Offset 0x19C7 - PCH Sata Rst Pcie Storage Remap enable
+/** Offset 0x19AF - PCH Sata Rst Pcie Storage Remap enable
Enable Intel RST for PCIe Storage remapping.
**/
UINT8 SataRstPcieEnable[3];
-/** Offset 0x19CA - PCH Sata Rst Pcie Storage Port
+/** Offset 0x19B2 - PCH Sata Rst Pcie Storage Port
Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
**/
UINT8 SataRstPcieStoragePort[3];
-/** Offset 0x19CD - PCH Sata Rst Pcie Device Reset Delay
+/** Offset 0x19B5 - PCH Sata Rst Pcie Device Reset Delay
PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
**/
UINT8 SataRstPcieDeviceResetDelay[3];
-/** Offset 0x19D0 - UFS enable/disable
+/** Offset 0x19B8 - UFS enable/disable
Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller
0 and (0,1) to enable controller 1
$EN_DIS
**/
UINT8 UfsEnable[2];
-/** Offset 0x19D2 - UFS Inline Encryption enable/disable
+/** Offset 0x19BA - UFS Inline Encryption enable/disable
Enable/Disable UFS Inline Encryption feature, One byte for each Controller - (1,0)
to enable Inline Encryption for controller 0 and (0,1) to enable Inline Encryption
for controller 1
@@ -2956,277 +2947,277 @@ typedef struct {
**/
UINT8 UfsInlineEncryption[2];
-/** Offset 0x19D4 - IEH Mode
+/** Offset 0x19BC - IEH Mode
Integrated Error Handler Mode, 0: Bypass, 1: Enable
0: Bypass, 1:Enable
**/
UINT8 IehMode;
-/** Offset 0x19D5 - SOC Thermal Throttling Suggested Setting
+/** Offset 0x19BD - SOC Thermal Throttling Suggested Setting
Thermal Throttling Suggested Setting. When it is enabled, customized throttle levels
are ignored but with native settings.
$EN_DIS
**/
UINT8 SocTTSuggestedSetting;
-/** Offset 0x19D6 - SOC Thermal Throttling Custimized T0Level Value
+/** Offset 0x19BE - SOC Thermal Throttling Custimized T0Level Value
Custimized T0Level value.
**/
UINT16 SocT0Level;
-/** Offset 0x19D8 - SOC Thermal Throttling Custimized T1Level Value
+/** Offset 0x19C0 - SOC Thermal Throttling Custimized T1Level Value
Custimized T1Level value.
**/
UINT16 SocT1Level;
-/** Offset 0x19DA - SOC Thermal Throttling Custimized T2Level Value
+/** Offset 0x19C2 - SOC Thermal Throttling Custimized T2Level Value
Custimized T2Level value.
**/
UINT16 SocT2Level;
-/** Offset 0x19DC - Enable SOC Thermal Throttle
+/** Offset 0x19C4 - Enable SOC Thermal Throttle
Enable thermal throttle function.
$EN_DIS
**/
UINT8 SocTTEnable;
-/** Offset 0x19DD - SOC PMSync State 13
+/** Offset 0x19C5 - SOC PMSync State 13
When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
at least T2 state.
$EN_DIS
**/
UINT8 SocTTState13Enable;
-/** Offset 0x19DE - SOC Thermal Throttle Lock
+/** Offset 0x19C6 - SOC Thermal Throttle Lock
Thermal Throttle Lock.
$EN_DIS
**/
UINT8 SocTTLock;
-/** Offset 0x19DF - PCH Thermal Throttling Suggested Setting
+/** Offset 0x19C7 - PCH Thermal Throttling Suggested Setting
Thermal Throttling Suggested Setting. When it is enabled, customized throttle levels
are ignored but with native settings.
$EN_DIS
**/
UINT8 PchTTSuggestedSetting;
-/** Offset 0x19E0 - PCH Thermal Throttling Custimized T0Level Value
+/** Offset 0x19C8 - PCH Thermal Throttling Custimized T0Level Value
Custimized T0Level value.
**/
UINT16 PchT0Level;
-/** Offset 0x19E2 - PCH Thermal Throttling Custimized T1Level Value
+/** Offset 0x19CA - PCH Thermal Throttling Custimized T1Level Value
Custimized T1Level value.
**/
UINT16 PchT1Level;
-/** Offset 0x19E4 - PCH Thermal Throttling Custimized T2Level Value
+/** Offset 0x19CC - PCH Thermal Throttling Custimized T2Level Value
Custimized T2Level value.
**/
UINT16 PchT2Level;
-/** Offset 0x19E6 - Enable PCH Thermal Throttle
+/** Offset 0x19CE - Enable PCH Thermal Throttle
Enable thermal throttle function.
$EN_DIS
**/
UINT8 PchTTEnable;
-/** Offset 0x19E7 - PCH PMSync State 13
+/** Offset 0x19CF - PCH PMSync State 13
When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
at least T2 state.
$EN_DIS
**/
UINT8 PchTTState13Enable;
-/** Offset 0x19E8 - PCH Thermal Throttle Lock
+/** Offset 0x19D0 - PCH Thermal Throttle Lock
Thermal Throttle Lock.
$EN_DIS
**/
UINT8 PchTTLock;
-/** Offset 0x19E9 - IOE Thermal Throttling Suggested Setting
+/** Offset 0x19D1 - IOE Thermal Throttling Suggested Setting
IOE Thermal Throttling Suggested Setting. When it is enabled, customized throttle
levels are ignored but with native settings.
$EN_DIS
**/
UINT8 IoeTTSuggestedSetting;
-/** Offset 0x19EA - IOE Thermal Throttling Custimized T0Level Value
+/** Offset 0x19D2 - IOE Thermal Throttling Custimized T0Level Value
Custimized IOE T0Level value.
**/
UINT16 IoeT0Level;
-/** Offset 0x19EC - IOE Thermal Throttling Custimized T1Level Value
+/** Offset 0x19D4 - IOE Thermal Throttling Custimized T1Level Value
Custimized IOE T1Level value.
**/
UINT16 IoeT1Level;
-/** Offset 0x19EE - IOE Thermal Throttling Custimized T2Level Value
+/** Offset 0x19D6 - IOE Thermal Throttling Custimized T2Level Value
Custimized IOE T2Level value.
**/
UINT16 IoeT2Level;
-/** Offset 0x19F0 - Enable IOE Thermal Throttle
+/** Offset 0x19D8 - Enable IOE Thermal Throttle
Enable thermal throttle function.
$EN_DIS
**/
UINT8 IoeTTEnable;
-/** Offset 0x19F1 - IOE Thermal Throttle Lock
+/** Offset 0x19D9 - IOE Thermal Throttle Lock
Thermal Throttle Lock.
$EN_DIS
**/
UINT8 IoeTTLock;
-/** Offset 0x19F2 - DMI Thermal Sensor Autonomous Width Enable
+/** Offset 0x19DA - DMI Thermal Sensor Autonomous Width Enable
DMI Thermal Sensor Autonomous Width Enable.
$EN_DIS
**/
UINT8 PchDmiTsawEn;
-/** Offset 0x19F3 - DMI Thermal Sensor Suggested Setting
+/** Offset 0x19DB - DMI Thermal Sensor Suggested Setting
DMT thermal sensor suggested representative values.
$EN_DIS
**/
UINT8 DmiSuggestedSetting;
-/** Offset 0x19F4 - Thermal Sensor 0 Target Width
+/** Offset 0x19DC - Thermal Sensor 0 Target Width
Thermal Sensor 0 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS0TW;
-/** Offset 0x19F5 - Thermal Sensor 1 Target Width
+/** Offset 0x19DD - Thermal Sensor 1 Target Width
Thermal Sensor 1 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS1TW;
-/** Offset 0x19F6 - Thermal Sensor 2 Target Width
+/** Offset 0x19DE - Thermal Sensor 2 Target Width
Thermal Sensor 2 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS2TW;
-/** Offset 0x19F7 - Thermal Sensor 3 Target Width
+/** Offset 0x19DF - Thermal Sensor 3 Target Width
Thermal Sensor 3 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS3TW;
-/** Offset 0x19F8 - Port 0 T1 Multipler
+/** Offset 0x19E0 - Port 0 T1 Multipler
Port 0 T1 Multipler.
**/
UINT8 SataP0T1M;
-/** Offset 0x19F9 - Port 0 T2 Multipler
+/** Offset 0x19E1 - Port 0 T2 Multipler
Port 0 T2 Multipler.
**/
UINT8 SataP0T2M;
-/** Offset 0x19FA - Port 0 T3 Multipler
+/** Offset 0x19E2 - Port 0 T3 Multipler
Port 0 T3 Multipler.
**/
UINT8 SataP0T3M;
-/** Offset 0x19FB - Port 0 Tdispatch
+/** Offset 0x19E3 - Port 0 Tdispatch
Port 0 Tdispatch.
**/
UINT8 SataP0TDisp;
-/** Offset 0x19FC - Port 1 T1 Multipler
+/** Offset 0x19E4 - Port 1 T1 Multipler
Port 1 T1 Multipler.
**/
UINT8 SataP1T1M;
-/** Offset 0x19FD - Port 1 T2 Multipler
+/** Offset 0x19E5 - Port 1 T2 Multipler
Port 1 T2 Multipler.
**/
UINT8 SataP1T2M;
-/** Offset 0x19FE - Port 1 T3 Multipler
+/** Offset 0x19E6 - Port 1 T3 Multipler
Port 1 T3 Multipler.
**/
UINT8 SataP1T3M;
-/** Offset 0x19FF - Port 1 Tdispatch
+/** Offset 0x19E7 - Port 1 Tdispatch
Port 1 Tdispatch.
**/
UINT8 SataP1TDisp;
-/** Offset 0x1A00 - Port 0 Tinactive
+/** Offset 0x19E8 - Port 0 Tinactive
Port 0 Tinactive.
**/
UINT8 SataP0Tinact;
-/** Offset 0x1A01 - Port 0 Alternate Fast Init Tdispatch
+/** Offset 0x19E9 - Port 0 Alternate Fast Init Tdispatch
Port 0 Alternate Fast Init Tdispatch.
$EN_DIS
**/
UINT8 SataP0TDispFinit;
-/** Offset 0x1A02 - Port 1 Tinactive
+/** Offset 0x19EA - Port 1 Tinactive
Port 1 Tinactive.
**/
UINT8 SataP1Tinact;
-/** Offset 0x1A03 - Port 1 Alternate Fast Init Tdispatch
+/** Offset 0x19EB - Port 1 Alternate Fast Init Tdispatch
Port 1 Alternate Fast Init Tdispatch.
$EN_DIS
**/
UINT8 SataP1TDispFinit;
-/** Offset 0x1A04 - Sata Thermal Throttling Suggested Setting
+/** Offset 0x19EC - Sata Thermal Throttling Suggested Setting
Sata Thermal Throttling Suggested Setting.
$EN_DIS
**/
UINT8 SataThermalSuggestedSetting;
-/** Offset 0x1A05
+/** Offset 0x19ED
**/
UINT8 Rsvd310;
-/** Offset 0x1A06 - Thermal Device Temperature
+/** Offset 0x19EE - Thermal Device Temperature
Decides the temperature.
**/
UINT16 PchTemperatureHotLevel;
-/** Offset 0x1A08 - USB2 Port Over Current Pin
+/** Offset 0x19F0 - USB2 Port Over Current Pin
Describe the specific over current pin number of USB 2.0 Port N.
**/
UINT8 Usb2OverCurrentPin[16];
-/** Offset 0x1A18 - USB3 Port Over Current Pin
+/** Offset 0x1A00 - USB3 Port Over Current Pin
Describe the specific over current pin number of USB 3.0 Port N.
**/
UINT8 Usb3OverCurrentPin[10];
-/** Offset 0x1A22 - Enable xHCI LTR override
+/** Offset 0x1A0A - Enable xHCI LTR override
Enables override of recommended LTR values for xHCI
$EN_DIS
**/
UINT8 PchUsbLtrOverrideEnable;
-/** Offset 0x1A23
+/** Offset 0x1A0B
**/
UINT8 Rsvd320[1];
-/** Offset 0x1A24 - xHCI High Idle Time LTR override
+/** Offset 0x1A0C - xHCI High Idle Time LTR override
Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
**/
UINT32 PchUsbLtrHighIdleTimeOverride;
-/** Offset 0x1A28 - xHCI Medium Idle Time LTR override
+/** Offset 0x1A10 - xHCI Medium Idle Time LTR override
Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
**/
UINT32 PchUsbLtrMediumIdleTimeOverride;
-/** Offset 0x1A2C - xHCI Low Idle Time LTR override
+/** Offset 0x1A14 - xHCI Low Idle Time LTR override
Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
**/
UINT32 PchUsbLtrLowIdleTimeOverride;
-/** Offset 0x1A30 - Enable 8254 Static Clock Gating
+/** Offset 0x1A18 - Enable 8254 Static Clock Gating
Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
legacy OS using 8254 timer. Also enable this while S0ix is enabled.
@@ -3234,7 +3225,7 @@ typedef struct {
**/
UINT8 Enable8254ClockGating;
-/** Offset 0x1A31 - Enable 8254 Static Clock Gating On S3
+/** Offset 0x1A19 - Enable 8254 Static Clock Gating On S3
This is only applicable when Enable8254ClockGating is disabled. FSP will do the
8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
avoids the SMI requirement for the programming.
@@ -3242,7 +3233,7 @@ typedef struct {
**/
UINT8 Enable8254ClockGatingOnS3;
-/** Offset 0x1A32 - Enable TCO timer.
+/** Offset 0x1A1A - Enable TCO timer.
When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
emulation must be enabled, and WDAT table must not be exposed to the OS.
@@ -3250,135 +3241,135 @@ typedef struct {
**/
UINT8 EnableTcoTimer;
-/** Offset 0x1A33 - Enable Timed GPIO 0.
+/** Offset 0x1A1B - Enable Timed GPIO 0.
When FALSE, it disables Timed GPIO 0.
$EN_DIS
**/
UINT8 EnableTimedGpio0;
-/** Offset 0x1A34 - Enable Timed GPIO 1.
+/** Offset 0x1A1C - Enable Timed GPIO 1.
When FALSE, it disables Timed GPIO 1.
$EN_DIS
**/
UINT8 EnableTimedGpio1;
-/** Offset 0x1A35
+/** Offset 0x1A1D
**/
UINT8 EmbReserved3FspsUpd[2];
-/** Offset 0x1A37
+/** Offset 0x1A1F
**/
UINT8 Rsvd330[5];
-/** Offset 0x1A3C
+/** Offset 0x1A24
**/
UINT8 UnusedUpdSpace2[4];
-/** Offset 0x1A40 - BgpdtHash[4]
+/** Offset 0x1A28 - BgpdtHash[4]
BgpdtHash values
**/
UINT64 BgpdtHash[4];
-/** Offset 0x1A60 - BiosGuardAttr
+/** Offset 0x1A48 - BiosGuardAttr
BiosGuardAttr default values
**/
UINT32 BiosGuardAttr;
-/** Offset 0x1A64
+/** Offset 0x1A4C
**/
UINT8 Rsvd340[4];
-/** Offset 0x1A68 - BiosGuardModulePtr
+/** Offset 0x1A50 - BiosGuardModulePtr
BiosGuardModulePtr default values
**/
UINT64 BiosGuardModulePtr;
-/** Offset 0x1A70 - SendEcCmd
+/** Offset 0x1A58 - SendEcCmd
SendEcCmd function pointer. \n
@code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
**/
UINT64 SendEcCmd;
-/** Offset 0x1A78 - EcCmdProvisionEav
+/** Offset 0x1A60 - EcCmdProvisionEav
Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
**/
UINT8 EcCmdProvisionEav;
-/** Offset 0x1A79 - EcCmdLock
+/** Offset 0x1A61 - EcCmdLock
EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
**/
UINT8 EcCmdLock;
-/** Offset 0x1A7A
+/** Offset 0x1A62
**/
UINT8 Rsvd350[6];
-/** Offset 0x1A80 - EcProvisionEav
+/** Offset 0x1A68 - EcProvisionEav
EcProvisionEav function pointer. \n
@code typedef EFI_STATUS (EFIAPI *EC_PROVISION_EAV) (IN UINT32 Eav, OUT UINT8
*ReturnValue); @endcode
**/
UINT64 EcProvisionEav;
-/** Offset 0x1A88 - EcBiosGuardCmdLock
+/** Offset 0x1A70 - EcBiosGuardCmdLock
EcBiosGuardCmdLock function pointer. \n
@code typedef EFI_STATUS (EFIAPI *EC_CMD_LOCK) (OUT UINT8 *ReturnValue); @endcode
**/
UINT64 EcBiosGuardCmdLock;
-/** Offset 0x1A90 - Skip Ssid Programming.
+/** Offset 0x1A78 - Skip Ssid Programming.
When set to TRUE, silicon code will not do any SSID programming and platform code
needs to handle that by itself properly.
$EN_DIS
**/
UINT8 SiSkipSsidProgramming;
-/** Offset 0x1A91
+/** Offset 0x1A79
**/
UINT8 Rsvd360;
-/** Offset 0x1A92 - Change Default SVID
+/** Offset 0x1A7A - Change Default SVID
Change the default SVID used in FSP to programming internal devices. This is only
valid when SkipSsidProgramming is FALSE.
**/
UINT16 SiCustomizedSvid;
-/** Offset 0x1A94 - Change Default SSID
+/** Offset 0x1A7C - Change Default SSID
Change the default SSID used in FSP to programming internal devices. This is only
valid when SkipSsidProgramming is FALSE.
**/
UINT16 SiCustomizedSsid;
-/** Offset 0x1A96
+/** Offset 0x1A7E
**/
UINT8 Rsvd370[2];
-/** Offset 0x1A98 - SVID SDID table Poniter.
+/** Offset 0x1A80 - SVID SDID table Poniter.
The address of the table of SVID SDID to customize each SVID SDID entry. This is
only valid when SkipSsidProgramming is FALSE.
**/
UINT32 SiSsidTablePtr;
-/** Offset 0x1A9C - Number of ssid table.
+/** Offset 0x1A84 - Number of ssid table.
SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
This is only valid when SkipSsidProgramming is FALSE.
**/
UINT16 SiNumberOfSsidTableEntry;
-/** Offset 0x1A9E - USB2 Port Reset Message Enable
+/** Offset 0x1A86 - USB2 Port Reset Message Enable
0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must
be enable for USB2 Port those are paired with CPU XHCI Port
**/
UINT8 PortResetMessageEnable[16];
-/** Offset 0x1AAE - SATA RST Interrupt Mode
+/** Offset 0x1A96 - SATA RST Interrupt Mode
Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
0:Msix, 1:Msi, 2:Legacy
**/
UINT8 SataRstInterrupt;
-/** Offset 0x1AAF - Enable PS_ON.
+/** Offset 0x1A97 - Enable PS_ON.
PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
target that will be required by the California Energy Commission (CEC). When FALSE,
PS_ON is to be disabled.
@@ -3386,184 +3377,184 @@ typedef struct {
**/
UINT8 PsOnEnable;
-/** Offset 0x1AB0 - Pmc Cpu C10 Gate Pin Enable
+/** Offset 0x1A98 - Pmc Cpu C10 Gate Pin Enable
Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
and VccSTG rails instead of SLP_S0# pin.
$EN_DIS
**/
UINT8 PmcCpuC10GatePinEnable;
-/** Offset 0x1AB1 - Pch Dmi Aspm Ctrl
+/** Offset 0x1A99 - Pch Dmi Aspm Ctrl
ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
**/
UINT8 PchDmiAspmCtrl;
-/** Offset 0x1AB2 - PchDmiCwbEnable
+/** Offset 0x1A9A - PchDmiCwbEnable
Central Write Buffer feature configurable and enabled by default
$EN_DIS
**/
UINT8 PchDmiCwbEnable;
-/** Offset 0x1AB3 - OS IDLE Mode Enable
+/** Offset 0x1A9B - OS IDLE Mode Enable
Enable/Disable OS Idle Mode
$EN_DIS
**/
UINT8 PmcOsIdleEnable;
-/** Offset 0x1AB4 - S0ix Auto-Demotion
+/** Offset 0x1A9C - S0ix Auto-Demotion
Enable/Disable the Low Power Mode Auto-Demotion Host Control feature.
$EN_DIS
**/
UINT8 PchS0ixAutoDemotion;
-/** Offset 0x1AB5 - Latch Events C10 Exit
+/** Offset 0x1A9D - Latch Events C10 Exit
When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are
captured on C10 exit (instead of C10 entry which is default)
$EN_DIS
**/
UINT8 PchPmLatchEventsC10Exit;
-/** Offset 0x1AB6 - PMC ADR enable
+/** Offset 0x1A9E - PMC ADR enable
Enable/disable asynchronous DRAM refresh
$EN_DIS
**/
UINT8 PmcAdrEn;
-/** Offset 0x1AB7 - PMC ADR timer configuration enable
+/** Offset 0x1A9F - PMC ADR timer configuration enable
Enable/disable ADR timer configuration
$EN_DIS
**/
UINT8 PmcAdrTimerEn;
-/** Offset 0x1AB8 - PMC ADR phase 1 timer value
+/** Offset 0x1AA0 - PMC ADR phase 1 timer value
Enable/disable ADR timer configuration
**/
UINT8 PmcAdrTimer1Val;
-/** Offset 0x1AB9 - PMC ADR phase 1 timer multiplier value
+/** Offset 0x1AA1 - PMC ADR phase 1 timer multiplier value
Specify the multiplier value for phase 1 ADR timer
**/
UINT8 PmcAdrMultiplier1Val;
-/** Offset 0x1ABA - PMC ADR host reset partition enable
+/** Offset 0x1AA2 - PMC ADR host reset partition enable
Specify whether PMC should set ADR_RST_STS bit after receiving Reset_Warn_Ack DMI message
$EN_DIS
**/
UINT8 PmcAdrHostPartitionReset;
-/** Offset 0x1ABB - PMC ADR source select override enable
+/** Offset 0x1AA3 - PMC ADR source select override enable
Tells the FSP to update the source select with platform value
$EN_DIS
**/
UINT8 PmcAdrSrcOverride;
-/** Offset 0x1ABC - PMC ADR source selection
+/** Offset 0x1AA4 - PMC ADR source selection
Specify which sources should cause ADR flow
**/
UINT32 PmcAdrSrcSel;
-/** Offset 0x1AC0 - PMC WDT enable
+/** Offset 0x1AA8 - PMC WDT enable
Enable/disable PMC WDT configuration
$EN_DIS
**/
UINT8 PmcWdtTimerEn;
-/** Offset 0x1AC1 - PCIe RootPort Clock Gating
+/** Offset 0x1AA9 - PCIe RootPort Clock Gating
Describes whether the PCI Express Clock Gating for each root port is enabled by
platform modules. 0: Disable; 1: Enable(Default).
$EN_DIS
**/
UINT8 PcieClockGating[29];
-/** Offset 0x1ADE - PCIe RootPort Power Gating
+/** Offset 0x1AC6 - PCIe RootPort Power Gating
Describes whether the PCI Express Power Gating for each root port is enabled by
platform modules. 0: Disable; 1: Enable(Default).
$EN_DIS
**/
UINT8 PciePowerGating[29];
-/** Offset 0x1AFB - FOMS Control Policy
+/** Offset 0x1AE3 - FOMS Control Policy
Choose the Foms Control Policy, <b>Default = 0 </b>
0: Auto, 1: Gen3 Foms, 2: Gen4 Foms, 3: Gen3 and Gen4 Foms
**/
UINT8 PcieFomsCp[29];
-/** Offset 0x1B18 - PCIe GPIO Assertion in Link Down
+/** Offset 0x1B00 - PCIe GPIO Assertion in Link Down
Describes whether the PCIe GPIO Assertion in Link Down programming is enabled for
each root portby platform modules. 0: Disable; 1: Enable(Default).
$EN_DIS
**/
UINT8 LinkDownGpios[29];
-/** Offset 0x1B35 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
+/** Offset 0x1B1D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate3UniqTranEnable[10];
-/** Offset 0x1B3F - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
+/** Offset 0x1B27 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
= 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate3UniqTran[10];
-/** Offset 0x1B49 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
+/** Offset 0x1B31 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate2UniqTranEnable[10];
-/** Offset 0x1B53 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
+/** Offset 0x1B3B - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate2UniqTran[10];
-/** Offset 0x1B5D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
+/** Offset 0x1B45 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate1UniqTranEnable[10];
-/** Offset 0x1B67 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
+/** Offset 0x1B4F - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate1UniqTran[10];
-/** Offset 0x1B71 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
+/** Offset 0x1B59 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate0UniqTranEnable[10];
-/** Offset 0x1B7B - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
+/** Offset 0x1B63 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate0UniqTran[10];
-/** Offset 0x1B85 - Skip PAM regsiter lock
+/** Offset 0x1B6D - Skip PAM regsiter lock
Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
PAM registers will be locked by RC
$EN_DIS
**/
UINT8 SkipPamLock;
-/** Offset 0x1B86 - Enable/Disable IGFX RenderStandby
+/** Offset 0x1B6E - Enable/Disable IGFX RenderStandby
Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
$EN_DIS
**/
UINT8 RenderStandby;
-/** Offset 0x1B87 - Enable/Disable GT Configuration
+/** Offset 0x1B6F - Enable/Disable GT Configuration
Enable(Default): Configure GT for use, Disable: Skip GT Configuration
$EN_DIS
**/
UINT8 ConfigureGT;
-/** Offset 0x1B88 - GT Frequency Limit
+/** Offset 0x1B70 - GT Frequency Limit
0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
@@ -3577,104 +3568,104 @@ typedef struct {
**/
UINT8 GtFreqMax;
-/** Offset 0x1B89 - Disable Turbo GT
+/** Offset 0x1B71 - Disable Turbo GT
0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
$EN_DIS
**/
UINT8 DisableTurboGt;
-/** Offset 0x1B8A - Enable RC1p GT frequency request to PMA (provided all other conditions are met)
+/** Offset 0x1B72 - Enable RC1p GT frequency request to PMA (provided all other conditions are met)
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 RC1pGtFreqEnable;
-/** Offset 0x1B8B - Enable RC1p Media frequency request to PMA (provided all other conditions are met)
+/** Offset 0x1B73 - Enable RC1p Media frequency request to PMA (provided all other conditions are met)
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 RC1pMediaFreqEnable;
-/** Offset 0x1B8C - Enable TSN Multi-VC
+/** Offset 0x1B74 - Enable TSN Multi-VC
Enable/disable Multi Virtual Channels(VC) in TSN.
$EN_DIS
**/
UINT8 PchTsnMultiVcEnable;
-/** Offset 0x1B8D - PMC Limit Powergating
+/** Offset 0x1B75 - PMC Limit Powergating
Enable/disable Limit PSF powergating to C3 and deeper states
$EN_DIS
**/
UINT8 PmcLimitC3AndDeeperWA;
-/** Offset 0x1B8E
+/** Offset 0x1B76
**/
UINT8 Rsvd380[10];
-/** Offset 0x1B98 - LogoPixelHeight Address
+/** Offset 0x1B80 - LogoPixelHeight Address
Address of LogoPixelHeight
**/
UINT32 LogoPixelHeight;
-/** Offset 0x1B9C - LogoPixelWidth Address
+/** Offset 0x1B84 - LogoPixelWidth Address
Address of LogoPixelWidth
**/
UINT32 LogoPixelWidth;
-/** Offset 0x1BA0 - Enable/Disable Media Configuration
+/** Offset 0x1B88 - Enable/Disable Media Configuration
Enable(Default): Configure Media for use, Disable: Skip Media Configuration
$EN_DIS
**/
UINT8 ConfigureMedia;
-/** Offset 0x1BA1 - ITbt Usb4CmMode value
+/** Offset 0x1B89 - ITbt Usb4CmMode value
ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM
**/
UINT8 Usb4CmMode;
-/** Offset 0x1BA2
+/** Offset 0x1B8A
**/
UINT8 Rsvd390[2];
-/** Offset 0x1BA4 - HorizontalResolution for PEI Logo
+/** Offset 0x1B8C - HorizontalResolution for PEI Logo
HorizontalResolution from PEIm Gfx for PEI Logo
**/
UINT32 HorizontalResolution;
-/** Offset 0x1BA8 - VerticalResolution for PEI Logo
+/** Offset 0x1B90 - VerticalResolution for PEI Logo
VerticalResolution from PEIm Gfx for PEI Logo
**/
UINT32 VerticalResolution;
-/** Offset 0x1BAC - Enable/Disable IGFX Media Standby
+/** Offset 0x1B94 - Enable/Disable IGFX Media Standby
Enable(Default): Enable IGFX Media Standby, Disable: Disable IGFX MediaStandby
$EN_DIS
**/
UINT8 MediaStandby;
-/** Offset 0x1BAD - SaPostMemTestRsvd
+/** Offset 0x1B95 - SaPostMemTestRsvd
Reserved for SA Post-Mem Test
$EN_DIS
**/
UINT8 SaPostMemTestRsvd[32];
-/** Offset 0x1BCD
+/** Offset 0x1BB5
**/
UINT8 SaFspsUpdRsvd[32];
-/** Offset 0x1BED - RSR feature
+/** Offset 0x1BD5 - RSR feature
Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
$EN_DIS
**/
UINT8 EnableRsr;
-/** Offset 0x1BEE - ReservedCpuPostMem1
+/** Offset 0x1BD6 - ReservedCpuPostMem1
Reserved for CPU Post-Mem 1
$EN_DIS
**/
UINT8 ReservedCpuPostMem1[4];
-/** Offset 0x1BF2 - Enable or Disable HWP
+/** Offset 0x1BDA - Enable or Disable HWP
Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the
CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; <b>1:
Enable;</b>
@@ -3682,7 +3673,7 @@ typedef struct {
**/
UINT8 Hwp;
-/** Offset 0x1BF3 - Package Long duration turbo mode time
+/** Offset 0x1BDB - Package Long duration turbo mode time
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained. Valid values(Unit
@@ -3691,14 +3682,14 @@ typedef struct {
**/
UINT8 PowerLimit1Time;
-/** Offset 0x1BF4 - Short Duration Turbo Mode
+/** Offset 0x1BDC - Short Duration Turbo Mode
Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program
the default values for Power Limit 2. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PowerLimit2;
-/** Offset 0x1BF5 - Turbo settings Lock
+/** Offset 0x1BDD - Turbo settings Lock
Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT
MSR will be locked and a reset will be required to unlock the register. <b>0: Disable;
</b> 1: Enable
@@ -3706,7 +3697,7 @@ typedef struct {
**/
UINT8 TurboPowerLimitLock;
-/** Offset 0x1BF6 - Package PL3 time window
+/** Offset 0x1BDE - Package PL3 time window
Power Limit 3 Time Window value in Milli seconds. Indicates the time window over
which Power Limit 3 value should be maintained. If the value is 0, BIOS leaves
the hardware default value. Valid value: <b>0</b>, 3-8, 10, 12, 14, 16, 20, 24,
@@ -3714,111 +3705,111 @@ typedef struct {
**/
UINT8 PowerLimit3Time;
-/** Offset 0x1BF7 - Package PL3 Duty Cycle
+/** Offset 0x1BDF - Package PL3 Duty Cycle
Specify the duty cycle in percentage that the CPU is required to maintain over the
configured time window. Range is 0-100.
**/
UINT8 PowerLimit3DutyCycle;
-/** Offset 0x1BF8 - Package PL3 Lock
+/** Offset 0x1BE0 - Package PL3 Lock
Power Limit 3 Lock. When enabled PL3 configurations are locked during OS. When disabled
PL3 configuration can be changed during OS. <b>0: Disable</b> ; 1:Enable
$EN_DIS
**/
UINT8 PowerLimit3Lock;
-/** Offset 0x1BF9 - Package PL4 Lock
+/** Offset 0x1BE1 - Package PL4 Lock
Power Limit 4 Lock. When enabled PL4 configurations are locked during OS. When disabled
PL4 configuration can be changed during OS. <b>0: Disable</b> ; 1:Enable
$EN_DIS
**/
UINT8 PowerLimit4Lock;
-/** Offset 0x1BFA - TCC Activation Offset
+/** Offset 0x1BE2 - TCC Activation Offset
TCC Activation Offset. Offset from factory set TCC activation temperature at which
the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
Temperature, in volts. <b>Default = 0h</b>.
**/
UINT8 TccActivationOffset;
-/** Offset 0x1BFB - Tcc Offset Clamp Enable/Disable
+/** Offset 0x1BE3 - Tcc Offset Clamp Enable/Disable
Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
below P1. <b>0: Disabled</b>; 1: Enabled.
$EN_DIS
**/
UINT8 TccOffsetClamp;
-/** Offset 0x1BFC - Tcc Offset Lock
+/** Offset 0x1BE4 - Tcc Offset Lock
Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
target; <b>0: Disabled</b>; 1: Enabled.
$EN_DIS
**/
UINT8 TccOffsetLock;
-/** Offset 0x1BFD - Custom Ratio State Entries
+/** Offset 0x1BE5 - Custom Ratio State Entries
The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
ratio table. Sets the number of custom P-states. At least 2 states must be present
**/
UINT8 NumberOfEntries;
-/** Offset 0x1BFE - Custom Short term Power Limit time window
+/** Offset 0x1BE6 - Custom Short term Power Limit time window
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained.
**/
UINT8 Custom1PowerLimit1Time;
-/** Offset 0x1BFF - Custom Turbo Activation Ratio
+/** Offset 0x1BE7 - Custom Turbo Activation Ratio
Custom value for Turbo Activation Ratio. Needs to be configured with valid values
from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255
**/
UINT8 Custom1TurboActivationRatio;
-/** Offset 0x1C00 - Custom Config Tdp Control
+/** Offset 0x1BE8 - Custom Config Tdp Control
Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level
1. Valid Range is 0 to 2
**/
UINT8 Custom1ConfigTdpControl;
-/** Offset 0x1C01 - Custom Short term Power Limit time window
+/** Offset 0x1BE9 - Custom Short term Power Limit time window
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained.
**/
UINT8 Custom2PowerLimit1Time;
-/** Offset 0x1C02 - Custom Turbo Activation Ratio
+/** Offset 0x1BEA - Custom Turbo Activation Ratio
Custom value for Turbo Activation Ratio. Needs to be configured with valid values
from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255
**/
UINT8 Custom2TurboActivationRatio;
-/** Offset 0x1C03 - Custom Config Tdp Control
+/** Offset 0x1BEB - Custom Config Tdp Control
Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level
1. Valid Range is 0 to 2
**/
UINT8 Custom2ConfigTdpControl;
-/** Offset 0x1C04 - Custom Short term Power Limit time window
+/** Offset 0x1BEC - Custom Short term Power Limit time window
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained.
**/
UINT8 Custom3PowerLimit1Time;
-/** Offset 0x1C05 - Custom Turbo Activation Ratio
+/** Offset 0x1BED - Custom Turbo Activation Ratio
Custom value for Turbo Activation Ratio. Needs to be configured with valid values
from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255
**/
UINT8 Custom3TurboActivationRatio;
-/** Offset 0x1C06 - Custom Config Tdp Control
+/** Offset 0x1BEE - Custom Config Tdp Control
Config Tdp(Base Power) Control (0/1/2) value for custom cTDP(Assured Power) level
1. Valid Range is 0 to 2
**/
UINT8 Custom3ConfigTdpControl;
-/** Offset 0x1C07 - ConfigTdp mode settings Lock
+/** Offset 0x1BEF - ConfigTdp mode settings Lock
cTDP(Assured Power) Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO and CONFIG_TDP_CONTROL.
Note: When CTDP(Assured Power) Lock is enabled Custom ConfigTDP Count will be forced
to 1 and Custom ConfigTDP Boot Index will be forced to 0. <b>0: Disable</b>; 1: Enable
@@ -3826,14 +3817,14 @@ typedef struct {
**/
UINT8 ConfigTdpLock;
-/** Offset 0x1C08 - Load Configurable TDP SSDT
+/** Offset 0x1BF0 - Load Configurable TDP SSDT
Enables cTDP(Assured Power) control via runtime ACPI BIOS methods. This 'BIOS only'
feature does not require EC or driver support. <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ConfigTdpBios;
-/** Offset 0x1C09 - PL1 Enable value
+/** Offset 0x1BF1 - PL1 Enable value
Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it
activates the PL1 value to be used by the processor to limit the average power
of given time window. <b>0: Disable</b>; 1: Enable.
@@ -3841,7 +3832,7 @@ typedef struct {
**/
UINT8 PsysPowerLimit1;
-/** Offset 0x1C0A - PL1 timewindow
+/** Offset 0x1BF2 - PL1 timewindow
Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to
128. 0 = default values. Indicates the time window over which Platform Processor
Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to
@@ -3849,7 +3840,7 @@ typedef struct {
**/
UINT8 PsysPowerLimit1Time;
-/** Offset 0x1C0B - PL2 Enable Value
+/** Offset 0x1BF3 - PL2 Enable Value
Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS
will program the default values for Platform Power Limit 2. <b>0: Disable</b>;
1: Enable.
@@ -3857,57 +3848,57 @@ typedef struct {
**/
UINT8 PsysPowerLimit2;
-/** Offset 0x1C0C - Enable or Disable MLC Streamer Prefetcher
+/** Offset 0x1BF4 - Enable or Disable MLC Streamer Prefetcher
Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MlcStreamerPrefetcher;
-/** Offset 0x1C0D - Enable or Disable MLC Spatial Prefetcher
+/** Offset 0x1BF5 - Enable or Disable MLC Spatial Prefetcher
Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 MlcSpatialPrefetcher;
-/** Offset 0x1C0E - Enable or Disable Monitor /MWAIT instructions
+/** Offset 0x1BF6 - Enable or Disable Monitor /MWAIT instructions
Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner
should not set in MWAIT Loop. 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MonitorMwaitEnable;
-/** Offset 0x1C0F - Enable or Disable initialization of machine check registers
+/** Offset 0x1BF7 - Enable or Disable initialization of machine check registers
Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MachineCheckEnable;
-/** Offset 0x1C10 - AP Idle Manner of waiting for SIPI
+/** Offset 0x1BF8 - AP Idle Manner of waiting for SIPI
AP threads Idle Manner for waiting signal to run. 1: HALT loop; <b>2: MWAIT loop</b>;
3: RUN loop.
1: HALT loop, 2: MWAIT loop, 3: RUN loop
**/
UINT8 ApIdleManner;
-/** Offset 0x1C11 - Control on Processor Trace output scheme
+/** Offset 0x1BF9 - Control on Processor Trace output scheme
Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
0: Single Range Output, 1: ToPA Output
**/
UINT8 ProcessorTraceOutputScheme;
-/** Offset 0x1C12 - Enable or Disable Processor Trace feature
+/** Offset 0x1BFA - Enable or Disable Processor Trace feature
Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ProcessorTraceEnable;
-/** Offset 0x1C13 - Enable or Disable Intel SpeedStep Technology
+/** Offset 0x1BFB - Enable or Disable Intel SpeedStep Technology
Allows more than two frequency ranges to be supported. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Eist;
-/** Offset 0x1C14 - Enable or Disable Energy Efficient P-state
+/** Offset 0x1BFC - Enable or Disable Energy Efficient P-state
Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access
to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 0 indicating no support
for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS
@@ -3917,7 +3908,7 @@ typedef struct {
**/
UINT8 EnergyEfficientPState;
-/** Offset 0x1C15 - Enable or Disable Energy Efficient Turbo
+/** Offset 0x1BFD - Enable or Disable Energy Efficient Turbo
Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically
lower the turbo frequency to increase efficiency. Recommended only to disable in
overclocking situations where turbo frequency must remain constant. Otherwise,
@@ -3926,100 +3917,100 @@ typedef struct {
**/
UINT8 EnergyEfficientTurbo;
-/** Offset 0x1C16 - Enable or Disable T states
+/** Offset 0x1BFE - Enable or Disable T states
Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 TStates;
-/** Offset 0x1C17 - Enable or Disable Bi-Directional PROCHOT#
+/** Offset 0x1BFF - Enable or Disable Bi-Directional PROCHOT#
Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 BiProcHot;
-/** Offset 0x1C18 - Enable or Disable PROCHOT# signal being driven externally
+/** Offset 0x1C00 - Enable or Disable PROCHOT# signal being driven externally
Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 DisableProcHotOut;
-/** Offset 0x1C19 - Enable or Disable PROCHOT# Response
+/** Offset 0x1C01 - Enable or Disable PROCHOT# Response
Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ProcHotResponse;
-/** Offset 0x1C1A - Enable or Disable VR Thermal Alert
+/** Offset 0x1C02 - Enable or Disable VR Thermal Alert
Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 DisableVrThermalAlert;
-/** Offset 0x1C1B - Enable or Disable Thermal Reporting
+/** Offset 0x1C03 - Enable or Disable Thermal Reporting
Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 EnableAllThermalFunctions;
-/** Offset 0x1C1C - Enable or Disable Thermal Monitor
+/** Offset 0x1C04 - Enable or Disable Thermal Monitor
Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 ThermalMonitor;
-/** Offset 0x1C1D - Enable or Disable CPU power states (C-states)
+/** Offset 0x1C05 - Enable or Disable CPU power states (C-states)
Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not
100% utilized. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Cx;
-/** Offset 0x1C1E - Configure C-State Configuration Lock
+/** Offset 0x1C06 - Configure C-State Configuration Lock
Configure MSR to CFG Lock bit. 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 PmgCstCfgCtrlLock;
-/** Offset 0x1C1F - Enable or Disable Enhanced C-states
+/** Offset 0x1C07 - Enable or Disable Enhanced C-states
Enable/Disable C1E. When enabled, CPU will switch to minimum speed when all cores
enter C-State. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1e;
-/** Offset 0x1C20 - Enable or Disable Package Cstate Demotion
+/** Offset 0x1C08 - Enable or Disable Package Cstate Demotion
Enable or Disable Package C-State Demotion. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PkgCStateDemotion;
-/** Offset 0x1C21 - Enable or Disable Package Cstate UnDemotion
+/** Offset 0x1C09 - Enable or Disable Package Cstate UnDemotion
Enable or Disable Package C-State Un-Demotion. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PkgCStateUnDemotion;
-/** Offset 0x1C22 - Enable or Disable CState-Pre wake
+/** Offset 0x1C0A - Enable or Disable CState-Pre wake
Disable - to disable the Cstate Pre-Wake. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 CStatePreWake;
-/** Offset 0x1C23 - Enable or Disable TimedMwait Support.
+/** Offset 0x1C0B - Enable or Disable TimedMwait Support.
Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 TimedMwait;
-/** Offset 0x1C24 - Enable or Disable IO to MWAIT redirection
+/** Offset 0x1C0C - Enable or Disable IO to MWAIT redirection
When set, will map IO_read instructions sent to IO registers PMG_IO_BASE_ADDRBASE+offset
to MWAIT(offset). <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 CstCfgCtrIoMwaitRedirection;
-/** Offset 0x1C25 - Set the Max Pkg Cstate
+/** Offset 0x1C0D - Set the Max Pkg Cstate
Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value.
Auto: Initializes to deepest available Package C State Limit. Valid values 0 -
C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 -
@@ -4027,38 +4018,38 @@ typedef struct {
**/
UINT8 PkgCStateLimit;
-/** Offset 0x1C26 - Interrupt Redirection Mode Select
+/** Offset 0x1C0E - Interrupt Redirection Mode Select
Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1:
Round robin; 2: Hash vector; 7: No change.
**/
UINT8 PpmIrmSetting;
-/** Offset 0x1C27 - Lock prochot configuration
+/** Offset 0x1C0F - Lock prochot configuration
Lock prochot configuration Enable/Disable; 0: Disable;<b> 1: Enable</b>
$EN_DIS
**/
UINT8 ProcHotLock;
-/** Offset 0x1C28 - Configuration for boot TDP selection
+/** Offset 0x1C10 - Configuration for boot TDP selection
cTDP(Assured Power) Mode as Nominal/Level1/Level2/Deactivate TDP(Base Power) selection.
Deactivate option will set MSR to Nominal and MMIO to Zero. <b>0: TDP(Base Power)
Nominal</b>; 1: TDP(Base Power) Down; 2: TDP(Base Power) Up;0xFF : Deactivate
**/
UINT8 ConfigTdpLevel;
-/** Offset 0x1C29 - Max P-State Ratio
+/** Offset 0x1C11 - Max P-State Ratio
Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F
**/
UINT8 MaxRatio;
-/** Offset 0x1C2A - P-state ratios for custom P-state table
+/** Offset 0x1C12 - P-state ratios for custom P-state table
P-state ratios for custom P-state table. NumberOfEntries has valid range between
0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
are configurable. Valid Range of each entry is 0 to 0x7F
**/
UINT8 StateRatio[40];
-/** Offset 0x1C52 - P-state ratios for max 16 version of custom P-state table
+/** Offset 0x1C3A - P-state ratios for max 16 version of custom P-state table
P-state ratios for max 16 version of custom P-state table. This table is used for
OS versions limited to a max of 16 P-States. If the first entry of this table is
0, or if Number of Entries is 16 or less, then this table will be ignored, and
@@ -4067,11 +4058,11 @@ typedef struct {
**/
UINT8 StateRatioMax16[16];
-/** Offset 0x1C62
+/** Offset 0x1C4A
**/
UINT8 Rsvd400[2];
-/** Offset 0x1C64 - Package Long duration turbo mode power limit
+/** Offset 0x1C4C - Package Long duration turbo mode power limit
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -4081,7 +4072,7 @@ typedef struct {
**/
UINT32 PowerLimit1;
-/** Offset 0x1C68 - Package Short duration turbo mode power limit
+/** Offset 0x1C50 - Package Short duration turbo mode power limit
Power Limit 2 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. If the value is 0, BIOS will program this value as 1.25*Processor
Base Power (TDP). Processor applies control policies such that the package power
@@ -4090,7 +4081,7 @@ typedef struct {
**/
UINT32 PowerLimit2Power;
-/** Offset 0x1C6C - Package PL3 power limit
+/** Offset 0x1C54 - Package PL3 power limit
Power Limit 3 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. XE SKU: Any value can be programmed. Overclocking SKU: Value
must be between Max and Min Power Limits. Other SKUs: This value must be between
@@ -4100,28 +4091,28 @@ typedef struct {
**/
UINT32 PowerLimit3;
-/** Offset 0x1C70 - Package PL4 power limit
+/** Offset 0x1C58 - Package PL4 power limit
Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. If the value is 0, BIOS leaves default value. Units are based
on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767.
**/
UINT32 PowerLimit4;
-/** Offset 0x1C74 - Package PL4 boost configuration
+/** Offset 0x1C5C - Package PL4 boost configuration
Configure Power Limit 4 Boost in Watts. Valid Range 0 to 1023 in step size of 1
Watt. The value 0 means disable.
**/
UINT16 PowerLimit4Boost;
-/** Offset 0x1C76
+/** Offset 0x1C5E
**/
UINT8 Rsvd410[2];
-/** Offset 0x1C78 - Tcc Offset Time Window for RATL
+/** Offset 0x1C60 - Tcc Offset Time Window for RATL
**/
UINT32 TccOffsetTimeWindowForRatl;
-/** Offset 0x1C7C - Short term Power Limit value for custom cTDP level 1
+/** Offset 0x1C64 - Short term Power Limit value for custom cTDP level 1
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -4130,7 +4121,7 @@ typedef struct {
**/
UINT32 Custom1PowerLimit1;
-/** Offset 0x1C80 - Long term Power Limit value for custom cTDP level 1
+/** Offset 0x1C68 - Long term Power Limit value for custom cTDP level 1
Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Processor applies control policies
such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -4138,7 +4129,7 @@ typedef struct {
**/
UINT32 Custom1PowerLimit2;
-/** Offset 0x1C84 - Short term Power Limit value for custom cTDP level 2
+/** Offset 0x1C6C - Short term Power Limit value for custom cTDP level 2
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -4147,7 +4138,7 @@ typedef struct {
**/
UINT32 Custom2PowerLimit1;
-/** Offset 0x1C88 - Long term Power Limit value for custom cTDP level 2
+/** Offset 0x1C70 - Long term Power Limit value for custom cTDP level 2
Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Processor applies control policies
such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -4155,7 +4146,7 @@ typedef struct {
**/
UINT32 Custom2PowerLimit2;
-/** Offset 0x1C8C - Short term Power Limit value for custom cTDP level 3
+/** Offset 0x1C74 - Short term Power Limit value for custom cTDP level 3
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -4164,7 +4155,7 @@ typedef struct {
**/
UINT32 Custom3PowerLimit1;
-/** Offset 0x1C90 - Long term Power Limit value for custom cTDP level 3
+/** Offset 0x1C78 - Long term Power Limit value for custom cTDP level 3
Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Processor applies control policies
such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -4172,7 +4163,7 @@ typedef struct {
**/
UINT32 Custom3PowerLimit2;
-/** Offset 0x1C94 - Platform PL1 power
+/** Offset 0x1C7C - Platform PL1 power
Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W
when programming. Value set 120 = 15W. Any value can be programmed between Max
and Min Power Limits. This setting will act as the new PL1 value for the Package
@@ -4181,7 +4172,7 @@ typedef struct {
**/
UINT32 PsysPowerLimit1Power;
-/** Offset 0x1C98 - Platform PL2 power
+/** Offset 0x1C80 - Platform PL2 power
Platform Power Limit 2 Power in Milli Watts. BIOS will round to the nearest 1/8W
when programming. Value set 120 = 15W. Any value can be programmed between Max
and Min Power Limits. This setting will act as the new Max Turbo Power (PL2) value
@@ -4190,13 +4181,13 @@ typedef struct {
**/
UINT32 PsysPowerLimit2Power;
-/** Offset 0x1C9C - CCF AutoGV
+/** Offset 0x1C84 - CCF AutoGV
Enable/Disable CCF AutoGV; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 CcfAutoGv;
-/** Offset 0x1C9D - Race To Halt
+/** Offset 0x1C85 - Race To Halt
Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
in order to enter pkg C-State faster to reduce overall power. 0: Disable; <b>1:
Enable</b>
@@ -4204,64 +4195,64 @@ typedef struct {
**/
UINT8 RaceToHalt;
-/** Offset 0x1C9E - Enable or Disable Three Strike Counter
+/** Offset 0x1C86 - Enable or Disable Three Strike Counter
Enable (default): Three Strike counter will be incremented. Disable: Prevents Three
Strike counter from incrementing; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 ThreeStrikeCounter;
-/** Offset 0x1C9F - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
+/** Offset 0x1C87 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 HwpInterruptControl;
-/** Offset 0x1CA0 - ReservedCpuPostMem2
+/** Offset 0x1C88 - ReservedCpuPostMem2
Reserved for CPU Post-Mem 2
$EN_DIS
**/
UINT8 ReservedCpuPostMem2[4];
-/** Offset 0x1CA4 - Enable or Disable C1 Cstate Demotion
+/** Offset 0x1C8C - Enable or Disable C1 Cstate Demotion
Enable or Disable C1 Cstate Auto Demotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1StateAutoDemotion;
-/** Offset 0x1CA5 - Enable or Disable C1 Cstate UnDemotion
+/** Offset 0x1C8D - Enable or Disable C1 Cstate UnDemotion
Enable or Disable C1 Cstate Un-Demotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1StateUnDemotion;
-/** Offset 0x1CA6 - Minimum Ring ratio limit override
+/** Offset 0x1C8E - Minimum Ring ratio limit override
Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
ratio limit
**/
UINT8 MinRingRatioLimit;
-/** Offset 0x1CA7 - Maximum Ring ratio limit override
+/** Offset 0x1C8F - Maximum Ring ratio limit override
Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
ratio limit
**/
UINT8 MaxRingRatioLimit;
-/** Offset 0x1CA8 - Enable or Disable Per Core P State OS control
+/** Offset 0x1C90 - Enable or Disable Per Core P State OS control
Enable/Disable Per Core P state OS control mode. When set, the highest core request
is used for all other core requests. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 EnablePerCorePState;
-/** Offset 0x1CA9 - Enable or Disable HwP Autonomous Per Core P State OS control
+/** Offset 0x1C91 - Enable or Disable HwP Autonomous Per Core P State OS control
Disable Autonomous PCPS Autonomous will request the same value for all cores all
the time. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 EnableHwpAutoPerCorePstate;
-/** Offset 0x1CAA - Enable or Disable HwP Autonomous EPP Grouping
+/** Offset 0x1C92 - Enable or Disable HwP Autonomous EPP Grouping
Enable EPP grouping Autonomous will request the same values for all cores with same
EPP. Disable EPP grouping autonomous will not necessarily request same values for
all cores with same EPP. <b> 0: Disable </b>; 1: Enable
@@ -4269,7 +4260,7 @@ typedef struct {
**/
UINT8 EnableHwpAutoEppGrouping;
-/** Offset 0x1CAB - Enable Configurable TDP
+/** Offset 0x1C93 - Enable Configurable TDP
Applies cTDP(Assured Power) initialization settings based on non-cTDP(Assured Power)
or cTDP(Assured Power). Default is 1: Applies to cTDP(Assured Power); if 0 then
applies non-cTDP(Assured Power) and BIOS will bypass cTDP(Assured Power) initialzation flow
@@ -4277,21 +4268,21 @@ typedef struct {
**/
UINT8 ApplyConfigTdp;
-/** Offset 0x1CAC - Misc Power Management MSR Lock
+/** Offset 0x1C94 - Misc Power Management MSR Lock
Enable/Disable HWP Lock support in Misc Power Management MSR. 0: Disable, <b>1:
Enable </b>
$EN_DIS
**/
UINT8 HwpLock;
-/** Offset 0x1CAD - Dual Tau Boost
+/** Offset 0x1C95 - Dual Tau Boost
Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W
sku. When DPTF is enabled this feature is ignored. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 DualTauBoost;
-/** Offset 0x1CAE - Response Mode
+/** Offset 0x1C96 - Response Mode
Use Response Mode to adjust Psys_PL3 power reduction behavior. Battery-enabled systems
use Gradual Power Reduction. <b>0: Gradual Power Reduction</b> ; 1: Aggressive
Power Reduction
@@ -4299,7 +4290,7 @@ typedef struct {
**/
UINT8 StepDownMode;
-/** Offset 0x1CAF - Power Floor Managment for SOC
+/** Offset 0x1C97 - Power Floor Managment for SOC
Option to disable Power Floor Managment for SOC. Disabling this might effectively
raise power floor of the SoC and may lead to stability issues. 0: Disable, <b>1:
Enable </b>
@@ -4307,57 +4298,57 @@ typedef struct {
**/
UINT8 PowerFloorManagement;
-/** Offset 0x1CB0 - Power Floor Disaplay Disconnect
+/** Offset 0x1C98 - Power Floor Disaplay Disconnect
SoC can disconnect secondary/external display to lower SoC floor power (Default
enabled). 0: Disable: Display disconnect will not be used by SoC., <b>1: Enable </b>
$EN_DIS
**/
UINT8 PowerFloorDisplayDisconnect;
-/** Offset 0x1CB1 - Resource Priority Feature
+/** Offset 0x1C99 - Resource Priority Feature
Enable/Disable Resource Priority Feature. Enable/Disable; <b>0: Disable</b> ; 1:Enable
$EN_DIS
**/
UINT8 EnableRp;
-/** Offset 0x1CB2 - Power Floor PCIe Gen Downgrade
+/** Offset 0x1C9A - Power Floor PCIe Gen Downgrade
SoC can downgrade PCIe gen speed to lower SoC floor power (Default enabled). 0:
Disable: Reduction in PCIe gen speed will not be used by SoC., <b>1: Enable </b>
$EN_DIS
**/
UINT8 PowerFloorPcieGenDowngrade;
-/** Offset 0x1CB3 - ReservedCpuPostMemTest
+/** Offset 0x1C9B - ReservedCpuPostMemTest
Reserved for CPU Post-Mem Test
$EN_DIS
**/
UINT8 ReservedCpuPostMemTest[13];
-/** Offset 0x1CC0
+/** Offset 0x1CA8
**/
UINT8 SecurityPostMemRsvd[16];
-/** Offset 0x1CD0 - End of Post message
+/** Offset 0x1CB8 - End of Post message
Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE
0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
**/
UINT8 EndOfPostMessage;
-/** Offset 0x1CD1 - D0I3 Setting for HECI Disable
+/** Offset 0x1CB9 - D0I3 Setting for HECI Disable
Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
HECI devices
$EN_DIS
**/
UINT8 DisableD0I3SettingForHeci;
-/** Offset 0x1CD2 - Mctp Broadcast Cycle
+/** Offset 0x1CBA - Mctp Broadcast Cycle
Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 MctpBroadcastCycle;
-/** Offset 0x1CD3 - ME Unconfig on RTC clear
+/** Offset 0x1CBB - ME Unconfig on RTC clear
0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
2: Cmos is clear, status unkonwn. 3: Reserved
0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
@@ -4365,193 +4356,193 @@ typedef struct {
**/
UINT8 MeUnconfigOnRtcClear;
-/** Offset 0x1CD4 - Enforce Enhanced Debug Mode
+/** Offset 0x1CBC - Enforce Enhanced Debug Mode
Determine if ME should enter Enhanced Debug Mode. <b>0: disable</b>, 1: enable
$EN_DIS
**/
UINT8 EnforceEDebugMode;
-/** Offset 0x1CD5 - CSE Data Resilience Support
+/** Offset 0x1CBD - CSE Data Resilience Support
0: Disable CSE Data Resilience Support. <b>1: Enable CSE Data Resilience Support.</b>
$EN_DIS
**/
UINT8 CseDataResilience;
-/** Offset 0x1CD6 - MePostMemRsvd
+/** Offset 0x1CBE - MePostMemRsvd
Reserved for ME Post-Mem
$EN_DIS
**/
UINT8 MePostMemRsvd[16];
-/** Offset 0x1CE6 - Enable LOCKDOWN SMI
+/** Offset 0x1CCE - Enable LOCKDOWN SMI
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
$EN_DIS
**/
UINT8 PchLockDownGlobalSmi;
-/** Offset 0x1CE7 - Enable LOCKDOWN BIOS Interface
+/** Offset 0x1CCF - Enable LOCKDOWN BIOS Interface
Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
$EN_DIS
**/
UINT8 PchLockDownBiosInterface;
-/** Offset 0x1CE8 - Unlock all GPIO pads
+/** Offset 0x1CD0 - Unlock all GPIO pads
Force all GPIO pads to be unlocked for debug purpose.
$EN_DIS
**/
UINT8 PchUnlockGpioPads;
-/** Offset 0x1CE9 - PCH Unlock SideBand access
+/** Offset 0x1CD1 - PCH Unlock SideBand access
The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
$EN_DIS
**/
UINT8 PchSbAccessUnlock;
-/** Offset 0x1CEA
+/** Offset 0x1CD2
**/
UINT8 Rsvd420[2];
-/** Offset 0x1CEC - PCIE RP Ltr Max Snoop Latency
+/** Offset 0x1CD4 - PCIE RP Ltr Max Snoop Latency
Latency Tolerance Reporting, Max Snoop Latency.
**/
UINT16 PcieRpLtrMaxSnoopLatency[29];
-/** Offset 0x1D26 - PCIE RP Ltr Max No Snoop Latency
+/** Offset 0x1D0E - PCIE RP Ltr Max No Snoop Latency
Latency Tolerance Reporting, Max Non-Snoop Latency.
**/
UINT16 PcieRpLtrMaxNoSnoopLatency[29];
-/** Offset 0x1D60 - PCIE RP Snoop Latency Override Mode
+/** Offset 0x1D48 - PCIE RP Snoop Latency Override Mode
Latency Tolerance Reporting, Snoop Latency Override Mode.
**/
UINT8 PcieRpSnoopLatencyOverrideMode[29];
-/** Offset 0x1D7D - PCIE RP Snoop Latency Override Multiplier
+/** Offset 0x1D65 - PCIE RP Snoop Latency Override Multiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
**/
UINT8 PcieRpSnoopLatencyOverrideMultiplier[29];
-/** Offset 0x1D9A - PCIE RP Snoop Latency Override Value
+/** Offset 0x1D82 - PCIE RP Snoop Latency Override Value
Latency Tolerance Reporting, Snoop Latency Override Value.
**/
UINT16 PcieRpSnoopLatencyOverrideValue[29];
-/** Offset 0x1DD4 - PCIE RP Non Snoop Latency Override Mode
+/** Offset 0x1DBC - PCIE RP Non Snoop Latency Override Mode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
**/
UINT8 PcieRpNonSnoopLatencyOverrideMode[29];
-/** Offset 0x1DF1 - PCIE RP Non Snoop Latency Override Multiplier
+/** Offset 0x1DD9 - PCIE RP Non Snoop Latency Override Multiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
**/
UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[29];
-/** Offset 0x1E0E - PCIE RP Non Snoop Latency Override Value
+/** Offset 0x1DF6 - PCIE RP Non Snoop Latency Override Value
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
**/
UINT16 PcieRpNonSnoopLatencyOverrideValue[29];
-/** Offset 0x1E48 - PCIE RP Slot Power Limit Scale
+/** Offset 0x1E30 - PCIE RP Slot Power Limit Scale
Specifies scale used for slot power limit value. Leave as 0 to set to default.
**/
UINT8 PcieRpSlotPowerLimitScale[29];
-/** Offset 0x1E65
+/** Offset 0x1E4D
**/
UINT8 Rsvd430[1];
-/** Offset 0x1E66 - PCIE RP Slot Power Limit Value
+/** Offset 0x1E4E - PCIE RP Slot Power Limit Value
Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
**/
UINT16 PcieRpSlotPowerLimitValue[29];
-/** Offset 0x1EA0 - PCIE RP Enable Port8xh Decode
+/** Offset 0x1E88 - PCIE RP Enable Port8xh Decode
This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
1: Enable.
$EN_DIS
**/
UINT8 PcieEnablePort8xhDecode;
-/** Offset 0x1EA1 - PCIE Port8xh Decode Port Index
+/** Offset 0x1E89 - PCIE Port8xh Decode Port Index
The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
**/
UINT8 PchPciePort8xhDecodePortIndex;
-/** Offset 0x1EA2 - PCH Energy Reporting
+/** Offset 0x1E8A - PCH Energy Reporting
Disable/Enable PCH to CPU energy report feature.
$EN_DIS
**/
UINT8 PchPmDisableEnergyReport;
-/** Offset 0x1EA3 - PCH Sata Test Mode
+/** Offset 0x1E8B - PCH Sata Test Mode
Allow entrance to the PCH SATA test modes.
$EN_DIS
**/
UINT8 SataTestMode;
-/** Offset 0x1EA4 - PCH USB OverCurrent mapping lock enable
+/** Offset 0x1E8C - PCH USB OverCurrent mapping lock enable
If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
$EN_DIS
**/
UINT8 PchXhciOcLock;
-/** Offset 0x1EA5 - Low Power Mode Enable/Disable config mask
+/** Offset 0x1E8D - Low Power Mode Enable/Disable config mask
Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds
to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4.
**/
UINT8 PmcLpmS0ixSubStateEnableMask;
-/** Offset 0x1EA6 - Low Power Mode Enable/Disable config mask
+/** Offset 0x1E8E - Low Power Mode Enable/Disable config mask
Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds
to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4.
**/
UINT8 PmcPchLpmS0ixSubStateEnableMask;
-/** Offset 0x1EA7 - PCH PMC ER Debug mode
+/** Offset 0x1E8F - PCH PMC ER Debug mode
Disable/Enable Energy Reporting Debug Mode.
$EN_DIS
**/
UINT8 PchPmErDebugMode;
-/** Offset 0x1EA8 - CPPM Forced Alignment Enable
+/** Offset 0x1E90 - CPPM Forced Alignment Enable
Enable/Disable CPPM Force Alignment. When enabled, PMC allows stalling of the backbone
or blocking the DMI transmit arbiter
$EN_DIS
**/
UINT8 CppmFaEn;
-/** Offset 0x1EA9 - PCH Lan WOL Fast Support
+/** Offset 0x1E91 - PCH Lan WOL Fast Support
Enables bit B_PCH_ACPI_GPE0_EN_127_96_PME_B0 during PchLanSxCallback in PchLanSxSmm.
$EN_DIS
**/
UINT8 PchLanWOLFastSupport;
-/** Offset 0x1EAA - Platform ATX Telemetry Unit
+/** Offset 0x1E92 - Platform ATX Telemetry Unit
Set ATX Telemetry Unit in Watts or Percentage; <b>0: Watts</b>; 1: Percent
$EN_DIS
**/
UINT8 PlatformAtxTelemetryUnit;
-/** Offset 0x1EAB - PCIE RP LTR Override Spec Complaint
+/** Offset 0x1E93 - PCIE RP LTR Override Spec Complaint
Override LTR based on Ep capability.
**/
UINT8 PcieRpLtrOverrideSpecComplaint[29];
-/** Offset 0x1EC8
+/** Offset 0x1EB0
**/
UINT8 PchMeFspsUpdRsvd[71];
-/** Offset 0x1F0F - PMC C10 dynamic threshold dajustment enable
+/** Offset 0x1EF7 - PMC C10 dynamic threshold dajustment enable
Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
$EN_DIS
**/
UINT8 PmcC10DynamicThresholdAdjustment;
-/** Offset 0x1F10 - Turbo Ratio Limit Ratio array
+/** Offset 0x1EF8 - Turbo Ratio Limit Ratio array
Performance-core Turbo Ratio Limit Ratio0-7 (TRLR) defines the turbo ratio (max
is 85 in normal mode and 120 in core extension mode). Ratio[0]: This Turbo Ratio
Limit Ratio0 must be greater than or equal all other ratio values. If this value
@@ -4561,46 +4552,50 @@ typedef struct {
**/
UINT8 TurboRatioLimitRatio[8];
-/** Offset 0x1F18 - Turbo Ratio Limit Num Core array
+/** Offset 0x1F00 - Turbo Ratio Limit Num Core array
Performance-core Turbo Ratio Limit Core0~7 defines the core range, the turbo ratio
is defined in Turbo Ratio Limit Ratio0~7. If value is zero, this entry is ignored.
**/
UINT8 TurboRatioLimitNumCore[8];
-/** Offset 0x1F20 - ATOM Turbo Ratio Limit Ratio array
+/** Offset 0x1F08 - ATOM Turbo Ratio Limit Ratio array
Efficient-core Turbo Ratio Limit Ratio0-7 defines the turbo ratio (max is 85 irrespective
of the core extension mode), the core range is defined in E-core Turbo Ratio Limit
CoreCount0-7.
**/
UINT8 AtomTurboRatioLimitRatio[8];
-/** Offset 0x1F28 - ATOM Turbo Ratio Limit Num Core array
+/** Offset 0x1F10 - ATOM Turbo Ratio Limit Num Core array
Efficient-core Turbo Ratio Limit CoreCount0-7 defines the core range, the turbo
ratio is defined in E-core Turbo Ratio Limit Ratio0-7. If value is zero, this entry
is ignored.
**/
UINT8 AtomTurboRatioLimitNumCore[8];
-/** Offset 0x1F30
+/** Offset 0x1F18
+**/
+ UINT8 PlatformReliabilityTuning;
+
+/** Offset 0x1F19
**/
- UINT8 Rsvd440[4];
+ UINT8 Rsvd440[3];
-/** Offset 0x1F34 - FspEventHandler
+/** Offset 0x1F1C - FspEventHandler
<b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
**/
UINT32 FspEventHandler;
-/** Offset 0x1F38 - Type C Port x Convert to TypeA
+/** Offset 0x1F20 - Type C Port x Convert to TypeA
Enable / Disable(default) Type C Port x Convert to TypeA
$EN_DIS
**/
UINT8 EnableTcssCovTypeA[4];
-/** Offset 0x1F3C
+/** Offset 0x1F24
**/
UINT8 Rsvd450[16];
-/** Offset 0x1F4C
+/** Offset 0x1F34
**/
UINT8 ReservedFspsUpd[12];
} FSP_S_CONFIG;
@@ -4621,11 +4616,11 @@ typedef struct {
**/
FSP_S_CONFIG FspsConfig;
-/** Offset 0x1F58
+/** Offset 0x1F40
**/
UINT8 Rsvd600[6];
-/** Offset 0x1F5E
+/** Offset 0x1F46
**/
UINT16 UpdTerminator;
} FSPS_UPD;
diff --git a/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FsptUpd.h b/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FsptUpd.h
index 7551ddd..45b2414 100644
--- a/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FsptUpd.h
+++ b/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/FsptUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2025, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
diff --git a/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/MemInfoHob.h b/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/MemInfoHob.h
index 35036a0..126e077 100644
--- a/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/MemInfoHob.h
+++ b/MeteorLakeFspBinPkg/IoT/MeteorLake/Include/MemInfoHob.h
@@ -4,9 +4,33 @@
data hobs.
@copyright
- Copyright 1999 - 2022 Intel Corporation. All rights reserved.<BR>
-
- SPDX-License-Identifier: BSD-2-Clause-Patent
+ INTEL CONFIDENTIAL
+ Copyright 1999 - 2022 Intel Corporation.
+
+ The source code contained or described herein and all documents related to the
+ source code ("Material") are owned by Intel Corporation or its suppliers or
+ licensors. Title to the Material remains with Intel Corporation or its suppliers
+ and licensors. The Material may contain trade secrets and proprietary and
+ confidential information of Intel Corporation and its suppliers and licensors,
+ and is protected by worldwide copyright and trade secret laws and treaty
+ provisions. No part of the Material may be used, copied, reproduced, modified,
+ published, uploaded, posted, transmitted, distributed, or disclosed in any way
+ without Intel's prior express written permission.
+
+ No license under any patent, copyright, trade secret or other intellectual
+ property right is granted to or conferred upon you by disclosure or delivery
+ of the Materials, either expressly, by implication, inducement, estoppel or
+ otherwise. Any license under such intellectual property rights must be
+ express and approved by Intel in writing.
+
+ Unless otherwise agreed by Intel in writing, you may not remove or alter
+ this notice or any other notice embedded in Materials by Intel or
+ Intel's suppliers or licensors in any way.
+
+ This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+ "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+ the terms of your license agreement with Intel or your vendor. This file may
+ be modified by the user, subject to additional terms of the license agreement.
@par Specification Reference:
**/
diff --git a/MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/Vbt.bin b/MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/VBT_MTL.bin
index ae646df..08e3b49 100644
--- a/MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/Vbt.bin
+++ b/MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/VBT_MTL.bin
Binary files differ
diff --git a/MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/Vbt_MTL.json b/MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/Vbt_MTL.json
index 0a6596e..3627d9b 100644
--- a/MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/Vbt_MTL.json
+++ b/MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/Vbt_MTL.json
@@ -5479,7 +5479,7 @@
"Block": {
"Id": "27",
"Name": "eDP Power Sequencing",
- "SizeInBytes": "817",
+ "SizeInBytes": "853",
"BlockIdSizeInBytes": "1",
"BlockSizeSizeInBytes": "2",
"StartOffset": "",
@@ -8752,6 +8752,125 @@
"ByteOffset": "",
"BitOffset": "",
"Value": ""
+ },
+ {
+ "Name": "SKIP",
+ "SizeInBits": "272",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_01",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_02",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_03",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_04",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_05",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_06",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_07",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_08",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_09",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_10",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_11",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_12",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_13",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_14",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_15",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "eDP_Pipe_Joiner_Feature_16",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
}
]
}
@@ -13133,7 +13252,7 @@
"Block": {
"Id": "44",
"Name": "BIA (Backlight Image Adaption) Support",
- "SizeInBytes": "101",
+ "SizeInBytes": "139",
"BlockIdSizeInBytes": "1",
"BlockSizeSizeInBytes": "2",
"StartOffset": "",
@@ -15405,6 +15524,678 @@
"ByteOffset": "",
"BitOffset": "",
"Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_01",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_02",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_03",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_04",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_05",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_06",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_07",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_08",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_09",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_10",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_11",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_12",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_13",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_14",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_15",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "PanelIdentifier_Type_16",
+ "SizeInBits": "8",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_01",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_02",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_03",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_04",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_05",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_06",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_07",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_08",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_09",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_10",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_11",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_12",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_13",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_14",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_15",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Enable_16",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_01",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_02",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_03",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_04",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_05",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_06",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_07",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_08",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_09",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_10",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_11",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_12",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_13",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_14",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_15",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Enable_16",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_01",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_01",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_02",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_02",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_03",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_03",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_04",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_04",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_05",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_05",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_06",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_06",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_07",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_07",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_08",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_08",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_09",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_09",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_10",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_10",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_11",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_11",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_12",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_12",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_13",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_13",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_14",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_14",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_15",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_15",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "XPST_Aggressiveness_Profile_16",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_Aggressiveness_Profile_16",
+ "SizeInBits": "4",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_01",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_02",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_03",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_04",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_05",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_06",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_07",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_08",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_09",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_10",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_11",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_12",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_13",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_14",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_15",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
+ },
+ {
+ "Name": "TCON_XPST_Enable_16",
+ "SizeInBits": "1",
+ "ByteOffset": "",
+ "BitOffset": "",
+ "Value": ""
}
]
}
@@ -25262,7 +26053,7 @@
"PageID": [
{
"WidgetType": "Label",
- "WidgetName": "PLATFORM: MeteorLake",
+ "WidgetName": "PLATFORM: MeteorLake/ArrowLake",
"Visibility": "",
"Data": [],
"HelpText": "",
@@ -25270,7 +26061,7 @@
},
{
"WidgetType": "Label",
- "WidgetName": "VBT Version: 256",
+ "WidgetName": "VBT Version: 261",
"Visibility": "",
"Data": [],
"HelpText": "",
@@ -28618,6 +29409,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_01"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -29611,49 +30422,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_01"
+ "Lfp_Pwm_Source_Selection_01"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_01"
+ "BLC_Inv_Type_01"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -29679,7 +30482,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -30219,6 +31022,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_02"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -31212,49 +32035,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_02"
+ "Lfp_Pwm_Source_Selection_02"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_02"
+ "BLC_Inv_Type_02"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -31280,7 +32095,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -31820,6 +32635,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_03"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -32813,49 +33648,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_03"
+ "Lfp_Pwm_Source_Selection_03"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_03"
+ "BLC_Inv_Type_03"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -32881,7 +33708,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -33421,6 +34248,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_04"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -34414,49 +35261,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_04"
+ "Lfp_Pwm_Source_Selection_04"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_04"
+ "BLC_Inv_Type_04"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -34482,7 +35321,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -35022,6 +35861,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_05"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -36015,49 +36874,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_05"
+ "Lfp_Pwm_Source_Selection_05"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_05"
+ "BLC_Inv_Type_05"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -36083,7 +36934,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -36623,6 +37474,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_06"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -37616,49 +38487,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_06"
+ "Lfp_Pwm_Source_Selection_06"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_06"
+ "BLC_Inv_Type_06"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -37684,7 +38547,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -38224,6 +39087,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_07"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -39217,49 +40100,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_07"
+ "Lfp_Pwm_Source_Selection_07"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_07"
+ "BLC_Inv_Type_07"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -39285,7 +40160,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -39825,6 +40700,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_08"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -40818,49 +41713,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_08"
+ "Lfp_Pwm_Source_Selection_08"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_08"
+ "BLC_Inv_Type_08"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -40886,7 +41773,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -41426,6 +42313,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_09"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -42419,49 +43326,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_09"
+ "Lfp_Pwm_Source_Selection_09"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_09"
+ "BLC_Inv_Type_09"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -42487,7 +43386,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -43027,6 +43926,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_10"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -44020,49 +44939,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_10"
+ "Lfp_Pwm_Source_Selection_10"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_10"
+ "BLC_Inv_Type_10"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -44088,7 +44999,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -44628,6 +45539,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_11"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -45621,49 +46552,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_11"
+ "Lfp_Pwm_Source_Selection_11"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_11"
+ "BLC_Inv_Type_11"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -45689,7 +46612,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -46229,6 +47152,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_12"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -47222,49 +48165,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_12"
+ "Lfp_Pwm_Source_Selection_12"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_12"
+ "BLC_Inv_Type_12"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -47290,7 +48225,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -47830,6 +48765,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_13"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -48823,49 +49778,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_13"
+ "Lfp_Pwm_Source_Selection_13"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_13"
+ "BLC_Inv_Type_13"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -48891,7 +49838,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -49431,6 +50378,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_14"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -50424,49 +51391,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_14"
+ "Lfp_Pwm_Source_Selection_14"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_14"
+ "BLC_Inv_Type_14"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -50492,7 +51451,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -51032,6 +51991,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_15"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -52025,49 +53004,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_15"
+ "Lfp_Pwm_Source_Selection_15"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_15"
+ "BLC_Inv_Type_15"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -52093,7 +53064,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -52633,6 +53604,26 @@
]
},
{
+ "WidgetType": "ComboBox",
+ "WidgetName": " eDP Pipe Joiner Feature: ",
+ "Visibility": "",
+ "Data": [
+ "27",
+ "eDP_Pipe_Joiner_Feature_16"
+ ],
+ "HelpText": "This feature when set to yes, will enable Pipe Joiner feature for eDP display. Please note: Feature is only supported in ARL platform and Not supported in pre-OS.",
+ "WidgetValues": [
+ {
+ "Key": "Enabled",
+ "Value": "1"
+ },
+ {
+ "Key": "Disabled",
+ "Value": "0"
+ }
+ ]
+ },
+ {
"WidgetType": "Button",
"WidgetName": "Power Features",
"Visibility": "",
@@ -53626,49 +54617,41 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Type: ",
+ "WidgetName": "Brightness Control Selection: ",
"Visibility": "",
"Data": [
"43",
- "BLC_Inv_Type_16"
+ "Lfp_Pwm_Source_Selection_16"
],
- "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
+ "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'Brightness Control Selection' will be used",
"WidgetValues": [
{
- "Key": "None/External",
- "Value": "0"
+ "Key": "PWM From Display Engine/AUX default",
+ "Value": "2"
},
{
- "Key": "PWM",
- "Value": "2"
+ "Key": "Legacy VESA eDP AUX Interface",
+ "Value": "5"
}
]
},
{
"WidgetType": "ComboBox",
- "WidgetName": " Pwm Source Selection: ",
+ "WidgetName": "Inverter Type: ",
"Visibility": "",
"Data": [
"43",
- "Lfp_Pwm_Source_Selection_16"
+ "BLC_Inv_Type_16"
],
- "HelpText": "If panel supports 'Intel HDR AUX Interface', it will always be chosen by default. If not, value in 'PWM Source Selection' will be used",
+ "HelpText": "This feature allows for the selection of the Backlight Inverter type that is to be used to control the backlight brightness of the LFP.\nWhen PWM is selected, the driver and VBIOS will control the backlight brightness via the integrated PWM solution for the applicable chipsets.\nWhen None/External is selected, the system BIOS will control the backlight brightness via the external solution.",
"WidgetValues": [
{
- "Key": "PWM From Display Engine",
- "Value": "2"
- },
- {
- "Key": "PWM From LCD Panel",
- "Value": "3"
- },
- {
- "Key": "Panel Driver Interface",
- "Value": "4"
+ "Key": "None/External",
+ "Value": "0"
},
{
- "Key": "VESA eDP AUX Interface",
- "Value": "5"
+ "Key": "PWM/Internal",
+ "Value": "2"
}
]
},
@@ -53694,7 +54677,7 @@
},
{
"WidgetType": "ComboBox",
- "WidgetName": "Inverter Polarity: ",
+ "WidgetName": " Inverter Polarity: ",
"Visibility": "",
"Data": [
"43",
@@ -54558,7 +55541,7 @@
"2",
"EFP1_IsMaxFrlRateFieldValid"
],
- "HelpText": "Indicates if we need to consider the MaxFrlRate field for HDMI2.1\nNo - Don't consider the MaximumFrlRate for limiting the FrlRates on HDMI2.1 displays\nYes - MaximumFrlRate given in bits 0 to 3 are used to override Max FRL Rate supported by platform/panel",
+ "HelpText": "Indicates if we need to consider the \"Maximum FrlRate\" field for HDMI2.1 as explained in below table\n----------------------------------------------------------------------------------------\n|\tIs Max FrlRate Field Valid\t|\t Maximum FrlRate \t|\t HDMI Mode Of Operation \t|\n----------------------------------------------------------------------------------------\n|\t No \t|\t NA \t|\t HDMI 2.0 TMDS Mode \t|\n|\t Yes \t|\tFrlRates Not Supported\t|\t HDMI 2.0 TMDS Mode \t|\n|\t Yes \t|\t <3,6,8,10,12>Gbps \t|\t HDMI 2.1 FRL Mode \t|\n----------------------------------------------------------------------------------------\n",
"WidgetValues": [
{
"Key": "No",
@@ -55443,7 +56426,7 @@
"2",
"EFP2_IsMaxFrlRateFieldValid"
],
- "HelpText": "Indicates if we need to consider the MaxFrlRate field for HDMI2.1\nNo - Don't consider the MaximumFrlRate for limiting the FrlRates on HDMI2.1 displays\nYes - MaximumFrlRate given in bits 0 to 3 are used to override Max FRL Rate supported by platform/panel",
+ "HelpText": "Indicates if we need to consider the \"Maximum FrlRate\" field for HDMI2.1 as explained in below table\n----------------------------------------------------------------------------------------\n|\tIs Max FrlRate Field Valid\t|\t Maximum FrlRate \t|\t HDMI Mode Of Operation \t|\n----------------------------------------------------------------------------------------\n|\t No \t|\t NA \t|\t HDMI 2.0 TMDS Mode \t|\n|\t Yes \t|\tFrlRates Not Supported\t|\t HDMI 2.0 TMDS Mode \t|\n|\t Yes \t|\t <3,6,8,10,12>Gbps \t|\t HDMI 2.1 FRL Mode \t|\n----------------------------------------------------------------------------------------\n",
"WidgetValues": [
{
"Key": "No",
@@ -56328,7 +57311,7 @@
"2",
"EFP3_IsMaxFrlRateFieldValid"
],
- "HelpText": "Indicates if we need to consider the MaxFrlRate field for HDMI2.1\nNo - Don't consider the MaximumFrlRate for limiting the FrlRates on HDMI2.1 displays\nYes - MaximumFrlRate given in bits 0 to 3 are used to override Max FRL Rate supported by platform/panel",
+ "HelpText": "Indicates if we need to consider the \"Maximum FrlRate\" field for HDMI2.1 as explained in below table\n----------------------------------------------------------------------------------------\n|\tIs Max FrlRate Field Valid\t|\t Maximum FrlRate \t|\t HDMI Mode Of Operation \t|\n----------------------------------------------------------------------------------------\n|\t No \t|\t NA \t|\t HDMI 2.0 TMDS Mode \t|\n|\t Yes \t|\tFrlRates Not Supported\t|\t HDMI 2.0 TMDS Mode \t|\n|\t Yes \t|\t <3,6,8,10,12>Gbps \t|\t HDMI 2.1 FRL Mode \t|\n----------------------------------------------------------------------------------------\n",
"WidgetValues": [
{
"Key": "No",
@@ -57213,7 +58196,7 @@
"2",
"EFP4_IsMaxFrlRateFieldValid"
],
- "HelpText": "Indicates if we need to consider the MaxFrlRate field for HDMI2.1\nNo - Don't consider the MaximumFrlRate for limiting the FrlRates on HDMI2.1 displays\nYes - MaximumFrlRate given in bits 0 to 3 are used to override Max FRL Rate supported by platform/panel",
+ "HelpText": "Indicates if we need to consider the \"Maximum FrlRate\" field for HDMI2.1 as explained in below table\n----------------------------------------------------------------------------------------\n|\tIs Max FrlRate Field Valid\t|\t Maximum FrlRate \t|\t HDMI Mode Of Operation \t|\n----------------------------------------------------------------------------------------\n|\t No \t|\t NA \t|\t HDMI 2.0 TMDS Mode \t|\n|\t Yes \t|\tFrlRates Not Supported\t|\t HDMI 2.0 TMDS Mode \t|\n|\t Yes \t|\t <3,6,8,10,12>Gbps \t|\t HDMI 2.1 FRL Mode \t|\n----------------------------------------------------------------------------------------\n",
"WidgetValues": [
{
"Key": "No",
@@ -58098,7 +59081,7 @@
"2",
"EFP5_IsMaxFrlRateFieldValid"
],
- "HelpText": "Indicates if we need to consider the MaxFrlRate field for HDMI2.1\nNo - Don't consider the MaximumFrlRate for limiting the FrlRates on HDMI2.1 displays\nYes - MaximumFrlRate given in bits 0 to 3 are used to override Max FRL Rate supported by platform/panel",
+ "HelpText": "Indicates if we need to consider the \"Maximum FrlRate\" field for HDMI2.1 as explained in below table\n----------------------------------------------------------------------------------------\n|\tIs Max FrlRate Field Valid\t|\t Maximum FrlRate \t|\t HDMI Mode Of Operation \t|\n----------------------------------------------------------------------------------------\n|\t No \t|\t NA \t|\t HDMI 2.0 TMDS Mode \t|\n|\t Yes \t|\tFrlRates Not Supported\t|\t HDMI 2.0 TMDS Mode \t|\n|\t Yes \t|\t <3,6,8,10,12>Gbps \t|\t HDMI 2.1 FRL Mode \t|\n----------------------------------------------------------------------------------------\n",
"WidgetValues": [
{
"Key": "No",
@@ -58983,7 +59966,7 @@
"2",
"EFP6_IsMaxFrlRateFieldValid"
],
- "HelpText": "Indicates if we need to consider the MaxFrlRate field for HDMI2.1\nNo - Don't consider the MaximumFrlRate for limiting the FrlRates on HDMI2.1 displays\nYes - MaximumFrlRate given in bits 0 to 3 are used to override Max FRL Rate supported by platform/panel",
+ "HelpText": "Indicates if we need to consider the \"Maximum FrlRate\" field for HDMI2.1 as explained in below table\n----------------------------------------------------------------------------------------\n|\tIs Max FrlRate Field Valid\t|\t Maximum FrlRate \t|\t HDMI Mode Of Operation \t|\n----------------------------------------------------------------------------------------\n|\t No \t|\t NA \t|\t HDMI 2.0 TMDS Mode \t|\n|\t Yes \t|\tFrlRates Not Supported\t|\t HDMI 2.0 TMDS Mode \t|\n|\t Yes \t|\t <3,6,8,10,12>Gbps \t|\t HDMI 2.1 FRL Mode \t|\n----------------------------------------------------------------------------------------\n",
"WidgetValues": [
{
"Key": "No",
diff --git a/MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/Vbt_MTLS.bin b/MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/Vbt_MTLS.bin
deleted file mode 100644
index a7359f1..0000000
--- a/MeteorLakeFspBinPkg/IoT/MeteorLake/VbtBin/Vbt_MTLS.bin
+++ /dev/null
Binary files differ
generated by cgit v1.2.3 (git 2.39.0) at 2026-10-01 17:15:24 +0300