Updated to Rangeley FSP POSTGOLD 1.6RangeleyPostGold6Fsp006

17 files changed, 96 insertions, 98 deletions

diff --git a/RangeleyFspBinPkg/Docs/RangeleyFspIntegrationGuide.pdf b/RangeleyFspBinPkg/Docs/RangeleyFspIntegrationGuide.pdf
index 907e09b..c515c51 100755..100644
--- a/RangeleyFspBinPkg/Docs/RangeleyFspIntegrationGuide.pdf
+++ b/RangeleyFspBinPkg/Docs/RangeleyFspIntegrationGuide.pdf
diff --git a/RangeleyFspBinPkg/Docs/RangeleyFspReleaseNotes.pdf b/RangeleyFspBinPkg/Docs/RangeleyFspReleaseNotes.pdf
index efdb64d..9c5c5f6 100755..100644
--- a/RangeleyFspBinPkg/Docs/RangeleyFspReleaseNotes.pdf
+++ b/RangeleyFspBinPkg/Docs/RangeleyFspReleaseNotes.pdf
diff --git a/RangeleyFspBinPkg/FspBin/RangeleyFSP.bsf b/RangeleyFspBinPkg/FspBin/RangeleyFSP.bsf
index 136c322..caf6d2a 100755..100644
--- a/RangeleyFspBinPkg/FspBin/RangeleyFSP.bsf
+++ b/RangeleyFspBinPkg/FspBin/RangeleyFSP.bsf
@@ -8,7 +8,7 @@
   be modified by end users or could render the generated boot loader

   inoperable.

 

-  Copyright (c) 2016 Intel Corporation. All rights reserved

+  Copyright (c) 2017 Intel Corporation. All rights reserved

   This software and associated documentation (if any) is furnished

   under a license and may only be used or copied in accordance

   with the terms of the license. Except as permitted by such

@@ -60,10 +60,10 @@ StructDef
         $gPlatformFspPkgTokenSpaceGuid_PcdEccSupport                   1 bytes    $_DEFAULT_ = 1

         $gPlatformFspPkgTokenSpaceGuid_PcdSerialPortBaudRate           1 bytes    $_DEFAULT_ = 1

         Skip 8 bytes

-        $gPlatformFspPkgTokenSpaceGuid_PcdCustomerRevision            32 bytes    $_DEFAULT_ = "version xxx"

+        $gPlatformFspPkgTokenSpaceGuid_PcdCustomerRevision            32 bytes    $_DEFAULT_ = 0x76,0x65,0x72,0x73,0x69,0x6F,0x6E,0x20,0x78,0x78,0x78,0x00

 

     Find "AVNRNG-V"

-        $gPlatformFspPkgTokenSpaceGuid_PcdImageRevision                4 bytes    $_DEFAULT_ = 0x00000150

+        $gPlatformFspPkgTokenSpaceGuid_PcdImageRevision                4 bytes    $_DEFAULT_ = 0x00000160

         Skip 24 bytes

         $gPlatformFspPkgTokenSpaceGuid_PcdSpdWriteProtect              1 bytes    $_DEFAULT_ = 0x01

         $gPlatformFspPkgTokenSpaceGuid_PcdTcoEnable                    1 bytes    $_DEFAULT_ = 0x00

@@ -101,8 +101,6 @@ List &gPlatformFspPkgTokenSpaceGuid_PcdSerialPortBaudRate
     Selection 6 , "19200"

     Selection 12 , "9600"

     Selection 24 , "4800"

-    Selection 48 , "2400"

-    Selection 96 , "1200"

 EndList

 

 List &gPlatformFspPkgTokenSpaceGuid_PcdMrcInitTsegSize

diff --git a/RangeleyFspBinPkg/FspBin/RangeleyFSP.fd b/RangeleyFspBinPkg/FspBin/RangeleyFSP.fd
index 061230b..6c222ac 100755..100644
--- a/RangeleyFspBinPkg/FspBin/RangeleyFSP.fd
+++ b/RangeleyFspBinPkg/FspBin/RangeleyFSP.fd
diff --git a/RangeleyFspBinPkg/Include/fspapi.h b/RangeleyFspBinPkg/Include/fspapi.h
index 5009246..5009246 100755..100644
--- a/RangeleyFspBinPkg/Include/fspapi.h
+++ b/RangeleyFspBinPkg/Include/fspapi.h
diff --git a/RangeleyFspBinPkg/Include/fspbootmode.h b/RangeleyFspBinPkg/Include/fspbootmode.h
index 16cddf0..16cddf0 100755..100644
--- a/RangeleyFspBinPkg/Include/fspbootmode.h
+++ b/RangeleyFspBinPkg/Include/fspbootmode.h
diff --git a/RangeleyFspBinPkg/Include/fspffs.h b/RangeleyFspBinPkg/Include/fspffs.h
index 9e8244d..9e8244d 100755..100644
--- a/RangeleyFspBinPkg/Include/fspffs.h
+++ b/RangeleyFspBinPkg/Include/fspffs.h
diff --git a/RangeleyFspBinPkg/Include/fspfv.h b/RangeleyFspBinPkg/Include/fspfv.h
index 9688cf4..9688cf4 100755..100644
--- a/RangeleyFspBinPkg/Include/fspfv.h
+++ b/RangeleyFspBinPkg/Include/fspfv.h
diff --git a/RangeleyFspBinPkg/Include/fspguid.h b/RangeleyFspBinPkg/Include/fspguid.h
index b9a6183..b9a6183 100755..100644
--- a/RangeleyFspBinPkg/Include/fspguid.h
+++ b/RangeleyFspBinPkg/Include/fspguid.h
diff --git a/RangeleyFspBinPkg/Include/fsphob.h b/RangeleyFspBinPkg/Include/fsphob.h
index 0f743b5..0f743b5 100755..100644
--- a/RangeleyFspBinPkg/Include/fsphob.h
+++ b/RangeleyFspBinPkg/Include/fsphob.h
diff --git a/RangeleyFspBinPkg/Include/fspinfoheader.h b/RangeleyFspBinPkg/Include/fspinfoheader.h
index 28382cf..28382cf 100755..100644
--- a/RangeleyFspBinPkg/Include/fspinfoheader.h
+++ b/RangeleyFspBinPkg/Include/fspinfoheader.h
diff --git a/RangeleyFspBinPkg/Include/fspplatform.h b/RangeleyFspBinPkg/Include/fspplatform.h
index c35dca0..c35dca0 100755..100644
--- a/RangeleyFspBinPkg/Include/fspplatform.h
+++ b/RangeleyFspBinPkg/Include/fspplatform.h
diff --git a/RangeleyFspBinPkg/Include/fspsupport.h b/RangeleyFspBinPkg/Include/fspsupport.h
index dbbbf77..dbbbf77 100755..100644
--- a/RangeleyFspBinPkg/Include/fspsupport.h
+++ b/RangeleyFspBinPkg/Include/fspsupport.h
diff --git a/RangeleyFspBinPkg/Include/fsptypes.h b/RangeleyFspBinPkg/Include/fsptypes.h
index da19250..da19250 100755..100644
--- a/RangeleyFspBinPkg/Include/fsptypes.h
+++ b/RangeleyFspBinPkg/Include/fsptypes.h
diff --git a/RangeleyFspBinPkg/Include/fspvpd.h b/RangeleyFspBinPkg/Include/fspvpd.h
index 433f41c..55813ad 100755..100644
--- a/RangeleyFspBinPkg/Include/fspvpd.h
+++ b/RangeleyFspBinPkg/Include/fspvpd.h
@@ -1,93 +1,93 @@
-/** @file

-

-Copyright (C) 2016, Intel Corporation

-

-Redistribution and use in source and binary forms, with or without modification,

-are permitted provided that the following conditions are met:

-

-* Redistributions of source code must retain the above copyright notice, this

-  list of conditions and the following disclaimer.

-* Redistributions in binary form must reproduce the above copyright notice, this

-  list of conditions and the following disclaimer in the documentation and/or

-  other materials provided with the distribution.

-* Neither the name of Intel Corporation nor the names of its contributors may

-  be used to endorse or promote products derived from this software without

-  specific prior written permission.

-

-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE

-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF

-  THE POSSIBILITY OF SUCH DAMAGE.

-

-  This file is automatically generated. Please do NOT modify !!!

-

-**/

-

-#ifndef __FSP_VPD_H__

-#define __FSP_VPD_H__

-

-#pragma pack(1)

-

-

-

-typedef struct _UPD_DATA_REGION {

-  UINT64                      Signature;                     /* Offset 0x0000 */

-  UINT64                      Reserved;                      /* Offset 0x0008 */

-  UINT8                       UnusedUpdSpace0[16];           /* Offset 0x0010 */

-  UINT8                       PcdMrcInitTsegSize;            /* Offset 0x0020 */

-  UINT8                       PcdMemoryDown;                 /* Offset 0x0021 */

-  UINT8                       PcdMrcRmtSupport;              /* Offset 0x0022 */

-  UINT8                       PcdMrcRmtCpgcExpLoopCntValue;  /* Offset 0x0023 */

-  UINT8                       PcdMrcRmtCpgcNumBursts;        /* Offset 0x0024 */

-  UINT8                       PcdSpdBaseAddress_0_0;         /* Offset 0x0025 */

-  UINT8                       PcdSpdBaseAddress_0_1;         /* Offset 0x0026 */

-  UINT8                       PcdSpdBaseAddress_1_0;         /* Offset 0x0027 */

-  UINT8                       PcdSpdBaseAddress_1_1;         /* Offset 0x0028 */

-  UINT8                       PcdExtendedTemperatureEnable;  /* Offset 0x0029 */

-  UINT8                       PcdEnableRelaxedTurnaroundTiming; /* Offset 0x002A */

-  UINT8                       UnusedUpdSpace1[5];            /* Offset 0x002B */

-  UINT8                       PcdEnableLan;                  /* Offset 0x0030 */

-  UINT8                       PcdEnableSata2;                /* Offset 0x0031 */

-  UINT8                       PcdEnableSata3;                /* Offset 0x0032 */

-  UINT8                       PcdEnableIQAT;                 /* Offset 0x0033 */

-  UINT8                       PcdEnableUsb20;                /* Offset 0x0034 */

-  UINT8                       PcdBifurcation;                /* Offset 0x0035 */

-  UINT8                       PcdPcieRootPort1DeEmphasis;    /* Offset 0x0036 */

-  UINT8                       PcdPcieRootPort2DeEmphasis;    /* Offset 0x0037 */

-  UINT8                       PcdPcieRootPort3DeEmphasis;    /* Offset 0x0038 */

-  UINT8                       PcdPcieRootPort4DeEmphasis;    /* Offset 0x0039 */

-  UINT8                       UnusedUpdSpace2[6];            /* Offset 0x003A */

-  UINT8                       PcdPrintDebugMessages;         /* Offset 0x0040 */

-  UINT8                       PcdFastboot;                   /* Offset 0x0041 */

-  UINT8                       PcdEccSupport;                 /* Offset 0x0042 */

-  UINT8                       PcdSerialPortBaudRate;         /* Offset 0x0043 */

-  UINT32                      PcdMicrocodeRegionBase;        /* Offset 0x0044 */

-  UINT32                      PcdMicrocodeRegionSize;        /* Offset 0x0048 */

-  UINT8                       PcdCustomerRevision[32];       /* Offset 0x004C */

-  UINT32                      UnusedUpdSpace3;               /* Offset 0x006C */

-  UINT16                      PcdRegionTerminator;           /* Offset 0x0070 */

-} UPD_DATA_REGION;

-

-#define VPD_IMAGE_ID    0x562D474E524E5641        /* 'AVNRNG-V' */

-#define VPD_IMAGE_REV   0x00000150 

-

-typedef struct _VPD_DATA_REGION {

-  UINT64                      PcdVpdRegionSign;              /* Offset 0x0000 */

-  UINT32                      PcdImageRevision;              /* Offset 0x0008 */

-  UINT32                      PcdUpdRegionOffset;            /* Offset 0x000C */

-  UINT8                       UnusedVpdSpace0[16];           /* Offset 0x0010 */

-  UINT32                      PcdFspReservedMemoryLength;    /* Offset 0x0020 */

-  UINT8                       PcdSpdWriteProtect;            /* Offset 0x0024 */

-  UINT8                       PcdTcoEnable;                  /* Offset 0x0025 */

-} VPD_DATA_REGION;

-

-#pragma pack()

-

-#endif

+/** @file
+
+Copyright (C) 2017, Intel Corporation
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+  be used to endorse or promote products derived from this software without
+  specific prior written permission.
+
+  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+  THE POSSIBILITY OF SUCH DAMAGE.
+
+  This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSP_VPD_H__
+#define __FSP_VPD_H__
+
+#pragma pack(1)
+
+
+
+typedef struct _UPD_DATA_REGION {
+  UINT64                      Signature;                     /* Offset 0x0000 */
+  UINT64                      Reserved;                      /* Offset 0x0008 */
+  UINT8                       UnusedUpdSpace0[16];           /* Offset 0x0010 */
+  UINT8                       PcdMrcInitTsegSize;            /* Offset 0x0020 */
+  UINT8                       PcdMemoryDown;                 /* Offset 0x0021 */
+  UINT8                       PcdMrcRmtSupport;              /* Offset 0x0022 */
+  UINT8                       PcdMrcRmtCpgcExpLoopCntValue;  /* Offset 0x0023 */
+  UINT8                       PcdMrcRmtCpgcNumBursts;        /* Offset 0x0024 */
+  UINT8                       PcdSpdBaseAddress_0_0;         /* Offset 0x0025 */
+  UINT8                       PcdSpdBaseAddress_0_1;         /* Offset 0x0026 */
+  UINT8                       PcdSpdBaseAddress_1_0;         /* Offset 0x0027 */
+  UINT8                       PcdSpdBaseAddress_1_1;         /* Offset 0x0028 */
+  UINT8                       PcdExtendedTemperatureEnable;  /* Offset 0x0029 */
+  UINT8                       PcdEnableRelaxedTurnaroundTiming; /* Offset 0x002A */
+  UINT8                       UnusedUpdSpace1[5];            /* Offset 0x002B */
+  UINT8                       PcdEnableLan;                  /* Offset 0x0030 */
+  UINT8                       PcdEnableSata2;                /* Offset 0x0031 */
+  UINT8                       PcdEnableSata3;                /* Offset 0x0032 */
+  UINT8                       PcdEnableIQAT;                 /* Offset 0x0033 */
+  UINT8                       PcdEnableUsb20;                /* Offset 0x0034 */
+  UINT8                       PcdBifurcation;                /* Offset 0x0035 */
+  UINT8                       PcdPcieRootPort1DeEmphasis;    /* Offset 0x0036 */
+  UINT8                       PcdPcieRootPort2DeEmphasis;    /* Offset 0x0037 */
+  UINT8                       PcdPcieRootPort3DeEmphasis;    /* Offset 0x0038 */
+  UINT8                       PcdPcieRootPort4DeEmphasis;    /* Offset 0x0039 */
+  UINT8                       UnusedUpdSpace2[6];            /* Offset 0x003A */
+  UINT8                       PcdPrintDebugMessages;         /* Offset 0x0040 */
+  UINT8                       PcdFastboot;                   /* Offset 0x0041 */
+  UINT8                       PcdEccSupport;                 /* Offset 0x0042 */
+  UINT8                       PcdSerialPortBaudRate;         /* Offset 0x0043 */
+  UINT32                      PcdMicrocodeRegionBase;        /* Offset 0x0044 */
+  UINT32                      PcdMicrocodeRegionSize;        /* Offset 0x0048 */
+  UINT8                       PcdCustomerRevision[32];       /* Offset 0x004C */
+  UINT32                      UnusedUpdSpace3;               /* Offset 0x006C */
+  UINT16                      PcdRegionTerminator;           /* Offset 0x0070 */
+} UPD_DATA_REGION;
+
+#define VPD_IMAGE_ID    0x562D474E524E5641        /* 'AVNRNG-V' */
+#define VPD_IMAGE_REV   0x00000160 
+
+typedef struct _VPD_DATA_REGION {
+  UINT64                      PcdVpdRegionSign;              /* Offset 0x0000 */
+  UINT32                      PcdImageRevision;              /* Offset 0x0008 */
+  UINT32                      PcdUpdRegionOffset;            /* Offset 0x000C */
+  UINT8                       UnusedVpdSpace0[16];           /* Offset 0x0010 */
+  UINT32                      PcdFspReservedMemoryLength;    /* Offset 0x0020 */
+  UINT8                       PcdSpdWriteProtect;            /* Offset 0x0024 */
+  UINT8                       PcdTcoEnable;                  /* Offset 0x0025 */
+} VPD_DATA_REGION;
+
+#pragma pack()
+
+#endif
diff --git a/RangeleyFspBinPkg/SampleCode/fsphob.c b/RangeleyFspBinPkg/SampleCode/fsphob.c
index 4986d52..4986d52 100755..100644
--- a/RangeleyFspBinPkg/SampleCode/fsphob.c
+++ b/RangeleyFspBinPkg/SampleCode/fsphob.c
diff --git a/RangeleyFspBinPkg/SampleCode/fspsupport.c b/RangeleyFspBinPkg/SampleCode/fspsupport.c
index 9f15b3e..9f15b3e 100755..100644
--- a/RangeleyFspBinPkg/SampleCode/fspsupport.c
+++ b/RangeleyFspBinPkg/SampleCode/fspsupport.c