Updated to Denverton-NS FSP Production Validated 003DenvertonNS

5 files changed, 114 insertions, 2 deletions

diff --git a/DenvertonNSFspBinPkg/Docs/DenvertonNSFspIntegrationGuide.pdf b/DenvertonNSFspBinPkg/Docs/DenvertonNSFspIntegrationGuide.pdf
index eb577e1..54393ba 100644
--- a/DenvertonNSFspBinPkg/Docs/DenvertonNSFspIntegrationGuide.pdf
+++ b/DenvertonNSFspBinPkg/Docs/DenvertonNSFspIntegrationGuide.pdf
diff --git a/DenvertonNSFspBinPkg/Docs/DenvertonNSFspReleaseNotes.pdf b/DenvertonNSFspBinPkg/Docs/DenvertonNSFspReleaseNotes.pdf
index 60e561c..2e6496d 100644
--- a/DenvertonNSFspBinPkg/Docs/DenvertonNSFspReleaseNotes.pdf
+++ b/DenvertonNSFspBinPkg/Docs/DenvertonNSFspReleaseNotes.pdf
diff --git a/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.bsf b/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.bsf
index eafdf0f..49bd8b4 100644
--- a/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.bsf
+++ b/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.bsf
@@ -118,6 +118,14 @@ StructDef
         $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort5Aspm       1 bytes    $_DEFAULT_ = 0x02

         $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort6Aspm       1 bytes    $_DEFAULT_ = 0x02

         $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7Aspm       1 bytes    $_DEFAULT_ = 0x02

+        $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort0LaneReversal   1 bytes    $_DEFAULT_ = 0

+        $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort1LaneReversal   1 bytes    $_DEFAULT_ = 0

+        $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort2LaneReversal   1 bytes    $_DEFAULT_ = 0

+        $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort3LaneReversal   1 bytes    $_DEFAULT_ = 0

+        $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort4LaneReversal   1 bytes    $_DEFAULT_ = 0

+        $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort5LaneReversal   1 bytes    $_DEFAULT_ = 0

+        $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort6LaneReversal   1 bytes    $_DEFAULT_ = 0

+        $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort7LaneReversal   1 bytes    $_DEFAULT_ = 0

 

 EndStruct

 

@@ -180,6 +188,11 @@ List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdActiveCoreCount
     Selection 15 , "15"

 EndList

 

+List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort2LaneReversal

+    Selection 0 , "Disabled"

+    Selection 1 , "Enabled"

+EndList

+

 List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort1Aspm

     Selection 0 , "Disabled"

     Selection 2 , "L1"

@@ -243,11 +256,21 @@ List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3LinkSpeed
     Selection 3 , "GEN3"

 EndList

 

+List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort0LaneReversal

+    Selection 0 , "Disabled"

+    Selection 1 , "Enabled"

+EndList

+

 List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort3DeEmphasis

     Selection 0 , "6dB"

     Selection 1 , "3.5dB"

 EndList

 

+List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort3LaneReversal

+    Selection 0 , "Disabled"

+    Selection 1 , "Enabled"

+EndList

+

 List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort2Aspm

     Selection 0 , "Disabled"

     Selection 2 , "L1"

@@ -292,6 +315,16 @@ List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdDdrFreq
     Selection 6 , "2400"

 EndList

 

+List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort6LaneReversal

+    Selection 0 , "Disabled"

+    Selection 1 , "Enabled"

+EndList

+

+List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort4LaneReversal

+    Selection 0 , "Disabled"

+    Selection 1 , "Enabled"

+EndList

+

 List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdMrcRmtCpgcNumBursts

     Selection 1 , "1"

     Selection 2 , "2"

@@ -326,6 +359,11 @@ List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port2Pin
     Selection 8 , "No pin mapped"

 EndList

 

+List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort1LaneReversal

+    Selection 0 , "Disabled"

+    Selection 1 , "Enabled"

+EndList

+

 List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdFsptPort80RouteDisable

     Selection 0 , "VPD-Style"

     Selection 1 , "Enable Port80 Output[Default]"

@@ -362,6 +400,11 @@ List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb3Port1Pin
     Selection 8 , "No pin mapped"

 EndList

 

+List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort5LaneReversal

+    Selection 0 , "Disabled"

+    Selection 1 , "Enabled"

+EndList

+

 List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7Aspm

     Selection 0 , "Disabled"

     Selection 2 , "L1"

@@ -414,6 +457,11 @@ List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdUsb2Port3Pin
     Selection 8 , "No pin mapped"

 EndList

 

+List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort7LaneReversal

+    Selection 0 , "Disabled"

+    Selection 1 , "Enabled"

+EndList

+

 List &gHarrisonvilleFspPkgTokenSpaceGuid_PcdEnableGbE

     Selection 0 , "Disable LAN 0 & LAN 1"

     Selection 1 , "Enable LAN 0 & LAN 1"

@@ -502,6 +550,22 @@ Page "SoC"
         Help "Enable PCI Express Active State Power Management settings"

     Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7Aspm, "PCIe Root Port 7 ASPM", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdPcieRootPort7Aspm,

         Help "Enable PCI Express Active State Power Management settings"

+    Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort0LaneReversal, "PCIe Root Port 0 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort0LaneReversal,

+        Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"

+    Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort1LaneReversal, "PCIe Root Port 1 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort1LaneReversal,

+        Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"

+    Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort2LaneReversal, "PCIe Root Port 2 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort2LaneReversal,

+        Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"

+    Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort3LaneReversal, "PCIe Root Port 3 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort3LaneReversal,

+        Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"

+    Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort4LaneReversal, "PCIe Root Port 4 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort4LaneReversal,

+        Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"

+    Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort5LaneReversal, "PCIe Root Port 5 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort5LaneReversal,

+        Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"

+    Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort6LaneReversal, "PCIe Root Port 6 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort6LaneReversal,

+        Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"

+    Combo $gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort7LaneReversal, "PCIe Root Port 7 Lane Reversal", &gHarrisonvilleFspPkgTokenSpaceGuid_PcdRootPort7LaneReversal,

+        Help "Enable / Disable Dynamic Lane reversal on PCI Express RootPort"

 EndPage

 

 Page "Platform Specific"

diff --git a/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd b/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd
index 8696f0a..f1c6b59 100644
--- a/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd
+++ b/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd
diff --git a/DenvertonNSFspBinPkg/Include/FspsUpd.h b/DenvertonNSFspBinPkg/Include/FspsUpd.h
index 71ac9cf..02f61df 100644
--- a/DenvertonNSFspBinPkg/Include/FspsUpd.h
+++ b/DenvertonNSFspBinPkg/Include/FspsUpd.h
@@ -253,9 +253,57 @@ typedef struct {
 **/

   UINT8                       PcdPcieRootPort7Aspm;

 

-/** Offset 0x0054

+/** Offset 0x0054 - PCIe Root Port 0 Lane Reversal

+  Enable / Disable Dynamic Lane reversal on PCI Express RootPort

+  0:Disabled, 1:Enabled

 **/

-  UINT8                       UnusedUpdSpace2[140];

+  UINT8                       PcdRootPort0LaneReversal;

+

+/** Offset 0x0055 - PCIe Root Port 1 Lane Reversal

+  Enable / Disable Dynamic Lane reversal on PCI Express RootPort

+  0:Disabled, 1:Enabled

+**/

+  UINT8                       PcdRootPort1LaneReversal;

+

+/** Offset 0x0056 - PCIe Root Port 2 Lane Reversal

+  Enable / Disable Dynamic Lane reversal on PCI Express RootPort

+  0:Disabled, 1:Enabled

+**/

+  UINT8                       PcdRootPort2LaneReversal;

+

+/** Offset 0x0057 - PCIe Root Port 3 Lane Reversal

+  Enable / Disable Dynamic Lane reversal on PCI Express RootPort

+  0:Disabled, 1:Enabled

+**/

+  UINT8                       PcdRootPort3LaneReversal;

+

+/** Offset 0x0058 - PCIe Root Port 4 Lane Reversal

+  Enable / Disable Dynamic Lane reversal on PCI Express RootPort

+  0:Disabled, 1:Enabled

+**/

+  UINT8                       PcdRootPort4LaneReversal;

+

+/** Offset 0x0059 - PCIe Root Port 5 Lane Reversal

+  Enable / Disable Dynamic Lane reversal on PCI Express RootPort

+  0:Disabled, 1:Enabled

+**/

+  UINT8                       PcdRootPort5LaneReversal;

+

+/** Offset 0x005A - PCIe Root Port 6 Lane Reversal

+  Enable / Disable Dynamic Lane reversal on PCI Express RootPort

+  0:Disabled, 1:Enabled

+**/

+  UINT8                       PcdRootPort6LaneReversal;

+

+/** Offset 0x005B - PCIe Root Port 7 Lane Reversal

+  Enable / Disable Dynamic Lane reversal on PCI Express RootPort

+  0:Disabled, 1:Enabled

+**/

+  UINT8                       PcdRootPort7LaneReversal;

+

+/** Offset 0x005C

+**/

+  UINT8                       UnusedUpdSpace2[132];

 

 /** Offset 0x00E0

 **/