meta-nuvoton: npcm8xx-bootloader: update IGPS to 04.03.08

IGPS 04.03.08 - Jul 31th 2025
============
- SystemControlFlags on L1 - added bits 5+6.
  5 controls the ability to disable the UART log printing (1 = to disable)
  6 controls the new option to write the log to an address in the memory
- SystemControlFlags on L0 - added bits 0 or 1 to control the print to
  uart \ memory, added log size and address as well.
- Fix Lms flags configuration on programmer monitor generation
  (left over from previews transition to .json file)
- Fuse map XML file:
  * Edit the mask of
  * Add PQA 1 field
- SKMT keys: removed SKMT ECC keys 2-3-4. we only use 0+1,
  change SKMT LMS keys 5-6 to 2-3. Udpated both SKMT XMLs (ECC + LMS)
- Pad value: changed to 0 instead of 0xFF for L0 XML.
- TIP_FW 0.8.2 L0 0.7.1 L1
  * Added option to write the log to the memory instead and as addition to UART,
    using a flag from the L0 XML header and using the system flags on L1.
  * Added Baud rate 750000 option.
  * Added serial_printf_setup function that will include code from both
    serial_printf_init & serial_printf_reconfig.
  * Update CLK and UART drv code to latest HAL.
  * Supports AES, RNG, Flash, and FW update proxy commands to provide crypto
    services for A35. Code is under BMC_DIRECT flag, disabled by default.
  * SKMT keys: revert the manifest key to be the last one.
  * Split GCM AES from all the rest of AES engine. Remove GCM calls from main AES engine.
  * Bug fix: clear the SCRPAD mutex during init, for the case it's set previously.
- LMS Changes:
  * Check the KMT valid key only if the key is ECC, not LMS
  * ECC verification needs sha alg enum, while LMS needs the digest length
  * Remove the 2nd keyindex loop
- Bootblock 0.5.6
  * Add the flag "-ftrack-macro-expansion=0" (easier for handling compilation errors).
  * Print chip revision flag correctly for A3.
  * Lock DRAM memory regions. TIP region is locked for tip mode only.
    - No change in NO_TIP mode.
  * Bug fix: reset UART FIFOs during serial_printf_init to avoid UART stuck
    when switching to 720MHz.
- Register tables: set RCR locks on any reset (0x9FF instead of 0x100).
  * Add bit 11 for WOL reset handling.
- Production scripts:
  * version numbder will be without 0s. (4.3.8 and not 04.03.08)
  * gerVersion.bat will look on \aglick as well as \tperry
- Uboot v2023.10-npcm8xx-20250728
  * Add configuration of SPI Chip select for Recovery boot ENV.
  * Support configurable VCD input source.
  * Add PCIE-RC driver.
- Programmer monitor 1.1.6 - supports A3.

Tested:
Build pass and boot up successful with correct TIP FW latest version

Signed-off-by: Tali Perry <tali.perry@nuvoton.com>
Signed-off-by: Adi Glick <adi.glick@nuvoton.com>
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: I4ce588463f15019955342ff0a829b02299d1fc14

0 files changed, 0 insertions, 0 deletions