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| author | Andrew Geissler <geissonator@yahoo.com> | 2025-04-07 17:05:06 +0300 |
|---|---|---|
| committer | Andrew Geissler <geissonator@yahoo.com> | 2025-04-11 16:57:35 +0300 |
| commit | c9ad1a671eb676e797d4f70251ca88ec58fe05e7 (patch) | |
| tree | 9c7c76bd2fd7b9769dc8340e3974e93f4e31b504 /meta-openembedded/meta-python/recipes-devtools/python/python3-grpcio/0001-Include-missing-cstdint-header.patch | |
| parent | 26e2777c444df35338cf33b6e7a113ada1dec63d (diff) | |
| download | openbmc-c9ad1a671eb676e797d4f70251ca88ec58fe05e7.tar.xz | |
meta-ibm: meta-system1: Increase pgood timeout
The system1 FPGA requires more then 10s to power on at times. Increase
timeout to maximum, 30s.
Change-Id: Ib4a42e692712292e5cdf2f16b3968ba3f30ba1fd
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
Diffstat (limited to 'meta-openembedded/meta-python/recipes-devtools/python/python3-grpcio/0001-Include-missing-cstdint-header.patch')
0 files changed, 0 insertions, 0 deletions