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| author | Tim Lee <timlee660101@gmail.com> | 2024-12-17 06:53:24 +0300 |
|---|---|---|
| committer | Tim Lee <chli30@nuvoton.com> | 2024-12-17 06:57:13 +0300 |
| commit | 6a61b56f3884a484b2738e42d8962de6881fe89c (patch) | |
| tree | 70d3eae1e5e997a86d67ba7303c2896344760ea3 /meta-openembedded/meta-python/recipes-devtools/python/python3-grpcio/0001-Include-missing-cstdint-header.patch | |
| parent | fbcdbb9c59d93b2887b3de8b66d52349073f6939 (diff) | |
| download | openbmc-6a61b56f3884a484b2738e42d8962de6881fe89c.tar.xz | |
meta-nuvoton: npcm8xx-bootloader: update IGPS to 04.02.07
IGPS 04.02.07 - Dec 10th 2024
============
- bootblock 0.5.4
* Add two new header fields:
- pll0_override: can be used to set pll0, unless CPU != MC
frequency. In this case override would fail.
- i3c divider. once it's set P.eCI root complex will not function
anymore. Recommendation for I3C users: set CPU = MC = 1000,
pll0_override = 625, i3c_div = 13.For RC users: pll0_override = 0,
i3c_div = 0xFF.
* Add MC support for 300MHz.
* Add CPU support for 325MHz, 625MHz.
- XML: add field for pll0_override and i3c_div.
BootBlockAndHeader_A1_MS.xml will set I3C at 48MHz.
- All other XMLs set to 100MHz needed for Root Complex.
- Put all LMS keys as place-holder, both in the fuse XML and in the
folder.
Tested:
Build pass and boot up successful with correct BB/TIP FW latest version.
Signed-off-by: Tali Perry <tali.perry@nuvoton.com>
Signed-off-by: Tim Lee <timlee660101@gmail.com>
Change-Id: Ia20d10b72856b88cc1374a2734d528e49a6bb89e
Diffstat (limited to 'meta-openembedded/meta-python/recipes-devtools/python/python3-grpcio/0001-Include-missing-cstdint-header.patch')
0 files changed, 0 insertions, 0 deletions