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| author | Rex Fu <Rex.Fu@amd.com> | 2026-05-28 11:45:23 +0300 |
|---|---|---|
| committer | Patrick Williams <patrick@stwcx.xyz> | 2026-06-05 19:30:27 +0300 |
| commit | 2593309ad2712da6c2dbde894db10cc6384cdfa4 (patch) | |
| tree | 343f2c4f2a0725e6a13bef5c4ee4990a87d73121 /upstream-layers/meta-openembedded/meta-python/recipes-devtools/python/python3-matplotlib-inline_0.2.2.bb | |
| parent | 77dcd4460c2b731aa46930e58d79452894473d8f (diff) | |
| download | openbmc-2593309ad2712da6c2dbde894db10cc6384cdfa4.tar.xz | |
meta-facebook: anacapa: Decode DIMM power faults on PG timeout
Use DIMM_PMIC_PG_TIMEOUT as the CPLD-reported DIMM power-good timeout
trigger. When asserted, read CPLD register 0x24 and log a PowerRailFault
event for each rail whose corresponding power-good bit is low.
Tested:
- Verified CPLD register 0x24 is used to decode DIMM power-good status.
- Verified bit value 0 generates a PowerRailFault event for the matching
DIMM power rail.
- Verified multiple low bits generate multiple PowerRailFault events.
Change-Id: I7aebf54135e9f8196beaacd204ce31d63ed65625
Signed-off-by: Rex Fu <Rex.Fu@amd.com>
Diffstat (limited to 'upstream-layers/meta-openembedded/meta-python/recipes-devtools/python/python3-matplotlib-inline_0.2.2.bb')
0 files changed, 0 insertions, 0 deletions