meta-facebook: rainiera7: Add RSE MCTP readiness

The updated SoC firmware uses C0 POST 0x1C to indicate that the BMC
may start MCTP-over-I3C setup. The existing monitor stops at the old
terminal codes and does not publish this readiness.

Adapt the RSE POST monitor from the SoC implementation.
Set readiness when the C0 raw POST code reaches 0x1C or later, and
stop monitoring at C0 0x1F and C1 raw 0x1C. Preserve the C1 offset
of 0x20 when publishing Boot.Raw.

Store readiness in /run/rainier/mctp_i3c_link_ready and clear it
from ExecStopPost when the monitor is stopped. Keep the service
active after polling completes so host-stop processing can run
cleanup. Retain Rainier's GPIO chip discovery and environment
configuration.

Evaluate readiness before handling an initial terminal POST code
so a BMC reboot can recover the link without a new host POST cycle.

This prepares the readiness source for the subsequent MCTP
lifecycle change without replacing the existing activation path.

Tested: With the lifecycle integration on Rainier A7:
- C0 reached 0x1C before MCTP initialization.
- C1 raw 0x1C was published as 0x3C and polling completed.
- Host stop cleared readiness.
- An initial C0 0x1F allowed recovery after a BMC reboot.

Change-Id: I380e0606fd17f478d8519a334c0e3152033ccdb4
Signed-off-by: Alan Tsai <alan-tsai@quantatw.com>
Co-authored-by: Manoj Kumar Prabakaran <manojkumar.prabakaran@arm.com>

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